Linearity Distortion Analysis Research Articles

Linear Distortion Analysis of 3D Double Gate Junctionless Transistor with High-K Dielectrics and Gate Metals

The paper presents the investigation of linearity distortion analysis of double gate junctionless transistor with high-k gate dielectrics and gate metals. As double gate junctionless transistors have shown high performance in digital circuits, linearity analysis is carried out to understand nonlinear behavior of the device for RFIC applications. In order to ensure minimum intermodulation and higher order harmonics at the system output, different linearity parameters like Second Order Voltage Intercept Point, Third Order distortion, Third Order Input Intercept Point and Third Order Intermodulation Distortion are evaluated. The results show that junctionless transistor should be biased at appropriate low voltage to ensure better linearity which is desired for RFICs. The effects of high-k gate dielectrics and gate metals on linearity characteristics of junctionless transistor are also investigated. Deterioration of the linearity is observed in junctionless transistor for the use of high-k insulators as gate dielectrics. It is also observed that low work function gate material is suitable to achieve higher linearity in low power applications.

Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.

Temperature Dependent Performance Evaluation and Linearity Analysis of Double Gate-all-around (DGAA) MOSFET: an Advance Multigate Structure

Multi-gate devices such as double gate, FinFET and Gate-All-Around (GAA) are potential candidates to achieve the performance expected by semiconductor association. This paper presents an analog/RF performance and linearity distortion analysis for an advance multigate structure named Double Gate-All-Around (DGAA) MOSFET. Temperature dependent characteristics of the DGAA MOSFET have also been investigated in detail from 200 K to 400 K. A comparative analysis between Gate-All-Around (GAA) and DGAA MOSFETs with impact of silicon film thickness is analyzed by using 3-D ATLAS TCAD device simulator. It is demonstrated that depending on gate voltage, DGAA MOSFET has larger value of drain current (Ids), transconductance (gm) and gain. Results demonstrate that drain current, transconductance, device gain and transconductance to drain current ratio (gm/Ids) improves when temperature is decreased. DGAA MOSFET shows improvement in analog/RF performance, suppressed Short Channel Effects (SCEs) and harmonics distortions due to more gate controllability on the channel charge.

Linearity Distortion Analysis of III–V and Si Quadruple Gate Field Effect Transistor (QG-FET) for Analog Applications

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.

Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications

Junctionless double gate (JLDG) MOSFET in sub nano meter regime has been the preferred choice for researchers as the leakage current in a JLDG MOSFET is significantly less compared to junction based double gate (DG) MOSFET. Also since the conduction mechanism in JLDG MOSFET is bulk conduction instead of surface channel conduction, the short channel effects (SCEs) get significantly reduced. In this research paper, major reliability issues concerning JLDG MOSFET has been studied and discussed. This research paper considers the gate misalignment effect and analysis of the thermal stability by subjecting the temperature variation from 200K to 500K. Gate misalignments is one of the major reliability issues and with enhancement in second order effects, it causes reduction in on current that degrades the performance of a JLDG MOSFET. The alignment between front and back gate critically influences the performance of a JLDG device. Misalignment effect in the device occurs due to shift in the back gate either towards the drain side or the source side. The gate misalignment therefore introduces some non-ideal effects from overlap or non-overlap regions. Thermal stability of the device has been tested for operating the device over a wide range of temperatures ranging from 200K to 500K, so that the effect of temperature on the performance issues remains limited. Further, the analog/RF performance parameters have been evaluated and linearity distortion analysis due to gate misalignment effect in terms of major performance matrices has been investigated. The investigated results show that there exist a thermally stable point in and around which if the device operates would be more stable.

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , transconductance frequency product, higher order transconductance coefficients (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m1</sub> , g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> ), VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HDGAA-TFET is more immune toward the interface trap charges present at the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Performance Evaluation and Reliability Issues of Junctionless CSG MOSFET for RFIC Design

This paper investigates the reliability issues of junctionless cylindrical surrounding-gate (JL CSG) MOSFET by employing temperature variations, ranging from 200 K to 500 K, along with the influence of interface trap charges. Furthermore, the analog/RF performance evaluation and linearity distortion analysis due to the interface trap charges in terms of figure-of-merit metrics, i.e., drain current Ids; intrinsic gain (gm/gd) Ion/Ioff ; cutoff frequency fT; gain; gain transconductance frequency product; IMD3; VIP2; VIP3; IIP3; and higher order transconductance coefficients gm1, gm2, and gm3 of JL CSG MOSFET have been carried out. A direct comparative study in terms of performance degradation is made between gate material engineered (GME) and single-material gate (SMG) JL CSG MOSFET using ATLAS 3-D device simulator. Simulation results reveal that a GME JL transistor shows better immunity against the influence of interface trap charges and exhibits significant enhancement to maintain device linearization, as compared to an SMG JL CSG MOSFET, so that it can be used as a high-efficiency linear radio-frequency integrated-circuit design and wireless applications. Also from simulation study, degrading effects in JL CSG MOSFET are more pronounce at low temperature and subthreshold region. Apart from analog/RF performance, trap charges change the temperature sensitivity coefficient of the drain current and zero crossover point.