Line Width Roughness Research Articles

Process Optimization on Self-Aligned Double Patterned Fin Formation

In this work, we focused on self-aligned-double-patterning (SaDP) Fin etch process and investigated some well-known issues such as dense-isolated loading, pitch-walking performance and line width roughness (LWR) from the point of view of various advanced plasma techniques. Results indicate the introduction of bias pulsing scheme and mixed mode pulsing (MMP) could rigorously control the loading between dense and isolated patterns for the formation of both mandrel and Fin. The synchronous pulsing scheme has also been demonstrated to play an important role on the formation of almost flat spacer top in spacer etch. This could definitely benefit the subsequent pitch walking performance. Besides, we also attempted various techniques such as core material, plasma ribbon beam and chemical down-stream etch (CDE) to improve mandrel LWR. Finally, we demonstrated Fin formation could be greatly improved.

Simulation study of the effect of molar mass dispersity on domain interfacial roughness in lamellae forming block copolymers for directed self-assembly

A coarse-grained molecular dynamics model was used to study the thin film self-assembly and resulting pattern properties of block copolymer (BCP) systems with various molar mass dispersities. Diblock copolymers (i.e. A–b–B type) were simulated in an aligned lamellar state, which is one of the most common patterns of potential use for integrated circuit fabrication via directed self-assembly of BCPs. Effects of the molar mass dispersity (Ð) on feature pitch and interfacial roughness, which are critical lithographic parameters that have a direct impact on integrated circuit performance, were simulated. It was found that for a realistic distribution of polymer molecular weights, modeled by a Wesslau distribution, both line edge roughness (LER) and line width roughness (LWR) increase approximately linearly with increasing Ð, up to ∼45% of the monodisperse value at Ð = 1.5. Mechanisms of compensation for increased A–A and B–B roughness were considered. It was found that long and short chain positions were not correlated, and that long chains were significantly deformed in shape. The increase in LWR was due to the increase in LER and a constant correlation between the line edges. Unaligned systems show a correlation between domain width and local molecular weight, while systems aligned on an alternating pattern of A and B lines did not show any correlation. When the volume fraction of individual chains was allowed to vary, similar results were found when considering the Ð of the block as opposed to the Ð of the entire system.

Automated Defect and Correlation Length Analysis of Block Copolymer Thin Film Nanopatterns.

Line patterns produced by lamellae- and cylinder-forming block copolymer (BCP) thin films are of widespread interest for their potential to enable nanoscale patterning over large areas. In order for such patterning methods to effectively integrate with current technologies, the resulting patterns need to have low defect densities, and be produced in a short timescale. To understand whether a given polymer or annealing method might potentially meet such challenges, it is necessary to examine the evolution of defects. Unfortunately, few tools are readily available to researchers, particularly those engaged in the synthesis and design of new polymeric systems with the potential for patterning, to measure defects in such line patterns. To this end, we present an image analysis tool, which we have developed and made available, to measure the characteristics of such patterns in an automated fashion. Additionally we apply the tool to six cylinder-forming polystyrene-block-poly(2-vinylpyridine) polymers thermally annealed to explore the relationship between the size of each polymer and measured characteristics including line period, line-width, defect density, line-edge roughness (LER), line-width roughness (LWR), and correlation length. Finally, we explore the line-edge roughness, line-width roughness, defect density, and correlation length as a function of the image area sampled to determine each in a more rigorous fashion.

More systematic errors in the measurement of power spectral density

Power spectral density (PSD) analysis is an important part of understanding line-edge and linewidth roughness in lithography. But uncertainty in the measured PSD, both random and systematic, complicates inter- pretation. It is essential to understand and quantify the sources of the measured PSD's uncertainty and to develop mitigation strategies. Both analytical derivations and simulations of rough features are used to evaluate data window functions for reducing spectral leakage and to understand the impact of data detrending on biases in PSD, autocovariance function (ACF), and height-to-height covariance function measurement. A generalized Welch window was found to be best among the windows tested. Linear detrending for line-edge roughness measurement results in underestimation of the low-frequency PSD and errors in the ACF and height-to-height covariance function. Measuring multiple edges per scanning electron microscope image reduces this detrending

Understanding the efficacy of linewidth roughness postprocessing

Lack of progress in reducing linewidth roughness of lithographic features has led to investigations of the use of postlithography process smoothing techniques. However, it remains unclear whether such postprocessing will sufficiently reduce the detrimental effects of feature roughness. Thus, there is a need to understand the efficacy of postprocessing on not just roughness reduction, but on the negative device impacts of roughness. We derive model equations of how roughness impacts lithographic performance and incorporates smoothing using postprocessing. These models clearly show that postprocess smoothing works best by increasing the correlation length. Increasing the correlation length is very effective at reducing high-frequency roughness that impacts within-feature variations but is less effective at reducing low-frequency roughness that impacts feature-to-feature variations. It seems that postprocess smoothing is not a substitute for reducing the initial roughness of resist features.

Line edge roughness frequency analysis during pattern transfer in semiconductor fabrication

Line edge roughness (LER) and line width roughness (LWR) are analyzed based on the frequency domain 3σ LER characterization methodology during pattern transfer in a self-aligned double patterning (SADP) process. The power spectrum of the LER/LWR is divided into three regions: low frequency, middle frequency, and high frequency regions. Three standard deviation numbers are used to characterize the LER/LWR in the three frequency regions. Pattern wiggling is also detected quantitatively during LER/LWR transfer in the SADP process.

Process Optimization on Self-Aligned Double Patterned Fin Formation

As the feature size of integrated circuit (IC) keeps shrinking, self-aligned double patterning (SADP) has been widely used in 14nm technology node and beyond.[1] In SADP Fin etch,the precise pattern transfer is critical for the robust device performance. However, compared with single patterning scheme, SADP poses more challenges from the point of view of even/odd issue, RIE-lag loading and line width roughness (LWR) control.In this work,we delivered the overall solution by introducing the bias pulsing plasma etch and mixed mode pulsing(MMP) concept in mandrel and shallow trench isolation (STI) to address the rigorous loading control [2] between dense and isolated patterns, the synchronous pulsing scheme to form the spacer with almost flat spacer top, thus benefiting the even/odd performance in SADP fin etch. Besides,we also investigated the effects of plasma ribbon beam[3], chemical down-stream etch (CDE) and high conductance on LWR improvement, respectively. Rigorous loading control at dense and isolated patterns is important to ensure the robust device performance.This is especially true at sub20nm technology node. In SADP Fin etch, the dense-isolated loading (including CD, depth and sidewall angle) mainly comes from mandrel etch and STI etch process. As is well known, etch by-product deposition mode behaves quite differently between dense and isolated area. In traditional continuous wave (CW) plasma, it’s quite hard to tackle such notorious loading for its inherent high Te induced ionization. While, the bias pulsing plasma paves the way to alleviate such toggled loading for less bombardment during the bias-off period could reduce the etch by-product formation to some extent.Moreover, MMP plasma enables precise etch process control by repeatedly resetting each phase to initial state which could eliminate most of process induced loading accumulation.Based on the above learning, we induced MMP concept in STI etch process and successfully developed a well-controlled loading performance on Fin (shown in Fig1). In SADP Fin etch,both spacer top profile and mandrel performance are extremely critical to final even/odd performance. On one hand, the mandrel performance could result in the difference of depth and line edge roughness (LER) between mandrel space and spacer space as schematically shown in Fig 2a. Such even/odd distribution could finally introduce the huge variation of the effective Fin height. Among three different mandrel materials, we found such even/odd issue could be improved by means of mandrel material selection.On the other hand, traditional spacer etch process usually delivers the undesired spacer shoulder loss(schematically shown in Fig2a).Such asymmetric spacer height pattern could be directly transferred to Fin formation and easily induce the asymmetric stress distribution on Fin, which could potentially lead to Fin distortion. Here, we resorted to the synchronous pulsing scheme to reshape the spacer top profile without the excessive loss of spacer height. LWR has aroused much attention as CMOS is being scaled down to FinFET. Both high frequency LWR and low frequency LWR have to be addressed at mandrel definition as the LWR of ALD spacer strongly depend on mandrel LWR. We leveraged plasma ribbon beam to improve low-frequency LWR of photo resist and did achieve the remarkable improvement. However, the substrate damage and photo resist loss need special method such as synchronous pulsing scheme to reduce photo resist loss during etch process. Besides, CDE was used to improve high-frequency LWR at mandrel and Fin. However, the result is quite different between them. 30% LWR reduction could be seen on Fin while it does NOT work on mandrel at all. This might come from the material difference or insufficient CD loss. Last but not least, mandrel etch itself could deliver better high LWR performance with high conductance and special photo resist treatment. ACKNOWLEDGMENT This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).

(Invited) Nano-Controlled Etching of Polycrystalline Metals - a Key Enabler for Future Technologies

As Moore's law continues its relentless march, defying odds of its predicted demise well in to more than a decade, innovations are required to enable 10 nm and beyond technology nodes. The capability to etch polycrystalline metals with an unprecedented nanometer scale control offers unique challenges at the forefront of mechanistic and structural understanding of chemical reactivity and kinetics. Since the advent of Cu-based interconnects embedded in low-k dielectrics, the landscape of BEOL cleans has focused on development of process technologies that were aimed at enhancing metal compatibility in highly corrosive media. Fluorocarbon plasma-based etches and ashes needed to pattern interlayer vias leave behind a chemically-susceptible dielectric, surface modified metals, locally corrosive environments and copious amounts of etch polymer. Advanced formulations for BEOL via cleans incorporated metal corrosion inhibitors, buffering agents for precise pH control, additives for surface tension control and carefully selected solvent systems for precisely tuned viscosity control. Removal of post-plasma-etch residues with metal compatibility remained a finely tuned balancing act between clean wafers and undamaged wiring. Capping of the interconnect wires by selective metal growth as shown in Figure 1 has been extensively researched. While its benefits and limitations are beyond the scope of discussion here, two critical yield impactors, nodules of non-selective metal growth and protrusions of capping metal beyond the CD of the patterned line, are shown schematically in Figure 1. The scheme shown in Figure 2 relies on nano-controlled wet etching of the polycrystalline Cu in the line to create a recessed cavity which may be capped with a metal of choice followed by polishing to yield a capped metal flush with the dielectric. This scheme has the potential to realize benefits of metal capping without the yield-limiting defects shown in Figure 1. In this paper, we describe the development of a liquid phase chemical solution to etch a solid polycrystalline metal line composed of grains with potentially different sizes, orientations, phases, textures and inherently anisotropic grain boundaries with nanometer scale precision to yield a non-pitted and smooth metal surface with a RMS roughness of ~ 1.2 nm. Rates and mechanisms of metal dissolution reactions, in both acidic and basic media, are highly sensitive to dissolved oxygen concentration and the mass-transport of reactants and products. Development of etchant chemistry involved optimization of the chemistry components along with tool parameters to yield the process on a 300 mm wafer with < 3 nm center to edge etch depth uniformity (shown in Figure 3). Use of dopants to improve electromigration (EM) performance of Cu-interconnects has been a fairly standard practice in the semiconductor industry. Within the context of understanding dissolution of Cu lines with added EM-dopant, we observed somewhat expectedly, drastic differences in etch rates and profiles using the same chemical etch solution. The barrier metal, in direct contact with the Cu line, was also found to influence the mechanism and profile of metal etching. While Ta-based barriers yielded uniform etch rates in the middle of the Cu line relative to the edges, Ru-based barriers showed effects of galvanically-accelerated etching at contacted interfaces (Figure 4). Fundamental studies in the nature of metal etching at grain boundaries as a function of grain size, phase, orientation and texture are critically needed. The reaction mechanisms and equilibriums leading to oxidation, nature of transient oxides and their dissolution in the etchant as well as chelation-based stabilization of the dissolved metal to prevent re-deposition are not well characterized. While the application of nano-controlled etching to enable metal-capping for better EM performance and LWR control as described, is quite specific, it is neither unique nor exhaustive. Enhanced ability to selectively and controllably etch different metals may enable multiple innovations that will be needed at the 10 nm node and beyond to drive Moore's law. Fig 1. Metal capping by selective metal deposition: a) marginality in growth selectivity poses a shorting risk; b) cap growth typical produces an overhang which reduces dielectric CD and negatively impacts line width roughness (LWR) Fig 2. Nano-controlled etch of polycrystalline metal allows for deposition of a metal cap in the recessed cavity. Fig 3. Nano-controlled etch of Cu lines with a Ta-based barrier Fig 4. a) Nano-controlled Cu etch with a Ta-based barrier b) Nano-controlled Cu etch with a Ru-based barrier Figure 1

Low Dislocation Density AlGaN Epilayers for UV Laser Diodes and Devices for Power Electronics

The AlGaN alloy system has been the material system of choice for development of solid-state UV emitters and has promising properties for high-voltage power electronics. The performance and reliability of both optical emitters and power devices are critically dependent on the density of threading dislocations. While the binary substrates, GaN and AlN, are becoming commercially available, only a limited range of AlGaN compositions can be grown pseudomorphicly to device-relevant thicknesses of a micron or more. This his restricts the range of heterostructures available for designing advanced devices, and creates a need for a ternary-like pseudo-substrate with a tunable lattice constant. We present a method for fabricating crack-free AlxGa1-xN templates over the entire alloy range with threading dislocation densities (TDD) in the low 108 cm-2 ranges. We employ AlxGa1-xN overgrowth of previously grown AlxGa1-xN/AlN/sapphire templates that have been patterned with parallel trenches on a 2 μm pitch consisting of submicron-wide-mesas.1 Following overgrowth, the remaining threading dislocations are uniformly distributed over 2-inch-wafer-size areas enabling large area devices such as LEDs and PIN diodes to consist of only low TDD material. As a result, laser diodes do not need to be aligned to the underlying trench pattern. Wafer bow is reduced to less than 15 μm and epilayer cracking is essentially eliminated by using 1.3 mm-thick sapphire substrates (three times thicker than typical 2-inch wafers). The utility of the described overgrowth process for various alloy compositions is demonstrated by growing 5 to 10 μm thick Al0.3Ga0.7N, Al0.7Ga0.3N and AlN epilayers on sapphire substrates. While AlN substrates continue to improve, they are still relatively immature, expensive, and small in area compared to GaN substrates. Using the described overgrowth process and a modest growth temperature of 1100 °C, AlN epilayers grown on sapphire have achieved FWHM linewidths < 300 arc seconds for the (10-11) x-ray diffraction reflection and an RMS roughness of 1 Å over a 10 x 10 μm2region. Such x-ray linewidth and surface roughness values are comparable to AlN grown in specialized MOCVD reactors capable of growth in excess of 1300 °C. These low TDD AlGaN layers have been used for various devices. For example, the AlN overgrowth templates are used to demonstrate 2DEG formation in MODFETs formed by Al0.85Ga0.15N / Al0.7Ga0.3N heterostructures. Additionally, UV laser diodes were grown on Al0.3Ga0.7N overgrowth templates that achieved room-temperature, pulsed-current operation with emission at 352 nm and peak output powers > 2.5 mW per facet. Finally, we will also discuss the potential of using >10 μm thick Al0.3Ga0.7N overgrowth templates for PIN diodes. [1.] Allerman, et. al. J. Crystal Growth 38876 (2014). This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Atomic force microscope caliper for critical dimension measurements of micro and nanostructures through sidewall scanning

A novel atomic force microscope (AFM) dual-probe caliper for critical dimension (CD) metrology has been developed. The caliper is equipped with two facing tilted optical fiber probes (OFPs) wherein each can be used independently to scan either sidewall of micro and nanostructures. The OFP tip with length up to 500μm (aspect ratio 10:1, apex diameter ⩾10nm) has unique features of scanning deep trenches and imaging sidewalls of relatively high steps with exclusive profiling possibilities. The caliper arms–OFPs can be accurately aligned with a well calibrated opening distance. The line width, line edge roughness, line width roughness, groove width and CD angles can be measured through serial scan of adjacent or opposite sidewalls with each probe. Capabilities of the presented AFM caliper have been validated through experimental CD measurement results of comb microstructures and AFM calibration grating TGZ3.

Double-Patterned Sidewall Directed Self-Assembly and Pattern Transfer of Sub-10 nm PTMSS-b-PMOST.

The directed self-assembly (DSA) of two sub-20 nm pitch silicon-containing block copolymers (BCPs) was accomplished using a double-patterned sidewall scheme in which each lithographic prepatterned feature produced two regions for pattern registration. In doing so, the critical dimension of the lithographic prepatterns was relaxed by a factor of 2 compared to previously reported schemes for DSA. The key to enabling the double-patterned sidewall scheme is the exploitation of the oxidized sidewalls of cross-linked polystyrene formed during the pattern transfer of the resist via reactive ion etching. This results in shallow trenches with two guiding interfaces per prepatterned feature. Electron loss spectroscopy was used to study and confirm the guiding mechanism of the double-patterned sidewalls, and pattern transfer of the BCPs into a silicon substrate was achieved using reactive ion etching. The line edge roughness, width roughness, and placement error are near the target required for bit-patterned media applications, and the technique is also compatible with the needs of the semiconductor industry for high-volume manufacturing.

Gate double patterning strategies for 10-nm node FinFET devices

Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Hydrothermal fabrication of ZnO nanorod-based grating patterns with arrays of optical fiber cores as templates

A hydrothermal fabrication of ZnO nanorod-based grating patterns on Si substrates is reported. The arrays of optical fiber cores were manually assembled as templates with nominal pitches of 250μm and 375μm. The profiles of the templates and the grating patterns were extracted and quantitatively characterized based on micrographs of scanning electron microscopy (SEM) and Image Processing Toolbox of MATLAB. The errors of the actual pitches and the parallelism demonstrate that the process capability of manually assembling the optical fiber cores can meet the quality requirement of the templates. The critical dimensions (CDs) show that the size of the trough formed by the template and the Si substrate determines the location of the grating pattern. The characteristic parameters, including line edge roughness (LER), line width roughness (LWR), skewness (Sk), kurtosis (Ku), and correlation length (ζ), exhibit that the three-phase contact lines among the trapped air bubble, ZnO seed solution, and Si substrate (or the optical fiber core) decide the form of the grating pattern. The research found that larger nominal pitch of the template resulted in larger size of the trough which further led to less CD, and higher hydrophilicity of the Si surfaces resulted in smoother profiles whilst lower hydrophilicity of the optical fiber core surfaces led to rougher ones.

The Influence of H2Plasma Treatment on LWR Mitigation: The Importance of EUV Photoresist Composition

To meet the demands for sub-20 nm feature devices in the semiconductor industry, minimizing the line width roughness (LWR) is a critical concern for ultra-large scale integrated circuit manufacturing. Post-lithography treatments should reduce the LWR by at least 50% to meet the technology requirements, but the available post-lithography strategies come short. To support the delayed progress, an in depth understanding of the interaction of such post-lithography treatments with EUV-specific resist functionalities is required. In this article, we analyze the change in line widths and LWR's for 30–35 nm lines using EUV photoresists. In addition we study the effect of the chemical composition on the reduction of LWR after hydrogen plasma treatment using “artificially” prepared reference resists. We highlight the effect of the fluorine unit, ester functionalities and photo acid generator/quencher loading on the LWR improvement and H2 plasma induced reflow.

Enabling EUV Resist Research at the 1x and Smaller Regime

Author(s): Naulleau, P; Anderson, C; Chao, W; Goldberg, K; Wojdyla, A; Bhattarai, S; Neureuther, A; Goodwin, F; Neisser, M | Abstract: With the slipping of the insertion node for extreme ultraviolet lithography, demands on resist resolution have increased further stressing sensitivity requirements. A variety of resists, both chemically amplified and not, have been developed meeting resolution needs, but falling short on sensitivity and line-width roughness (LWR). Note that resolution is an absolute mandatory requirement, the true tradeoff that must be considered is between sensitivity and contact hole printing is a crucial application for extreme ultraviolet lithography and is particularly challenged by resist sensitivity due to inherent inefficiencies in darkfield contact printing. Checkerboard strong phase shift masks have the potential to alleviate this problem through a 4× increase in optical efficiency. The feasibility of this method is demonstrated using the SEMATECH-Berkeley Microfield Exposure Tool pseudo phase shift mask configuration and preliminary results are provided on the fabrication of an etched multilayer checkerboard phase shift mask.

Pattern Roughness Mitigation of 22 nm Lines and Spaces: The Impact of a H2Plasma Treatment

As the semiconductor industry pursues Moore's law, the demand to obtain smaller features continues. Extreme ultraviolet (EUV) lithography remains one of the primary options for sub-20 nm patterns. However, the technology struggles to meet the line width roughness (LWR) specifications. In this article, we present the significance of plasma treatment as a roughness smoothing technique. Two EUV photoresists with 22 nm lines are exposed to various plasma processes. We highlight the advantages of a hydrogen plasma treatment and its vacuum ultraviolet (VUV) emission as an optimal smoothing process and discuss the effect of photoresist thickness, initial LWR and the VUV plasma emission. Even though a H2 plasma treatment results in a successful reduction of LWR/LER, the target value of below 2nm is not yet achieved.

Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the poly-silicon gate etch based on the composite SiO2/Si3N4/SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α-Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

Synthesis of triphenylsulfonium triflate bound copolymer for electron beam lithography.

Photoacid generator (PAG) has been widely used as a key component in photoresist for high-resolution patterning with high sensitivity. A novel acrylic monomer, triphenylsulfonium salt methyl methacrylate (TPSMA), was synthesized and includes triphenylsulfonium triflate as a PAG. The poly(MMA-co-TPSMA) (PMT) as a polymer-bound PAG was synthesized with methyl methacrylate (MMA) and TPSMA for electron beam lithography. Characterization of PMT was carried out by NMR and FTIR. The molecular weight was analyzed by GPC. Thermal properties were studied using TGA and DSC. Thecharacterization results were in good agreement with corresponding chemical compositions and thermal stability. PMT was subsequently employed in electron beam lithography and its lithographic performance was confirmed by FE-SEM. This PMT was accomplished to improve the lithographic performance including sensitivity, line width roughness (LWR) and resolution. We found that PMT was capable of 20 nm negative tone patterns with better sensitivity than hydrogensilsesquioxane (HSQ) which is a conventional negative tone resist.

Response of Block Copolymer Thin-Film Morphology to Line-Width Roughness on a Chemoepitaxial Template

Using the Leibler–Ohta–Kawasaki (LOK) phase-field model of block copolymers (BCPs), we characterize how line-width roughness (LWR) in the chemoepitaxial template affects the BCP microdomain shape. Specifically, we derive formulas for the monomer density and the microdomain interface profile of periodic, lamellar BCP melts whose template lines widths oscillate with frequency k. The key idea behind our approach is to identify variations in the microdomain interface positions (relative to their averages) as corresponding to a local excess of one of the monomer types. For lamellar systems, our analysis (i) shows that the BCP morphology arises from the constraint that the total mass in a microdomain is fixed, independent of LWR, and (ii) determines a length scale λ over which template LWR affects the polymer melt.

Size and shape control of sub-20 nm patterns fabricated using focused electron beam-induced processing

In a first study to analyze the feasibility of electron beam-induced deposition (EBID) for creating certain patterns in advanced lithography, line patterns were fabricated on silicon wafers using EBID. The growth conditions were such that the growth rate is fully determined by the electron flux (the current limited growth regime). It is experimentally verified that different patterning strategies, such as serial versus parallel patterning and single pass patterning versus multiple pass patterning, all lead to the same result in this growth regime. Images of EBID lines, imaged in a scanning electron microscope, were analyzed to determine the position of the lines, the width of the lines, and the linewidth roughness (LWR). The results are that the lines have an average width of 13.7 nm, an average standard deviation of 1.6 nm in the center position of the lines, and an average LWR of 4.5 nm (1? value). As an example of the capabilities of EBID, a logic-resembling lithography pattern was fabricated