Abstract –In this paper, Digital multipliers are very important for the performance of VLSI systems. However, traditional designs like array multipliers suffer from high delay due to carry propagation and also consume more power. To overcome these problems, this paper presents the design of an optimized 8-bit Dadda multiplier that improves both speed and power efficiency.In this design, the conventional CMOS full adders are replaced with hybrid logic full adders based on XOR-XNOR cells. This change helps to reduce logic levels, internal capacitance, and switching activity, which directly improves the speed of operation. As a result, the generation of sum and carry becomes faster.To further reduce power consumption, an NMOS power gating technique is used. A sleep transistor is placed between the logic circuit and ground to reduce leakage current when the circuit is idle. This helps in minimizing static power dissipation.The proposed design is implemented and simulated using Cadence tools. The results are compared with a conventional Dadda multiplier, and significant improvements are observed. The propagation delay is reduced by 55.7%, from 740.0 ps to 327.3 ps, showing a clear increase in speed. Similarly, the total power consumption is reduced from 1.03 mW to 998.7 µW, improving overall efficiency.Although there is a small increase in area, with the transistor count increasing from 1744 MOS to 1752 MOS, the performance improvements in speed and power make it acceptable. Finally, the proposed multiplier offers a good balance between high speed, low power, and area, making it suitable for applications such as digital signal processing, image processing, and battery-operated embedded VLSI systems. Key Words: NMOS Power Gating, Leakage Power, Propagation Delay, VLSI Arithmetic, Xor-Xnor cell

Static random-access memory (SRAM) design at nanoscale dimensions faces critical challenges arising from degraded stability, excessive power dissipation, and heightened sensitivity to process variations, particularly under low-voltage operation. To address these limitations, this paper proposes a robust and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based nine-transistor (9T) SRAM cell architecture optimized for low-power applications. The proposed design employs a fully decoupled read and write structure with a single-ended access scheme, effectively eliminating read-disturb and half-select failures while enhancing overall noise immunity. Read stability is significantly improved by isolating the storage nodes from the read bitline, enabling the read static noise margin (RSNM) to reach the hold static noise margin (HSNM). Write robustness is achieved through controlled manipulation of the inverter pull-down paths, facilitating conflict-free write operations without aggressive transistor upsizing or complex assist circuitry. HSPICE simulations using the Stanford 32-nm CNTFET model demonstrate that, at a supply voltage of 0.3V, the proposed SRAM achieves a 2.1 × improvement in RSNM and over a 14 × enhancement in write static noise margin (WSNM) compared to the conventional 6T SRAM. In addition, reduced bitline activity, elimination of precharge circuitry, and effective transistor stacking result in substantial reductions in read, write, and leakage power consumption. Monte Carlo simulations incorporating realistic process variations further confirm superior robustness, with the highest mean-to-standard-deviation ratios for both RSNM and WSNM among the compared designs. Layout-level evaluation shows that these benefits are achieved with only a modest area overhead relative to the 6T SRAM cell and with a smaller footprint than existing 9T and 10T alternatives. Overall, the proposed CNTFET-based 9T SRAM cell provides a well-balanced solution for low-voltage, energy-constrained, and variability-aware memory systems, making it a promising candidate for future CNTFET-based integrated circuits.

Light detection and ranging (LiDAR) systems that rely on wavelength tuning typically employ gratings to realize wavelength-dependent beam steering. In this work, we propose a subwavelength grating (SWG) antenna incorporating shallow-etched auxiliary blocks. These auxiliary blocks break the vertical structural symmetry of the antenna, thereby effectively suppressing downward optical power leakage into the substrate. The geometric parameters are optimized using a particle swarm optimization (PSO) algorithm, resulting in a transmission of 66.2%, a scanning rate of -0.233∘/nm, and transmission fluctuations confined within 6.42%. The system uses a coarse wavelength-division multiplexing (CWDM) laser array as the light source and supports bidirectional waveguide propagation, achieving a 28° scanning field of view (FOV) over a 60nm wavelength range.

Abstract A power-efficient Schmitt trigger 10-transistor (ST10T) SRAM cell with single-ended operation has been proposed for high performance. To minimize read delay and improve read stability, a decoupled read structure has been employed. Furthermore, write delay and writeability have been improved by employing a Schmitt trigger structure. A comprehensive comparison is performed against several existing SRAM architectures, including ST9T, SE 10T, ST10T, and P10T SRAM cells. The proposed design achieves significant improvements, offering up to 1.90× higher read stability than the SE 10T, 1.84× better hold stability than the P10T SRAM cells, and 2.0× higher writability than the ST9T SRAM cell. In addition, the cell reduces leakage power by 4.93× compared to ST9T and dynamic power reduces by 2.17× compared to the P10T cell. The read and write delays also improve substantially, with reductions of 3.19× and 6.07× compared to the SE10T cell simultaneously. Monte Carlo analysis with 1000 samples confirms robust operation under process variations. To provide a complete evaluation, a relative (FOM) is calculated that includes all the most important performance indicators. All simulations are carried out in Cadence Virtuoso using 45 nm CMOS technology at VDD of 1.0V.

Abstract TFETs are viable alternatives to traditional MOSFETs as device dimensions continue to shrink. MOSFETs have a limited ability to switch sharply between the off and on states. As a result, the unwanted current increases with the applied potential, even when the device is off, leading to increased leakage and static power consumption. To address these concerns, nanotube TFET (NTFET) has been proposed based on a dopingless, optimized core-shell GAA structure to reduce leakage current. A dopingless transistor utilizing the charge plasma technique induces charge carriers via metal contacts at the drain and source, as well as an InGaAs source, achieving higher Ion due to the low bandgap. Incorporating ZrO2 as the gate dielectric material in the NTTFET device improves performance due to its high dielectric constant and superior thermodynamic stability. The GAA structure improves electrostatic control, minimizes the short-channel effect, and reduces power dissipation. To optimize device performance, a hybrid snow ablation and coati optimization algorithm determines the optimal gate and spacer lengths, effectively reducing leakage current using a defined fitness function. The overall performance of a dopingless, optimized TFET is evaluated using electrical measurements, including I-V curves, average subthreshold slope (mV/dec), mobility (cm2/V.s), transfer characteristics, drain current (A/μm), and transconductance (s/µm). Furthermore, performance measurement, such as IMD3, 1-dB compression point, Gm2, Gm1, VIP3, Gm3, VIP2, and the IIP3, are used for assess the linearity performance. These electrical characteristics are compared with the current models, channel length, and dielectric materials. The obtained values are: transconductance of 687 s/µm, drain current of 38 A/μm, average subthreshold slope of 47 mV/dec, and mobility of 1473 cm2/V.s. Therefore, all outcomes confirm that the proposed model offers better opportunities for electronic devices, resulting in increased speed and reduced current leakage.

The increased use and commercialisation of portable battery powered electronic gadgets has made low-power chip designs essential for extending battery life. Low-power electronic circuits also play an important role in the emerging wireless communication systems. Designing appropriate memory circuits is the key for the aforementioned cases, as memory occupies most of the chip area. In this paper, CNFET (Carbon Nanotube Field Effect Transistor)-based low-leakage SRAM (Static Random Access Memory) with enhanced stability is proposed. Simulations are carried out for the proposed CNFETSRAM cell, and its performance is compared with the conventional structures in terms of power, delay, stability, and power delay product by varying PVT (process-voltage-temperature) parameters. According to the results, the hold, read and write stability of the proposed CNFET SRAM improved by 49 %, 85% and 56 %, respectively, as compared to existing memory cells. Furthermore, the hold or leakage power is minimised by up to 99 % compared to conventional SRAMs. The simulation results confirm that the proposed solution is an appropriate memory structure for MIMO systems, meeting the requirements for very large-scale integration (VLSI) circuits with low leakage and high stability.

This paper presents an enhanced ONOFIC (ON/OFF Isolation Control) nano-domino logic framework implemented using 32 nm FinFET and CNTFET technologies for ultra-low leakage VLSI systems. The proposed ONOFIC technique employs feedback-controlled transistors to dynamically isolate leakage paths in the pull-up and pull-down networks, significantly reducing subthreshold leakage while preserving the high-speed characteristics of domino logic. Four ONOFIC-based architectures—Pull-Down, Dual-ONOFIC, Pull-Up, and Sandwiched ONOFIC—are designed and evaluated to investigate the trade-offs between leakage reduction, delay, and power consumption. In addition, an AI-assisted optimization approach is explored to automatically tune circuit parameters such as feedback bias and device sizing for improved leakage control and energy efficiency. HSPICE simulations using realistic FinFET and CNTFET models demonstrate up to 78% leakage reduction, approximately 45% total power savings, and 50–55% improvement in Power-Delay Product (PDP) compared with conventional domino logic techniques. The AI-optimized configurations further enhance leakage suppression and robustness under process-voltage-temperature (PVT) variations. These results confirm that combining ONOFIC-based leakage control with AI-assisted optimization provides an effective methodology for designing energy-efficient nano-scale VLSI systems suitable for modern low-power applications.

High power consumption, leakage currents, and fatigue in conventional electrical switches motivate the development of alternative switching paradigms for low-power and high-contrast signal control. In this study, a twisted bilayer SnTe switching architecture based on interlayer-twist-induced polarization switching is proposed. Introducing a finite twist disrupts the intrinsic symmetry of few-layer \ensuremath{\alpha}-SnTe, generating an out-of-plane polarization and enabling a large-contrast switching response. Near a twist angle of $27.{8}^{\ensuremath{\circ}}$, with a gradual rotation of $0.{323}^{\ensuremath{\circ}}$, the polarization undergoes a pronounced evolution from a virtually negligible value to a maximum of $3.26\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}11}\phantom{\rule{0.28em}{0ex}}\mathrm{C}/\mathrm{m}$, with the polarization differing by $3.24\ifmmode\times\else\texttimes\fi{}{10}^{\ensuremath{-}11}\phantom{\rule{0.28em}{0ex}}\mathrm{C}/\mathrm{m}$ between the two stable states. The remarkable polarization response induced by the subdegree interlayer twist establishes a viable strategy for designing low-power logic devices and multifunctional quantum electronic systems at the nanoscale.

The ever-increasing computational load and shrinking power budget have accentuated the need for energy-efficient operation of edge devices. In this article, a combination of static CMOS logic and Hybrid Pass transistor logic with Static CMOS output (HPSC), which has no floating or weak nodes and is thus as robust to noise as static CMOS logic, is used for designing toolchain-compatible super-Vth standard cells. Optimized HPSC variants of a 2/3-input XOR cell, a 2/3-input XNR cell, a half adder cell, a full adder cell, and two variants of a 1-bit multiply-accumulate combinational cell are presented in a commercial 65nm Low-Power CMOS technology. Measurements of test structures based on ring oscillators and dummy path techniques show an average frequency and average energy-delay product improvement of up to 30.3% and 32.5% respectively at typical conditions. The proposed cells’ superior performance compared to the commercially available standard cells is also highlighted in terms of propagation delay, leakage, and dynamic power consumption. This shows a promising approach for foundries or other commercial entities to improve digital design performance to about half a technology node at no additional cost.

Abstract A compact TM $$_{020}$$ 020 -mode RF cavity was proposed and studied by KEK and RIKEN for the storage ring of the NanoTerasu facility. However, performance limitations due to accelerating mode leakage into the coaxial slots have been identified. This paper presents an improved TM $$_{020}$$ 020 -mode cavity design to solve this issue. By employing an elliptical choke, the leakage power can be significantly reduced. Harmful parasitic modes other than the TM $$_{020}$$ 020 -mode are effectively suppressed using the elliptical choke placed at the magnetic node of the TM $$_{020}$$ 020 -mode. Through optimization, this improved TM $$_{020}$$ 020 -mode RF cavity meets the requirements of the Super Tau-Charm Facility (STCF) collider rings with a beam current of up to 2 A. Detailed mechanical design and thermal analysis confirm the feasibility and stability of the improved cavity.

The main objectives of the study focused on identifying the physical mechanisms of acoustic noise generation by high-voltage power lines under conditions of high humidity and quantitatively assessing associated energy losses. To achieve these objectives, the following tasks were accomplished: a physical-mathematical model was developed considering two complementary mechanisms - the motion of polarized water droplets in the non-uniform electric field of the wire and their subsequent destruction upon contact with the conductor; calculations were performed of the electric field strength near the wire, induced dipole moment of droplets, and the acting force; an assessment was made of droplet impact velocity on the wire and conditions for their micro-explosive destruction; and a methodology was developed for calculating additional leakage currents and power losses. The most important results are the theoretical substantiation of a new combined physical mechanism for noise generation, based on droplet polarization, acceleration, and micro-explosive destruction, and the development of a methodology for quantitative assessment of additional energy losses. The significance of the obtained results lies in proposing a comprehensive physical explanation of the acoustic phenomenon that establishes a connection between power line noise characteristics and electrophysical processes in the surface area under conditions of high humidity, as well as identifying a new mechanism of energy losses that is essential for optimizing operational regimes of high-voltage power transmission lines. The scientific novelty of the work is the proposal of this new mechanism and the established analytical relationships between key parameters. The practical significance lies in the developed methodology for assessing additional losses, which is important for improving the accuracy of loss forecasting and optimizing line operation in adverse weather conditions.

Low-power Arithmetic Logic Units (ALUs) form the computational backbone of modern energy-efficient digital systems, particularly in battery-powered and thermally constrained platforms such as Internet of Things (IoT) devices, mobile processors, and large-scale data centers. As semiconductor technologies continue to scale, power dissipation due to switching activity and leakage currents has emerged as a dominant limitation, often constraining performance, reliability, and system lifetime. Although conventional low-power techniques such as clock gating and power gating have shown promise, their static and heuristic-driven application is often insufficient to cope with dynamic workload variations and complex architectural interactions. This work presents an Optimization-Enhanced Low-Power ALU (O-ALU) that integrates metaheuristic-driven control with adaptive power management to achieve superior energy efficiency without compromising computational performance. The proposed architecture employs workload-aware activity monitoring combined with clock gating and power gating mechanisms that are dynamically optimized using intelligent search algorithms. This enables fine-grained, real-time adaptation of ALU submodules based on operational demand. The O-ALU is implemented and evaluated on an FPGA platform, and its performance is analyzed in terms of hardware resource utilization, dynamic and static power consumption, and execution efficiency. The experimental results demonstrate that the proposed design achieves significant reductions in both switching and leakage power while maintaining comparable throughput and latency to conventional ALU architectures. Moreover, the modular organization and adaptive control logic ensure scalability and robustness across varying workloads and technology nodes. Overall, the O-ALU provides a practical and effective solution for next-generation low-power processor design, offering a balanced trade-off between energy efficiency, performance, and architectural complexity.

The rapid growth of portable, embedded, and IoT systems has made power efficiency a primary design constraint for Arithmetic Logic Units (ALUs), FPGA platforms, and RISC-V based processors. This review critically examines recent lowpower design techniques reported between 2020 and 2025, covering clock gating, data gating, power gating, architectural optimization, and emerging device-level solutions. The surveyed literature shows that clock- and activity-aware gating methods, such as hybrid clock gating and signal-based gating, can achieve dynamic power reductions in the range of 45–66% while maintaining acceptable performance. FPGA-based implementations further demonstrate that clock gating, pipelining, and bioinspired transition suppression can lower power consumption by up to 40%, though often at the cost of increased area and timing overhead. Technology-level innovations, including GDI logic, reversible logic, ternary logic, and sub-threshold operation, provide additional improvements in power-delay and energy-delay products, but their practical adoption is limited by design and verification complexity. At the system level, power-gated SRAM-FPGAs, FSM partitioning, and RISC-V based power management units enable substantial leakage and runtime power reduction, particularly for battery-constrained applications. Overall, the review indicates that hybrid strategies combining ALU-level gating, architectural power management, and systemlevel control offer the most balanced trade-off between power efficiency, performance, and scalability in modern digital systems.

Modern vending machines operate to serve the consumer easy-access demand for daily items such as food, drinks, or books. Purchasing processes are carried out via automation from item selection, payment, up to the item dispensing are done without interaction to the human and this can be carried out for 24 hours a day and 7 days a week. However, the vending machines operates for 24/7, consumes the same electrical load regardless of if there is a transaction. Despite the advancements of Industrial Revolution 4.0 (IR4.0) in many sectors, electrical power of vending machine is yet to be optimized. This research aims to optimize vending machine power consumption by using camera to detect human near to the vending machine and relays to control the power usage. Human can be detected via camera via Artificial Intelligence (AI) and this becomes the input to the Smart Relay. Abnormality such as electrical leakage that draws more power can be detected as well. IoE dashboard is developed for vending operator to monitor the power usage, leakage potential, optimization, and prediction of power consumption. The system saves about to 50 percent of electrical power usage in the vending machine and low energy wastage while maintaining the same vending machine capabilities.

Abstract In the present world, the demand for low power consumption, enhanced performance and reduced area is ever increasing. Consequently a single-port 7T SRAM (Static Random Access Memory) bit-cell with a single bit-line configuration is proposed in this paper. The bit-cell is simulated at 32 nm technology node at 0.5 V power supply or VDD. The single bit-line architecture plays an important role in mitigating power consumption and reduction of the area of the bit-cell layout. Along with the static and transient analysis of the bit-cell, it is also tested for process variations and is observed to follow the 3- σ deviation when 10001-point Monte Carlo runs are performed. A comparative study of the proposed cell is conducted with six other single-ended SRAM bit-cells that have been earlier proposed, namely 7TA, 7TB, 7TC, 7TD, 7TE and 7TF. The proposed 7TP cell shows best static noise margin at 183 mV, the lowest write-0 delay of 38.58 ps and displays the lowest leakage power consumption of 5.14 nW which is 74.54%, 76%, 47.44%, 62.67% and 64.41% lower than 7TA, 7TB, 7TC, 7TD, 7TE and 7TF cells respectively. The energy-delay-area-product (EDAP) of proposed bit-cell is 3.339 × 10 −38 Jsm 2 which is 34.21%, 76.2%, 54.43%, 6.67%, 69.74% and 78.3% less than bit-cells 7TA, 7TB, 7TC, 7TD, 7TE and 7TF respectively, which proves that the proposed cell provides the best tradeoff in terms of power consumption, propagation delay and area as compared to other 7T bit-cells discussed in the paper. The 7TP cell also shows resilience to half select error and temperature variation.

Approximate computing has garnered significant attention due to its potential to reduce power consumption, enhance performance, and simplify circuit design. However, the security implications of applying approximate computing techniques remain largely unexplored. Identifying all possible vulnerabilities in approximate designs is very challenging. One of the challenges stems from the lack of insightful methodologies and metrics to perform a precise security evaluation. This paper presents <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ApproPower</i>, a security-driven framework for pre-silicon evaluation of power side-channel leakage in approximate multipliers. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ApproPower</i> enables an analysis of how approximation techniques influence power side-channel leakage and employs symbolic path analysis to estimate delay-dependent power leakage behaviors at design time. Using a set of open-source approximate multipliers, we examine the relationship between data precision, approximate strategies, and measured power leakage. Our results show that symbolic path analysis provides useful guidance for identifying potential power side-channel risks. We also observe that some approximate designs can offer improved resource efficiency while exhibiting reduced leakage; for instance, in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mul7x7u</i> set, a majority of benchmark circuits demonstrate lower leakage after approximation, with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mul7x7u_03M</i> achieving a 35% reduction in resource usage compared to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mul8x7u_3C6</i>.

Connecting rod bolts are critical fasteners in heavy equipment diesel engines, where their structural integrity is paramount for operational reliability. This study investigates the root cause of a connecting rod bolt fracture in a heavy equipment diesel engine which have 936 Horsepower, which precipitated a catastrophic engine breakdown involving low power, overheating, and oil leakage. The failure analysis employed visual observation, macrographic examination, and Vickers micro-hardness testing to evaluate the fracture morphology and material properties. Hardness testing results revealed a core hardness of 347 HV, confirming that the bolt material (AISI 8640) retained a proper tempered martensite structure consistent with standard specifications, thereby ruling out material deficiency or thermal degradation. Macrographic analysis identified a progressive failure sequence involving two distinct mechanisms. The primary bolt failed via High Cycle Fatigue (HCF), evidenced by a flat fracture surface and ratchet marks at the periphery, indicative of reversed bending forces. The fracture of the primary bolt caused a loss of clamping force, leading to the instantaneous failure of the remaining bolts via ductile overload, characterized by fibrous topography and shear lips. The study concludes that the root cause of the failure was mechanical joint instability (loosening), which introduced fatal bending stresses and initiated the fatigue mechanism.

This work presents the tape out of the first-ever side-channel protected machine learning (ML) classifier as an ASIC. Side-channel protection leverages hardware masking, algorithmic shuffling, and other countermeasures to mitigated power and electromagnetic leakage vulnerabilities in ML models. We fabricated the ASIC using the SkyWater 130nm technology node and a fully open-source design flow. We document our design and implementation process, detailing key decisions and the challenges encountered along the way, including but not limited to integrating the open-source physical design flow with Efabless’ ChipIgnite shuttle program. Our results indicate that open-source tools can be effectively used to produce secure and high-performance hardware, providing a valuable blueprint for future designs and advancing the field of secure ML hardware.

The continuous advancement of semiconductor processes has led to increasingly prominent leakage power issues in integrated circuits (ICs), making leakage-aware nonlinear thermal simulation a critical challenge in modern chip design. Traditional deterministic field solvers provide high accuracy but suffer from significant computational inefficiencies when handling large-scale mesh structures. Conversely, stochastic methods offer rapid computation speeds but are inherently limited to single-point solutions, preventing them from effectively addressing nonlinear thermal problems. To address this challenge, we propose a virtual path-based stochastic solver that enables efficient leakage-aware thermal simulation. The virtual path algorithm decomposes each real path in Brownian motion into virtual paths, extending stochastic solvers from single-point solutions to regional solutions, allowing a stochastic method to achieve full-chip thermal simulation for the first time, thus enabling the handling of nonlinearity. Additionally, we further accelerate the iteration process by reusing the path trajectories from the first solution process. Extensive experimental evaluations demonstrate that our method achieves a speedup of 20.17× to 52.23× compared to the state-of-the-art solver 3D-ICE on 4 GPUs across various scenarios while maintaining comparable accuracy.

Radio simultaneously localization and mapping (SLAM) is indispensable for a wide range of wireless applications owing to its ability to provide both location and mapping information. Traditional radio SLAM systems use fixed-aperture antennas with invariant beamwidths, which cannot adapt to the varying requirements for beam gain and coverage in complex environments. In this paper, we propose an aperture-changeable reconfigurable holographic surface (RHS)-assisted SLAM system. By deactivating different numbers of RHS elements, the equivalent antenna aperture is changeable, leading to adaptive beamwidths across detection directions. However, the RHS should follow the leakage power constraint, which stipulates that the total radiated power of RHS elements cannot exceed the input power. Its impact on the elements’ radiated power makes the optimization of RHS equivalent aperture challenging. To address this issue, we formulate a detection probability maximization problem and then adopt a two-step decomposition method to solve it. In the first step, we relax the leakage power constraint to obtain a relaxed solution. In the second step, we refine the relaxed solution by incorporating the leakage power constraint. We analyze the impact of RHS equivalent aperture and leakage power constraint on the SLAM system and evaluate the complexity of the proposed algorithm. Simulation results demonstrate that the proposed SLAM system can effectively reduce agent localization error compared with benchmark schemes.