LC VCO Research Articles

New Design Method of LC VCO Improving PVT Tolerance of Phase Noise

We present a LC VCO design method of the multiple start-point global optimization. It is used to optimize VCO phase noise variation in different Process, supply voltage and temperature (PVT) conditions at the same time. Based on this method, we can design PVT tol- erant LC VCO even without PVT compensation circuits. The design results of different foundry manufacturing pro- cess and oscillating frequency is shown to investigate the effect of this phase noise optimization method. The design method also can help to enhance manufacturing yield.

A 6.5 - 8.5 GHz CMOS UWB Transmitter Using Switched LC VCO

A 6.5 - 8.5 GHz CMOS UWB transmitter is implemented using 0.18 μm CMOS technology. The transmitter is mainly composed of switched LC VCO and digital pulse generator (DPG). Using RF switch and DPG, the uniform power and sidelobe rejection are achieved irrespective of the carrier frequency. The measured UWB carrier frequency range is 7 ~ 8 GHz and the pulse width is tunable from 1 to 2 ns. The measured energy efficiency per pulse is 2.1 % and the power consumption is 0.6 mW at 10 Mbps without the buffer amplifier. The chip core size is 0.72 mm 2 .

High-performance cost-efficient dual-band CMOS LC VCO

High-performance cost-efficient dual-band CMOS LC VCO

A low-power 2.4-GHz combined LNA–VCO structure in 0.13-µm CMOS

A combined low-noise amplifier and voltage-controlled oscillator (LNA---VCO) is implemented in a 0.13-µm CMOS technology. The low-power LC VCO and LNA circuits are stacked and share the same bias c...

A power scalable PLL frequency synthesizer for high-speed Δ—Σ ADC

A 35–130 MHz/300–360 MHz phase-locked loop frequency synthesizer for Δ—Σ analog-to-digital converter (ADC) in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode (300–360 MHz) or in low-power mode (35–130 MHz) to satisfy the ADC's requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the frequency synthesizer achieves a phase-noise of −132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of −112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.

Design of a Low Phase Noise VCO for WSN Applications

A fully integrated LC VCO with 1V low voltage supply, applied in the frequency synthesizer for wireless sensor network applications, is designed and implemented in TSMC 0.18μm RF/MS CMOS process with low power consumption and good phase noise performance. To conquer the problems brought by low voltage, the structure of VCO is carefully selected. A 4 bit switched capacitor array is used to widen tuning range without worsen the phase noise performance. Besides, a 2 bit switched tail current source array is used to achieve power consumption adapted to the desired operating scenario. Second harmonic filter technology is taken to improve phase noise performance. The VCO designed in this paper has good phase noise performance and low power consumption by optimization. The chip size is 860μm×730μm. Post-simulation results show that the frequency range is between 4.57~6.18GHz with tuning range 30%, the center frequency is 5.375GHz, and the power consumption of VCO core is between 2.6~4mW. At the meanwhile, phase noise is between-116.0~ -117.8dBc@1.0MHz.

A Band-Reject Nested-PLL Clock Cleaner Using a Tunable MEMS Oscillator

This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. As the architecture employs a modified PLL as a divider of another PLL, a stability analysis is presented to demonstrate suitable operation. The BRN-PLL close-to-carrier output noise is dominated by the PFD/CP of the inner PLL and the far-from-carrier output noise is dominated by the LO of the outer PLL. The PFD/CP noise can be reduced by approximately 20 dB when the output is disconnected from the VCO during idle states, and a low noise floor is achieved using a passively biased double-switching pair LC VCO. Additionally, to maintain lower integrated phase noise, the proposed scheme uses a high- Q MEMS-based VCO to effectively smoothen the transition of the response between the two dominant noise sources. Absolute figures equal to -105 dBc/Hz at 1 kHz and -155 dBc/Hz at 10 MHz are measured from a 104 MHz clock-cleaner.

Design of a Low-Phase-Noise LC Voltage Controlled Oscillator

A novel low phase noise LC Voltage Controlled Oscillator (LC-VCO) is designed in standard 0.18μm CMOS technology. Instead of common NMOS cross-pairs for a conventional complementary LC VCO, both body-biasing and Q-enhancement techniques are employed to provide a larger negative resistance for the VCO. Post-layout simulations showed that it can oscillate at a frequency range of 4.34-4.73GHz, and comsume a supply current of 1.52mA from a supply voltage of 1.8V. The VCO achieves a phase noise of -132.8dBc/Hz @ 1MHz offset and a figure of merit (FOM) of -195.9dBc/Hz at the frequency of 4.5GHz. A die area of 475μm×498.6μm is occupied.

Design of a Low-Phase-Noise LC Voltage Controlled Oscillator

A novel low phase noise LC Voltage Controlled Oscillator (LC-VCO) is designed in standard 0.18μm CMOS technology. Instead of common NMOS cross-pairs for a conventional complementary LC VCO, both body-biasing and Q-enhancement techniques are employed to provide a larger negative resistance for the VCO. Post-layout simulations showed that it can oscillate at a frequency range of 4.34-4.73GHz, and comsume a supply current of 1.52mA from a supply voltage of 1.8V. The VCO achieves a phase noise of -132.8dBc/Hz @ 1MHz offset and a figure of merit (FOM) of -195.9dBc/Hz at the frequency of 4.5GHz. A die area of 475μm×498.6μm is occupied.

A self-correcting quadrature voltage controlled oscillator

A self-correcting quadrature voltage controlled oscillator (QVCO) with phase correcting loop is proposed. It comprises the QVCO core and phase correcting loop, which corrects the quadrature phase error. Two LC VCOs, buffers, and phase shifters are coupled in circular configuration to achieve IQ symmetry. This paper introduces the idea of realizing QVCO with low phase noise and accurate quadrature phase by using the phase correcting loop. The simulation results based on the 65 nm CMOS process show that the self-correcting QVCO has a phase error less than 0.5° and 1 MHz offset phase noise of −120 dBc/Hz at 3.7 GHz with 49% tuning range.

A Wide Tuning Range mm-Wave LC VCO

A Wide Tuning Range mm-Wave LC VCO

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

A 20–40 MHz low-power clock oscillator with open-loop frequency calibration and temperature compensation

In this paper, a 20–40 MHz low-power clock oscillator is presented to provide the frequency reference in data interface applications. The frequency source is referenced to a frequency-calibrated and temperature-compensated 2.5 GHz LC VCO that is implemented with a bondwire inductor. Class-C type VCO is adopted in order to improve the phase noise and reduce the current consumption. A full digital frequency calibration circuit is proposed to cover the wide output frequency range minimizing the frequency variation. External crystal oscillator (REF_CLK) is used only for the absolute frequency calibration at the initial programming stage and is not needed after the programming stage. On the other hand, temperature compensation is performed in an analogue way by controlling the varactor in the LC VCO. This chip is fabricated using 0.18-µm CMOS with the option of lateral PNP transistor. Lateral PNP transistors are used in the temperature compensation circuits. It can be implemented laterally in standard CMOS process. The power consumption is 4.8 mW from a 1.8 V supply. The accuracy of the frequency is ±58 ppm from −20°C to 80°C. The nominal phase noise at 1 MHz and period jitter is −122 dBc/Hz and 2 ps, respectively, when the output frequency is 25 MHz.

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

A low‐power technique to boost the output amplitude of multi gigahertz push‐push LC VCOS

AbstractA design technique to increase the output amplitude and hence the output power of push‐push LC‐based voltage‐controlled oscillators (LC VCOs) is presented that relies on LC resonance boosting of the second harmonic. Measurement results are in good agreement with the results predicted from the analysis. Using the proposed technique, a low‐power push‐push LC VCO is designed and implemented in 90‐nm CMOS. Based on the measurement results, the VCO has a frequency tuning range of 23%, from 20.1 to 24.8 GHz. It exhibits up to 8 dB improvement in its output power at the middle of the frequency band compared to a traditional push‐push VCO. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1581–1584, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27599

Wide tuning range LC VCO with parallel coupled negative g m cells

To minimise phase noise degradation with a wide tuning range, the proposed LC voltage controlled oscillator incorporates parallel coupled negative transconductance (g m ) cells. Phase noise for wide tuning range VCOs suffers from degradation of quality factor of tank inductors or tank capacitors due to their parasitic resistance. The proposed parallel coupled negative g m cells provide additional current to compensate for the loss of phase noise. The measured results show a tuning range of 25.4% and a phase noise of − 116.7 dBc/Hz at 1 MHz offset frequency at 5.87 GHz with power consumption of 1.4 mW. The figure-of-merit with the fractional tuning range of the VCO was − 199.9 dBc/Hz, which is the best among the latest state-of-the-art wide tuning range CMOS LC VCOs.

Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8 GHz is designed and implemented in a 65 nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device.

Design and analysis of a bang—bang PLL for 6.25 Gbps SerDes

An analysis illustrates the loop nonlinear performance in a bang—bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase detector is composed of four master-slave DFFs and two XORs based on the current mode logic circuit. A no-load architecture is introduced in the XOR design. The oscillator is designed with an LC VCO implementation for the jitter requirement. A simple voltage-to-current converter is proposed to drive the loop filter. The loop filter design is described in detail, which is important to ensure the nonlinear loop stability. The chip is fabricated in a 0.18 μm CMOS technology. The experimental results show that it can achieve the frequency range of 2.995 to 3.35 GHz, and a phase noise of −118.38 dBc/Hz at 1 MHz offset. The frequency to voltage gain is 270 MHz/V. The chip consumes less than 81 mW with 1.8 V supply voltage, and it occupies a 0.5 mm2 area.

Quadrature Sine Wave Signals Generated by Selection Topology and its Components

This paper presents how to generate high frequency quadrature sinewave signals by selection topology and its active and passive components. Also, presents how to choose the value of inductor by different ways followed by performance comparison of various VCO topologies. The overall performance is displayed by all-pMOS VCO in terms of supply voltage and tuning range. The performance comparison of all-pMOS LC-VCO using various capacitive loads is discussed. All-pMOS LC-VCO with MOS capacitor switched capacitor array (SCA) followed by divider using CML latch without fixed tail current source is used for generation of high linearity quadrature signals. A three 2.4/4.8 GHz CMOS Quadrature Voltage Controlled Oscillators (QVCO's) tuned by a diode varactor, inversion- mode pMOS varactor and an accumulation-mode nMOS varactor, respectively. The performance comparison of different varactors QVCO is simulated in terms of frequency range, tuning range, harmonic distortion and power consumption. The overall performance is displayed by inversion mode pMOS varactor QVCO. However, all the performances of varactor QVCO's are significantly closer with all-pMOS LC VCO compared with other VCO topologies like all-nMOS LC-VCO and complementary cross coupled LC- VCO, due to low dc impedance path between the varactor to ground terminal. It displayed the power consumption of all varactor QVCO's are equal. The QVCO's were implemented in a 0.18 µm standard CMOS technology as the supply voltage is 1 V. The pre and post layout simulation results are compared in terms of tuning range, phase noise, power dissipation, and harmonic distortion, self oscillation frequency of divider and reference voltage of inversion mode pMOS varctor QVCO.

Active Inductor based VCO for High Tuning Range

This paper presents a study of Active inductor based VCOs that helps in increasing the tuning range of the VCO , reduces the chip size and phase noise of the circuit. Study has been done on LC VCOs by replacing the passive inductors with the active one consisting of MOSFET. Design of circuit has been done on Orcade Capture using .18um technology.power consumption of circuit is 1.33mW with tuning range of 81%.Tuning range of the VCO is increased because the active inductor cancels out the parasitic capacitance of the circuit.