LC-tank VCOs Research Articles

A Reconfigurable Radio-Frequency Converter IC in 0.18 µm CMOS

This work presents a reconfigurable RF converter for DVB-T television applications using triple-play over GPON. The system takes the DVB-T input, a wavelength division multiplexing (WDM) signal with spectral inversion in the range from 47 M Hz –1000 M Hz , up-converts its frequency to the band-pass of a highly selective surface-acoustic wave (SAW) filter centered at 1.3 G Hz , and then down-converts it so that it is compatible with the antenna input of conventional television sets. The designed RF converter incorporates two pairs of frequency synthesizer and mixer, based, respectively, on an integer-N phase-locked loop (PLL) with two LC-tank VCOs with 128 coarse tuning bands in the range from 1.35 G Hz –2.7 G Hz , and a double-balanced Gilbert cell, modified for better impedance matching and improved linearity. It is fed with regulated supplies compensated in temperature and programmed by an I 2 C interface operating on five 16-bit registers. This work presents the experimental characterization of the whole system plus selected cells for stand-alone testing, which have been fabricated in a 0.18 m CMOS process.

A Wideband Receiver With Resonant Multi-Phase LO and Current Reuse Harmonic Rejection Baseband

In this work we present an architecture for a low power SDR which draws on techniques from both narrowband low power radios and recent work in SDRs. The receiver consists of a wide tuning-range passive mixer, driven with resonant non-overlapping LO drive combined with a noise-power optimized multi-path baseband amplifier. LO generation circuitry drives the mixer with an 8-phase, 12.5% duty cycle LO, but does so directly from complementary LC-tank VCOs in order to resonate out the gate capacitance of the mixer. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock at no added cost in power or performance, while achieving a NF as low as 7 dB. The 1.8 mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply.

A Quadrature CMOS VCO Using Transformer Coupling and Current Reuse Topology

A new current reused quadrature voltage controlled oscillator (QVCO) is proposed and implemented using UMC 0.18 μm CMOS 1P6M process. The proposed circuit topology is made up two low voltage LC-tank VCOs, where the QVCO is obtained using the transformer coupling and current reuse technique. At 1.8 V supply voltage, the phase noise of the VCO is -117.13 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.18GHz, the core power consumption is 4.14mW, the total power consumption is 6.48 mW and tuning range is about 160 MHz.

A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology

A novel low-voltage quadrature voltage-controlled oscillator (QVCO) with voltage feedback to the input gate of a switching amplifier is proposed and implemented using the standard TSMC 0.18-mum CMOS 1P6M process. The proposed circuit topology is made up of two low-voltage LC-tank VCOs, where the coupled QVCO is obtained using the transformer coupling technique. At the 0.7-V supply voltage, the output phase noise of the VCO is -124.9 dBc/Hz at 1-MHz offset frequency from the carrier frequency of 2.4GHz, and the figure of merit is -185.35dBc/Hz. Total power consumption is 5.18 mW. Tuning range is about 135 MHz while the control voltage was tuned from 0 to 0.7V

A design approach for integrated CMOS LC-tank oscillators using bifurcation analysis

Abstract. Electrical oscillators play a decisive role in integrated transceivers for wired and wireless communication systems. In this context the study of fully integrated differential VCOs has received attention. In this paper formulas for investigations of the stability as well as the amplitude of CMOS LC tank oscillators are derived, where an overall model of nonlinear gain elements is used. By means of these results we are able to present an improved design approach which gives a deeper insight into the functionality of LC tank VCOs.

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18 mum 3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs. A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results. A prototype for the QVCO was implemented in a 0.35-/spl mu/m CMOS process with three standard metal layers. The QVCO could be tuned between 1.64 and 1.97 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply. The equivalent phase error between I and Q signals was at most 0.25/spl deg/.