For most people, Apple’s introduction of backside-illuminated (BSI) CMOS image sensors (CIS) in their iPhone4 may have been the first time they became aware of this technology. Compared with traditional front-illuminated CMOS, light in a BSI CIS can strike the photocathode directly without passing through wiring layer. Thus, photon absorption efficiency increases from 60% to 90%. As the size of the CIS decreases, this performance improves. Now, BSI CIS are widely used in digital cameras, smartphones, etc. However, placing the active matrix transistors behind the photocathode gave rise to a host of new problems, such as cross-talk, which would cause noise and dark-current, and color mixing between adjacent pixels. Solving these problems calls for a low-cost solution in the etch process used in volume production. Etching a BSI CIS film stack is very complex. The etch must pass through approximately half a micron of silicon oxide or nitride, a high-k film and more than 2 microns of silicon. As many of the pre-layers have been planarized, the thickness of oxide/nitride film or silicon film is very variable (typically more than 10%). High etch selectivity and precise time control are therefore necessary. The Applied Materials Centura® AdvantEdge™ Mesa™ etch chamber maintains a high silicon etch rate while preserving a vertical sidewall profile. The oxide/nitride etch rate was acceptable; it also exhibited high selectivity and minimal micro-loading. This chamber was therefore the best choice for this application. The EyeD® endpoint system was used to monitor the interface of the film to control process time. The backside grounding layer (application 1) is similar to pad1. To eliminate deposition voids, a very tapered profile was required (70º+/-5°). The SF6/Cl2/C4F8 recipe could achieve that profile, but had very high silicon etch rate. It would create serious sub-trench issues when the high-k layer was punched through. Its process window was also very marginal. CF4/CHF3 was tested as an alternative, but produced excessive polymer deposition. The profile of high-k became unacceptably tapered. We ultimately used a two-step approach to precisely control polymer deposition and this approach produced a very good profile. For the backside interconnection layer (application 2), tapered profiles were also required. More importantly, the etch had to pass through more than 2 microns of silicon while retaining an approximately 70° profile angle. The gas ratio had to be precise, and pressure was kept at a mid-level. The final profile, which was very good, was superior to that achieved by our competitors. The silicon thickness is very variable because of the limitations of the planarization process. For best production flexibility, we use the EyeD optical endpoint system. Initially, the signal was very weak when the process was deep in the silicon. However, a very robust endpoint was obtained by fine-tuning the EyeD algorithm.