Lateral Metal-oxide-semiconductor Field-effect Transistors Research Articles

Effects of high-temperature diluted-H2 annealing on effective mobility of 4H-SiC MOSFETs with thermally-grown SiO2

The impact of post-oxidation annealing (POA) in diluted-H2 ambient on a 4H-SiC/SiO2 interface was investigated with a cold wall furnace. Effective mobility (μeff) was extracted from lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) by applying the split capacitance–voltage (C–V) technique to the determination of charge density and a calibration technique using two MOSFETs with different gate lengths to minimize the contribution of parasitic components. POA at 1150 °C in diluted-H2 ambient resulted in an enhancement of μeff compared with that for POA in N2 ambient. It was indicated that the effects of POA in diluted H2 should be attributed to the reduction in the density of near interface traps, which disturb the electron transportation in the inversion channel, from the measurement temperature dependence of μeff as well as from the C–V curves of MOS capacitors fabricated on n-type SiC.

Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors

The conduction mechanisms and trapping effects at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors (MOSFETs) were studied by Fowler-Nordheim (FN) tunnelling and frequency dependent conductance measurements. In particular, the analysis of both MOS capacitors and MOSFETs fabricated on the same wafer revealed an anomalous FN behavior on p-type implanted SiC/SiO2 interfaces. The observed FN instability upon subsequent voltage sweeps was correlated to the charge-discharge of hole trap states close the valence band edge of 4H-SiC. The charge-discharge of these traps also explained the recoverable threshold voltage instability observed in lateral MOSFETs.

A simplified thermal model for lateral MOSFET and its application to temperature monitoring

This work presents a novel model to describe the thermal dependence of source-drain voltage of metal-oxide-semiconductor field-effect transistors (MOSFETs) in saturation regime, justified and experimentally tested in n-channel and p-channel transistors. This model provides the temperature coefficient of source-drain voltage as a function of transistor parameters and the drain current as a compact, static dc and empirical model. To do so, an exhaustive thermal characterization of p-channel MOSFET (pMOS) 3N163 (Vishay Siliconix, USA) and n-channel MOSFET (nMOS) 3N170 (Linear Systems, USA) was carried out in the industrial temperature range of −40 °C to 85 °C. Experimental results are in agreement with the proposed thermal model in different current ranges depending on the transistor model, from 15 μA to 700 μA for 3N163 and from 200 μA to 5 mA for 3N170. Finally, the thermal model was applied to design a temperature sensor based on differential measurements of source-drain voltages in a pair of complementary MOSFETs, achieving an average sensitivity of 5.17 ± 0.13 mV °C−2, with a maximum linearity error of 1.1% for the industrial temperature range. This temperature sensor based on MOSFETs offers high sensitivity with a low number of devices and possible compatibility with current manufacturing processes.

Designing of Quasi-Modulated Region in 4H-SiC Lateral RESURF MOSFETs

Characteristics of high-voltage lateral silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) with various reduced surface field (RESURF) structures were simulated. Breakdown voltage was enhanced from 5300 V for single-zone RESURF to 7400 V for two-zone, and to 7600 V for quasi-modulated RESURF MOSFETs.

Alternative method of interface traps passivation by introducing of thin silicon nitride layer at 4H-SiC/SiO2 interface

ABSTRACTAn alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).

Design of Double Gate Vertical MOSFET using Silicon On Insulator (SOI) Technology

Application of symmetric double gate vertical metal oxide semiconductorfield effect transistors (MOSFETs) is hindered by the parasitic overlapcapacitance associated with their layout, which is considerably larger than fora lateral MOSFET on the same technology node. A simple processsimulation has been developed to reduce the parasitic overlap capacitance inthe double gate vertical MOSFETs by using SOI (Silicon on Insulator) inbottom planar surfaces side. The result shows that while channel lengthdecreases, the threshold voltage goes lower, the DIBL rises and subthresholdswing tends to decrease, for both structures. It is noted that the SOI DGVMOSFET structure generally have better performance in SCE controlcompared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially incontrolling the depletion in subthreshold voltage

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.

Ultra-low on-resistance high voltage (> 600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

Silicon carbide oxidation in the presence of cesium: Modeling and analysis

In this work we have focused on investigating the interaction of cesium (Cs) atom/ion with the oxidant and carbon cluster defects at the SiC/SiO2 interface using atomistic scale computational techniques and experimental characterization methods. We observe that Cs behaves significantly different from sodium (Na) at the SiC/SiO2 interface. Our analyses indicate that Cs tends to form a strong bond with the incoming oxygen molecule, leading to the formation of Cs oxide and suboxides. Results suggest that Cs does not reduce the penetration barrier of the impinging oxidant (O2 molecule). Also, unlike Na, Cs is unable to increase the Fermi energy of SiC/SiO2 interface. Finally, lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated (using Cs) yielding mobilities less than 1 cm2/V s versus ∼100 cm2/V s fabricated using Na.

Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide

We propose a new technique for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /4H-SiC (0001) interface by postoxidation annealing using phosphoryl chloride (POCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ). The interface state density near the conduction band edge of 4H-SiC was reduced significantly, and the peak field-effect mobility of lateral 4H-SiC MOSFETs on (0001) Si face was improved to 89 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s by POCl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> annealing at 1000°C.

The Effects of Implant Activation Anneal on the Effective Inversion Layer Mobility of 4H-SiC MOSFETs

In this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC metal oxide semiconductor field-effect transistors (MOSFETs). Initially, lateral n-channel MOSFETs were fabricated with three process splits to investigate phosphorus implant activation anneal temperatures of 1200, 1650, and 1800°C. Mobility results were similar for all three temperatures (using a graphite cap at 1650°C and 1800°C). A subsequent experiment was performed to determine the effect of p-type epi-regrowth on the highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 A p-type regrowth, while growing 0.5 μm or more appears to be sufficient to grow out of the damaged area. A continuing series of tests are being conducted at present.

Lateral power MOSFET for megahertz-frequency, high-density DC/DC converters

DC/DC converters to power future CPU cores mandate low-voltage power metal-oxide semiconductor field-effect transistors (MOSFETs) with ultra low on-resistance and gate charge. Conventional vertical trench MOSFETs cannot meet the challenge. In this paper, we introduce an alternative device solution, the large-area lateral power MOSFET with a unique metal interconnect scheme and a chip-scale package. We have designed and fabricated a family of lateral power MOSFETs including a sub-10 V class power MOSFET with a record-low R/sub DS(ON)/ of 1m/spl Omega/ at a gate voltage of 6V, approximately 50% of the lowest R/sub DS(ON)/ previously reported. The new device has a total gate charge Q/sub g/ of 22nC at 4.5V and a performance figures of merit of less than 30m/spl Omega/-nC, a 3/spl times/ improvement over the state of the art trench MOSFETs. This new MOSFET was used in a 100-W dc/dc converter as the synchronous rectifiers to achieve a 3.5-MHz pulse-width modulation switching frequency, 97%-99% efficiency, and a power density of 970W/in/sup 3/. The new lateral MOSEFT technology offers a viable solution for the next-generation, multimegahertz, high-density dc/dc converters for future CPU cores and many other high-performance power management applications.

Lateral power MOSFETs with drift trench electrodes and drain trench electrodes for a 42 V automotive system

A novel lateral power metal-oxide-semiconductor field-effect transistor (MOSFET) with two kinds of trench electrodes for a 42 V automotive system is presented. The trench electrodes are named a ‘drift trench electrode’ and a ‘drain trench electrode’. It is shown that this MOSFET exhibits a breakdown voltage of 81 V and a specific on-resistance of 67 mΩ·mm2, by a simulation study. Compared with an 80 V-class conventional MOSFET, the specific on-resistance is reduced by 64%. The drift trench electrode works for the reduced surface field (RESURF) action in the off-state in addition to lowering the resistance of the drift region owing to the accumulation layer in the on-state. Alternatively, the drain trench electrode works by spreading the current distribution in the on-state, allowing lower specific on-resistance. Moreover, the conduction loss, the switching loss, and the gate driving loss of the proposed MOSFET were estimated.

Lateral RESURF MOSFET Fabricated on 4H-SiC&amp;lt;tex&amp;gt;$(000bar1)$&amp;lt;/tex&amp;gt;C-Face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.

Breakdown Voltage in Uniaxially Strained n-Channel SOI MOSFET

The drain breakdown voltage of n-channel silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFETs) was found to decrease with the application of uniaxial tensile strain along the channel. The decrease in drain breakdown voltage was found to depend on the direction of the strain applied with respect to the current flow. To investigate the mechanism of this phenomenon, the influence of uniaxial tensile strain on built-in potential at the source junction and on impact ionization was investigated using an SOI lateral diode and bulk MOSFET. Uniaxial strain was induced by mechanically applying bending deformation to the chip using a cantilever structure. Built-in potential at the source junction remained unchanged. Impact ionization rate at the drain edge of MOSFET was found to increase with increasing uniaxial tensile strain. This increase in impact ionization rate is shown to be the cause of the reduced drain breakdown of SOI MOSFET in the presence of uniaxial strain.

Reduction of parasitic capacitance in vertical mosfets by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Enhanced channel mobility of 4H–SiC metal–oxide–semiconductor transistors fabricated with standard polycrystalline silicon technology and gate-oxide nitridation

This work presents improved channel mobility of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) on 4H–SiC, achieved by gate-oxide nitridation in nitric oxide. Lateral enhancement mode MOSFETs were fabricated using standard polycrystalline silicon gate process and 900 °C annealing for the source and drain contacts. The low field mobility of these MOSFETs was as high as 48 cm2/Vs together with a threshold voltage of 0.6 V, while the interface state density—determined from the subthreshold slope—was about 3×1011 eV−1 cm−2. The 43-nm-thick gate oxide of coprocessed metal–oxide–semiconductor structures exhibited a breakdown field strength of 9 MV/cm.

Automotive HID headlamps producing compact electronic ballasts using power ICs

Incandescent halogen lamps have been the standard for automotive headlamps; however, metal halide high-intensity discharge (HID) lamps have slowly begun to be commercially used since the mid-1990s. The lighting system of the metal halide HID headlamp makes a great contribution to energy savings, longer lamp life and better visibility in traffic zones compared with halogen lamps. (Lamp life is lengthened because it prevents the loss of sodium metal as plus ions through the quartz of the lamp bulb.) This article describes power ICs consisting of full bridge inverters and their drivers in detail. Market requirements for electronic ballasts include more compact size, lighter weight, and lower cost. On the other hand, lamp manufacturers recommend that automotive metal halide HID lamps should be operated at negative voltage potential to the body of automotive headlight fixture in order to lengthen lamp life. In order to meet these requirements, a new multichip power integrated circuit (IC) for electronic ballast of automotive HID headlamps has been developed. Discrete power metal-oxide-semiconductor field-effect transistors (MOSFETs) are used for the inverter of the HID electronic ballast. It contains a high-voltage driver IC including a P-channel lateral double diffused MOSFET (LDMOS) to control the full bridge power MOSFETs.

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 /spl Omega/-cm/sup 2/. The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability.

Silicon Field Emitter Arrays Integrated with MOSFET Devices

AbstractWe report a metal oxide semiconductor field effect transistor (MOSFET) controlled field emission array (FEA) device. The device uses a lateral double diffused MOSFET (LD-MOSFET) to control electron supply to the surface. The FEAs were fabricated using isotropic etch of silicon, oxidation sharpening and chemical mechanical polishing. The LD-MOSFETs have a threshold voltage of 0.48V while the FEAs have a turn-on voltage of 28V. Analysis using the FN formulation indicates that a silicon tip radius of 11 nm would fit the FEA IV data. The tip radius from the electrical data is very close to the average tip radius of 10 nm obtained from transmission electron microscope (TEM) analysis. The IV characterization of the MOSFET/FEA demonstrated control of electron emission by the MOSFET gate voltage.