Latency Metric Research Articles

Average Token Delay: A Duration-aware Latency Metric for Simultaneous Translation

Average Token Delay: A Duration-aware Latency Metric for Simultaneous Translation

Identifying properties of pattern completion neurons in a computational model of the visual cortex.

Neural ensembles are found throughout the brain and are believed to underlie diverse cognitive functions including memory and perception. Methods to activate ensembles precisely, reliably, and quickly are needed to further study the ensembles' role in cognitive processes. Previous work has found that ensembles in layer 2/3 of the visual cortex (V1) exhibited pattern completion properties: ensembles containing tens of neurons were activated by stimulation of just two neurons. However, methods that identify pattern completion neurons are underdeveloped. In this study, we optimized the selection of pattern completion neurons in simulated ensembles. We developed a computational model that replicated the connectivity patterns and electrophysiological properties of layer 2/3 of mouse V1. We identified ensembles of excitatory model neurons using K-means clustering. We then stimulated pairs of neurons in identified ensembles while tracking the activity of the entire ensemble. Our analysis of ensemble activity quantified a neuron pair's power to activate an ensemble using a novel metric called pattern completion capability (PCC) based on the mean pre-stimulation voltage across the ensemble. We found that PCC was directly correlated with multiple graph theory parameters, such as degree and closeness centrality. To improve selection of pattern completion neurons in vivo, we computed a novel latency metric that was correlated with PCC and could potentially be estimated from modern physiological recordings. Lastly, we found that stimulation of five neurons could reliably activate ensembles. These findings can help researchers identify pattern completion neurons to stimulate in vivo during behavioral studies to control ensemble activation.

Latency optimization through routing-aware time scheduling protocols for wireless sensor networks

Communications in wireless sensor networks are mainly controlled by the temporal decisions of the data link layer and the spatial decisions of the network layer. When taken independently, these decisions may not be correlated which affects the latency metric. To tackle this problem, we propose cross-layer algorithms to define TDMA (Time Division Multiple Access) schedules based on routing information. Two main strategies are applied, based on routing tree traversals or on adapted ones using information from the network’s graph. We also present the Optimal scheduling algorithm which finds the scheduling with the minimal latency; the latter is used to compute the efficiency of our heuristics. Extensive simulations have been performed and show improvement in latency up to 29% compared with existing works. The effect of the heuristics on the duty-cycle is studied in the perspective of energy consumption. The duty-cycle is improved up to 11.54%.

Prioritisation of alternatives with analytical hierarchy process plus response latency and web surveys

This paper introduces a new method that combines the well-known analytical hierarchy process (AHP) with a response latency metric. The response latency is the time taken by respondents to make choices over pairwise comparisons. The analytical calculation of relative importance weights of the alternatives is made by using a response latency model previously validated in several case studies. This combination aims to overcome some drawbacks of the traditional AHP related to the use of a rating scale (the so-called Saaty scale), and it is a natural way to involve response latency in established decision-making methods. This new method can be profitably adopted in web surveys where it is easy to measure and record response latencies. An application to a new service development was used to test the proposed method. Findings show that the respondent effort, fatigue, and time consumption are drastically reduced, making the survey much simpler and faster. The obtained results seem to be very reliable in terms of judgement consistency.

An adaptive cryptographic engine for internet protocol security architectures

Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectures have to be flexible enough to adapt to diverse security parameters. This article proposes an FPGA-based Adaptive Cryptographic Engine (ACE) for IPSec architectures. By taking advantage of FPGA technology, ACE can adapt to diverse security parameters on the fly while providing superior performance compared with software-based solutions. In this paper, we focus on performance issues. A diverse set of private-key cryptographic algorithms is utilized to demonstrate the applicability of the proposed cryptographic engine. The time performance metrics are throughput and key-setup latency. The latency metric is the most important measure for IPSec where a small amount of data is processed per key and key context switching occurs repeatedly. We are not aware of any published results that include extensive key-setup latency results.

Latency Metric: An Experimental Method for Measuring and Evaluating Parallel Program and Architecture Scalability

Latency measures the delay caused by communication between processors and memory modules over the network in a parallel system. Using intensive measurements and simulation, we show that network latency forms a major obstacle to improving parallel computing performance and scalability. We present an experimental metric, using network latency to measure and evaluate the scalability of parallel programs and architectures. This latency metric is an extension to the isoefficiency function [Grama et al., IEEE Parallel Distrib. Technology 1, 3 (1993), 12-21] and iso-speed metric [Sun and Rover, IEEE Trans. Parallel Distrib. Systems 5, 6 (1994), 599-613]. We give a measurement method for using this latency metric, and report the experimental results of evaluating the scalabilities of several scientific computing algorithms on the KSR-1 shared-memory architecture. Our analysis and experiments show that the latency metric is a practical method to effectively predict and evaluate scalability based on measured latencies inherent in the program and the architecture.