Large-scale Spiking Neural Networks Research Articles

Spiking mode-based neural networks.

Spiking neural networks play an important role in brainlike neuromorphic computations and in studying working mechanisms of neural circuits. One drawback of training a large-scale spiking neural network is that updating all weights is quite expensive. Furthermore, after training, all information related to the computational task is hidden into the weight matrix, prohibiting us from a transparent understanding of circuit mechanisms. Therefore, in this work, we address these challenges by proposing a spiking mode-based training protocol, where the recurrent weight matrix is explained as a Hopfield-like multiplication of three matrices: input modes, output modes, and a score matrix. The first advantage is that the weight is interpreted by input and output modes and their associated scores characterizing the importance of each decomposition term. The number of modes is thus adjustable, allowing more degrees of freedom for modeling the experimental data. This significantly reduces the training cost because of significantly reduced space complexity for learning. Training spiking networks is thus carried out in the mode-score space. The second advantage is that one can project the high-dimensional neural activity (filtered spike train) in the state space onto the mode space which is typically of a low dimension, e.g., a few modes are sufficient to capture the shape of the underlying neural manifolds. We successfully apply our framework in two computational tasks-digit classification and selective sensory integration tasks. Our method thus accelerates the training of spiking neural networks by a Hopfield-like decomposition, and moreover this training leads to low-dimensional attractor structures of high-dimensional neural dynamics.

Leaky-integrate-fire neuron based on vertically extended drain Si[formula omitted]Ge[formula omitted] source TFET: Ultra-energy-efficient and high speed design

This article investigates the performance of a vertically extended drain double gate Si1−x Gex source tunnel field effect transistor (VD-DG-Si1−x Gex S-TFET) as a leaky integrate-and-fire (LIF) neuron. The proposed VD-DG-Si1−x Gex S-TFET structure has been designed and optimized by deploying the commercially available Silvaco TCAD. The LIF neuron using VD-DG-Si1−x Gex S-TFET requires a low spiking threshold voltage (i.e. 0.20 V) which is 5x, 3x, 5x, 1.3x, 1.55x, 7.5x, and 1.44x times less in comparison to MOSFET, Bulk FinFET, phase change device, SOI MOSFET, DG-JLFET, silicon nanowire, and DL-TFET silicon neuron. The proposed device based neuron demonstrates the least spiking energy (177 ZJ) reported to date which is 18192 times less as compared to BTBT based PDSOI MOSFET neuron. The threshold value of current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DL-TFET, respectively. Moreover, the effects of gate metal work function, germanium mole fraction, and temperature on the spike current variations have also been investigated. Here, impact ionization is a key method for generating a neuron spike due to holes accumulated in the potential well of VD-DG-Si1−xGex S-TFET. In addition, a LIF neuron based on VD-DG-Si0.5Ge0.5 S-TFET device exhibits a 9 THz spiking frequency which is approximately 12 times higher than real nerves present in the human body. This work shows a remarkable reduction in the power consumption and the proposed device neuron is a potential start-up solution for a large scale spiking neural networks (SNN) implementation because of its better performance and compact circuitry.

Harnessing Manycore Processors with Distributed Memory for Accelerated Training of Sparse and Recurrent Models

Current AI training infrastructure is dominated by single instruction multiple data (SIMD) and systolic array architectures, such as Graphics Processing Units (GPUs) and Tensor Processing Units (TPUs), that excel at accelerating parallel workloads and dense vector matrix multiplications. Potentially more efficient neural network models utilizing sparsity and recurrence cannot leverage the full power of SIMD processor and are thus at a severe disadvantage compared to today's prominent parallel architectures like Transformers and CNNs, thereby hindering the path towards more sustainable AI. To overcome this limitation, we explore sparse and recurrent model training on a massively parallel multiple instruction multiple data (MIMD) architecture with distributed local memory. We implement a training routine based on backpropagation though time (BPTT) for the brain-inspired class of Spiking Neural Networks (SNNs) that feature binary sparse activations. We observe a massive advantage in using sparse activation tensors with a MIMD processor, the Intelligence Processing Unit (IPU) compared to GPUs. On training workloads, our results demonstrate 5-10x throughput gains compared to A100 GPUs and up to 38x gains for higher levels of activation sparsity, without a significant slowdown in training convergence or reduction in final model performance. Furthermore, our results show highly promising trends for both single and multi IPU configurations as we scale up to larger model sizes. Our work paves the way towards more efficient, non-standard models via AI training hardware beyond GPUs, and competitive large scale SNN models.

Large-Scale Bio-Inspired FPGA Models for Path Planning.

The hippocampus provides significant inspiration for spatial navigation and memory in both humans and animals. Constructing large-scale spiking neural network (SNN) models based on the biological neural systems is an important approach to comprehend the computational principles and cognitive function of the hippocampus. Such models are usually implemented on neuromorphic computing platforms, which often have limited computing resources that constrain the achievable scale of the network. This work introduces a series of digital design methods to realize a Field-Programmable Gate Array (FPGA) friendly SNN model. The methods include FPGA-friendly nonlinear calculation modules and a fixed-point design algorithm. A brain-inspired large-scale SNN of ∼21 k place cells for path planning is mapped on FPGA. The results show that the path planning tasks in different environments are finished in real-time and the firing activities of place cells are successfully reproduced. With these methods, the achievable network size on one FPGA chip is increased by 1595 times with higher resource usage efficiency and faster computation speed compared to the state-of-the-art.

Leaky-integrate-and-fire operation with signal amplification using gate-controlled carrier-injection silicon-on-insulator transistor

This work demonstrated leaky-integrate-and-fire (LIF) behavior using a gate-controlled carrier-injection silicon-on-insulator transistor (GCCI SOI-Tr) and confirmed its signal amplification capability. We believe that a large-scale spiking neural network requires neural devices capable of signal amplification to effectively drive multiple post-synaptic neurons. The GCCI SOI-Tr could realize a capacitorless LIF behavior with a gate-controlled weight parameter. In addition, significant signal amplification might be achieved by scaling the GCCI SOI-Tr.

Memory-efficient neurons and synapses for spike-timing-dependent-plasticity in large-scale spiking networks.

This paper addresses the challenges posed by frequent memory access during simulations of large-scale spiking neural networks involving synaptic plasticity. We focus on the memory accesses performed during a common synaptic plasticity rule since this can be a significant factor limiting the efficiency of the simulations. We propose neuron models that are represented by only three state variables, which are engineered to enforce the appropriate neuronal dynamics. Additionally, memory retrieval is executed solely by fetching postsynaptic variables, promoting a contiguous memory storage and leveraging the capabilities of burst mode operations to reduce the overhead associated with each access. Different plasticity rules could be implemented despite the adopted simplifications, each leading to a distinct synaptic weight distribution (i.e., unimodal and bimodal). Moreover, our method requires fewer average memory accesses compared to a naive approach. We argue that the strategy described can speed up memory transactions and reduce latencies while maintaining a small memory footprint.

55 nm CMOS Mixed-Signal Neuromorphic Circuits for Constructing Energy-Efficient Reconfigurable SNNs

The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

The High-Performance Design of a General Spiking Convolution Computation Unit for Supporting Neuromorphic Hardware Acceleration

Recently, the design of spiking neural networks (SNNs) processors based on FPGA have become a hot research topic for their low power and high efficiency. However, most existing works lack flexibility in configuration to accomplish efficient computation of deep SNNs with different network structures (e.g., residuals). In this brief, a high-performance general spiking convolution processing unit and the corresponding hardware architecture (named SCPU) is designed to support both standard and residual convolution; then, a neuromorphic processor containing SCPU (called FPGA-SCPP) is implemented on Xilinx Virtex-7 FPGA. Specifically, the model parameters are fused and quantified to reduce the computational amounts and simplify its hardware implementation. And a spike event processing unit is designed based on event computation and direct data flow to complete the standard and residual convolution computations. The experimental results show the FPGA-SCPP can effectively deploy different large-scale SNNs models such as VGG and ResNet, with the highest recognition accuracies of 92.45% and 68.55% on CIFAR-10/CIFAR-100, respectively. Our FPGA-SCPP has a computational power of only 1.7W and a frame rate of 40fps, which improves inference speed by about 6 times and reduces power consumption by 3 times compared to existing processors. Therefore, FPGA-SCPP can effectively accomplish the acceleration of deep SNNs, especially for models with spiking residual blocks.

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit

In this brief, we propose a Resistive Random Access Memory (RRAM) based self-resetting Integrate and Fire ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}\&amp;\text{F}$ </tex-math></inline-formula> ) neuron. The proposed neuron circuit does not require any external bias voltage and the integration of control unit required to reset RRAM into neuron circuit optimizes its overall power consumption. The neuron circuit proposed in this brief consists of two RRAMs for integrate and fire operations, whereas, pulse propogation and reset circuit consists of 22 CMOS transistors. It consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~fJ$ </tex-math></inline-formula> per spike, which is 48% and 53% less than the recent neurons designed using, nanoscale FBFET and PDSOI-MOSFET, respectively. The operating frequency of proposed neuron ranges from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$277~KHz$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$03~MHz$ </tex-math></inline-formula> , which is at least 7.5% and 10% higher than the operating frequencies of above mentioned recent neurons, respectively. The inclusion of reset circuit into RRAM based neuron circuit enables the implementation of large scale spiking neural network (SNN), which makes it superior in terms of power and energy consumption.

Efficient parameter calibration and real-time simulation of large-scale spiking neural networks with GeNN and NEST.

Spiking neural networks (SNNs) represent the state-of-the-art approach to the biologically realistic modeling of nervous system function. The systematic calibration for multiple free model parameters is necessary to achieve robust network function and demands high computing power and large memory resources. Special requirements arise from closed-loop model simulation in virtual environments and from real-time simulation in robotic application. Here, we compare two complementary approaches to efficient large-scale and real-time SNN simulation. The widely used NEural Simulation Tool (NEST) parallelizes simulation across multiple CPU cores. The GPU-enhanced Neural Network (GeNN) simulator uses the highly parallel GPU-based architecture to gain simulation speed. We quantify fixed and variable simulation costs on single machines with different hardware configurations. As a benchmark model, we use a spiking cortical attractor network with a topology of densely connected excitatory and inhibitory neuron clusters with homogeneous or distributed synaptic time constants and in comparison to the random balanced network. We show that simulation time scales linearly with the simulated biological model time and, for large networks, approximately linearly with the model size as dominated by the number of synaptic connections. Additional fixed costs with GeNN are almost independent of model size, while fixed costs with NEST increase linearly with model size. We demonstrate how GeNN can be used for simulating networks with up to 3.5 · 106 neurons (> 3 · 1012synapses) on a high-end GPU, and up to 250, 000 neurons (25 · 109 synapses) on a low-cost GPU. Real-time simulation was achieved for networks with 100, 000 neurons. Network calibration and parameter grid search can be efficiently achieved using batch processing. We discuss the advantages and disadvantages of both approaches for different use cases.

Computation and implementation of large scalable Spiking Neural Network

Photonic neural networks are a highly sought-after area of research due to their potential for high-performance complex computing. Unlike artificial neural networks, which use simple nonlinear maps, biological neurons transmit information and perform computations through spikes that depend on spike time and/or rate. Through comprehensive studies and experiments, a strong foundation has been laid for the development of photonic neural networks. We have recently developed a large-scale spiking neural network, which serves as a proof-of-concept experiment for novel bio-inspired learning concepts. This breakthrough is significant because it demonstrates the potential of using photonic neural networks for advanced computing and highlights the importance of incorporating biological principles into artificial intelligence research.

Deploying and Optimizing Embodied Simulations of Large-Scale Spiking Neural Networks on HPC Infrastructure.

Simulating the brain-body-environment trinity in closed loop is an attractive proposal to investigate how perception, motor activity and interactions with the environment shape brain activity, and vice versa. The relevance of this embodied approach, however, hinges entirely on the modeled complexity of the various simulated phenomena. In this article, we introduce a software framework that is capable of simulating large-scale, biologically realistic networks of spiking neurons embodied in a biomechanically accurate musculoskeletal system that interacts with a physically realistic virtual environment. We deploy this framework on the high performance computing resources of the EBRAINS research infrastructure and we investigate the scaling performance by distributing computation across an increasing number of interconnected compute nodes. Our architecture is based on requested compute nodes as well as persistent virtual machines; this provides a high-performance simulation environment that is accessible to multi-domain users without expert knowledge, with a view to enable users to instantiate and control simulations at custom scale via a web-based graphical user interface. Our simulation environment, entirely open source, is based on the Neurorobotics Platform developed in the context of the Human Brain Project, and the NEST simulator. We characterize the capabilities of our parallelized architecture for large-scale embodied brain simulations through two benchmark experiments, by investigating the effects of scaling compute resources on performance defined in terms of experiment runtime, brain instantiation and simulation time. The first benchmark is based on a large-scale balanced network, while the second one is a multi-region embodied brain simulation consisting of more than a million neurons and a billion synapses. Both benchmarks clearly show how scaling compute resources improves the aforementioned performance metrics in a near-linear fashion. The second benchmark in particular is indicative of both the potential and limitations of a highly distributed simulation in terms of a trade-off between computation speed and resource cost. Our simulation architecture is being prepared to be accessible for everyone as an EBRAINS service, thereby offering a community-wide tool with a unique workflow that should provide momentum to the investigation of closed-loop embodiment within the computational neuroscience community.

Advancements in Algorithms and Neuromorphic Hardware for Spiking Neural Networks.

Artificial neural networks (ANNs) have experienced a rapid advancement for their success in various application domains, including autonomous driving and drone vision. Researchers have been improving the performance efficiency and computational requirement of ANNs inspired by the mechanisms of the biological brain. Spiking neural networks (SNNs) provide a power-efficient and brain-inspired computing paradigm for machine learning applications. However, evaluating large-scale SNNs on classical von Neumann architectures (central processing units/graphics processing units) demands a high amount of power and time. Therefore, hardware designers have developed neuromorphic platforms to execute SNNs in and approach that combines fast processing and low power consumption. Recently, field-programmable gate arrays (FPGAs) have been considered promising candidates for implementing neuromorphic solutions due to their varied advantages, such as higher flexibility, shorter design, and excellent stability. This review aims to describe recent advances in SNNs and the neuromorphic hardware platforms (digital, analog, hybrid, and FPGA based) suitable for their implementation. We present that biological background of SNN learning, such as neuron models and information encoding techniques, followed by a categorization of SNN training. In addition, we describe state-of-the-art SNN simulators. Furthermore, we review and present FPGA-based hardware implementation of SNNs. Finally, we discuss some future directions for research in this field.

Robust Resting-State Dynamics in a Large-Scale Spiking Neural Network Model of Area CA3 in the Mouse Hippocampus.

Hippocampal area CA3 performs the critical auto-associative function underlying pattern completion in episodic memory. Without external inputs, the electrical activity of this neural circuit reflects the spontaneous spiking interplay among glutamatergic pyramidal neurons and GABAergic interneurons. However, the network mechanisms underlying these resting-state firing patterns are poorly understood. Leveraging the Hippocampome.org knowledge base, we developed a data-driven, large-scale spiking neural network (SNN) model of mouse CA3 with 8 neuron types, 90,000 neurons, 51 neuron-type specific connections, and 250,000,000 synapses. We instantiated the SNN in the CARLsim4 multi-GPU simulation environment using the Izhikevich and Tsodyks-Markram formalisms for neuronal and synaptic dynamics, respectively. We analyzed the resultant population activity upon transient activation. The SNN settled into stable oscillations with a biologically plausible grand-average firing frequency, which was robust relative to a wide range of transient activation. The diverse firing patterns of individual neuron types were consistent with existing knowledge of cell type-specific activity in vivo. Altered network structures that lacked neuron- or connection-type specificity were neither stable nor robust, highlighting the importance of neuron type circuitry. Additionally, external inputs reflecting dentate mossy fibers shifted the observed rhythms to the gamma band. We freely released the CARLsim4-Hippocampome framework on GitHub to test hippocampal hypotheses. Our SNN may be useful to investigate the circuit mechanisms underlying the computational functions of CA3. Moreover, our approach can be scaled to the whole hippocampal formation, which may contribute to elucidating how the unique neuronal architecture of this system subserves its crucial cognitive roles.

Dopingless-TFET Leaky-Integrated-Fire (LIF) Neuron For High-Speed Energy Efficient Applications

The silicon based dopingless tunnel field effect transistor (DL-TFET) demonstrates artificial neuromorphic property for leaky-integrate-fire (LIF) neurons characteristics due to impact ionization. Using the calibrated simulations, this research article reports an ultra-high speed and ultra-energy efficient silicon based electrical neuron realization for emulating biological neuron behaviour. The reported DL-TFET exhibits a very low threshold voltage of 0.289 V and minimum energy of 1.5 aJ to fire a spike signal which is very low in comparison to the earlier reported literature. Here, impact ionization is the dominant mechanism for producing spiking behaviour due to induced holes storage in the potential well of DL-TFET. Furthermore, the DL-TFET device working as a LIF neuron reported around 0.6 THz spiking frequency. This work exhibits a significant reduction in energy consumption and overcomes the limitations of analog/digital circuit-based LIF neurons. Hence, DL-TFET based LIF neuron is a potential solution for implementing large-scale spiking neural networks (SNN) because of its compact circuitry and better efficiency.

Exploiting the electrothermal timescale in PrMnO3 RRAM for a compact, clock-less neuron exhibiting biological spiking patterns

Spiking neural networks (SNNs) are gaining widespread momentum in the field of neuromorphic computing. These network systems integrated with neurons and synapses provide computational efficiency by mimicking the human brain. It is desired to incorporate the biological neuronal dynamics, including complex spiking patterns which represent diverse brain activities within the neural networks. Earlier hardware realization of neurons was (a) area intensive because of large capacitors in the circuit design, (b) neuronal spiking patterns were demonstrated with clocked neurons at the device level. To achieve more realistic biological neuron spiking behavior, emerging memristive devices are considered promising alternatives. In this paper, we propose, PrMnO3 (PMO)-resistive random-access memory (RRAM) device-based neuron. The voltage-controlled electrothermal timescales of the compact PMO RRAM device replace the electrical timescales of charging a large capacitor. The electrothermal timescale is used to implement an integration block with multiple voltage-controlled timescales coupled with a refractory block to generate biological neuronal dynamics. Here, first, a Verilog-A implementation of the thermal device model is demonstrated, which captures the current-temperature dynamics of the PMO device. Second, a driving circuitry is designed to mimic different spiking patterns of cortical neurons, including intrinsic bursting and chattering. Third, a neuron circuit model is simulated, which includes the PMO RRAM device model and the driving circuitry to demonstrate the asynchronous neuron behavior. Finally, a hardware-software hybrid analysis is done in which the PMO RRAM device is experimentally characterized to mimic neuron spiking dynamics. The work presents a realizable and more biologically comparable hardware-efficient solution for large-scale SNNs.

HuRAI: A brain-inspired computational model for human-robot auditory interface

The deep learning era endows immense opportunities for ubiquitous robotic applications by leveraging big data generated from widespread sensors and ever-growing computing capability. While the growing demands for natural human-robot interaction (HRI) as well as concerns for energy efficiency, real-time performance, and data security motive novel solutions. In this paper, we present a brain-inspired spiking neural network (SNN) based Human-Robot Auditory Interface, namely HuRAI. The HuRAI integrates the voice activity detection, speaker localization and voice command recognition systems into a unified framework that can be implemented on the emerging low-power neuromorphic computing (NC) devices. Our experimental results demonstrate superior modeling capabilities of SNNs, achieving accurate and rapid prediction for each task. Moreover, the energy efficiency analysis reveals a compelling prospect, with up to three orders of magnitude energy savings, over the equivalent artificial neural networks that running on the state-of-the-art Nvidia graphics processing unit (GPU). Therefore, integrating the algorithmic power of large-scale SNN models and the energy efficiency of NC devices offers an attractive solution for real-time, low-power robotic applications.

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits.

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

Assessment of optogenetically-driven strategies for prosthetic restoration of cortical vision in large-scale neural simulation of V1

The neural encoding of visual features in primary visual cortex (V1) is well understood, with strong correlates to low-level perception, making V1 a strong candidate for vision restoration through neuroprosthetics. However, the functional relevance of neural dynamics evoked through external stimulation directly imposed at the cortical level is poorly understood. Furthermore, protocols for designing cortical stimulation patterns that would induce a naturalistic perception of the encoded stimuli have not yet been established. Here, we demonstrate a proof of concept by solving these issues through a computational model, combining (1) a large-scale spiking neural network model of cat V1 and (2) a virtual prosthetic system transcoding the visual input into tailored light-stimulation patterns which drive in situ the optogenetically modified cortical tissue. Using such virtual experiments, we design a protocol for translating simple Fourier contrasted stimuli (gratings) into activation patterns of the optogenetic matrix stimulator. We then quantify the relationship between spatial configuration of the imposed light pattern and the induced cortical activity. Our simulations in the absence of visual drive (simulated blindness) show that optogenetic stimulation with a spatial resolution as low as 100 upmum, and light intensity as weak as 10^{16} photons/s/cm^2 is sufficient to evoke activity patterns in V1 close to those evoked by normal vision.

Transitioning Spiking Neural Network Simulators to Heterogeneous Hardware

Spiking neural networks (SNN) are among the most computationally intensive types of simulation models, with node counts on the order of up to 10 11 . Currently, there is intensive research into hardware platforms suitable to support large-scale SNN simulations, whereas several of the most widely used simulators still rely purely on the execution on CPUs. Enabling the execution of these established simulators on heterogeneous hardware allows new studies to exploit the many-core hardware prevalent in modern supercomputing environments, while still being able to reproduce and compare with results from a vast body of existing literature. In this article, we propose a transition approach for CPU-based SNN simulators to enable the execution on heterogeneous hardware (e.g., CPUs, GPUs, and FPGAs), with only limited modifications to an existing simulator code base and without changes to model code. Our approach relies on manual porting of a small number of core simulator functionalities as found in common SNN simulators, whereas the unmodified model code is analyzed and transformed automatically. We apply our approach to the well-known simulator NEST and make a version executable on heterogeneous hardware available to the community. Our measurements show that at full utilization, a single GPU achieves the performance of about 9 CPU cores. A CPU-GPU co-execution with load balancing is also demonstrated, which shows better performance compared to CPU-only or GPU-only execution. Finally, an analytical performance model is proposed to heuristically determine the optimal parameters to execute the heterogeneous NEST.