Large Scale Integrated Circuit Chips Research Articles

Silicon interposer BGA package with a Cu-filled through silicon via and a multilayer redistribution layer fabricated via electroplating.

As large-scale integrated circuit chips become smaller, conventional organic buildup substrates can no longer support them. To resolve this problem, silicon interposers with through silicon via (TSV) technology are gaining recognition as alternative solution to provide high-density interconnection, improved electrical performance due to shorter interconnection from the die to substrate for nano-scale devices. In this study, we fabricated a silicon interposer to achieve high density and high performance packages. Via holes were etched via the Bosch process using a deep reactive ion etcher and SiO2 formed with a diffusion furnace as the diffusion barrier of the Cu electrode. TSVs were filled with Cu under various electroplating conditions. After Cu filling, a Cu post was formed directly using the over-filled Cu electrode through a chemical mechanical polishing process. A double-layer redistribution layer was formed on one side of the interposer using a lift-off process. Sn-3.5% Ag solder bumps 40 μm in diameter were formed directly on the Cu post on another side of the interposer using electroplating and the reflow method.

Circuit Architecture Test Verification Based on Hardware Software Co-design with ModelSim

In view of the recent paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs), the complexity of digital circuits has enormously increased. This growing complexity has resulted in a huge challenge in developing their appropriate and efficient fault testing environment. Despite significant efforts directed toward implementing effective testing strategies of very large scale integrated circuit chips with reasonable cost, new frontiers emerged with advances in technology. The subject paper endeavors to develop method to test verify circuit architecture under hardware software co-design environment, targeting specifically embedded cores-based SOCs. The concept of design-for-testability is utilized in the paper together with ModelSim simulation and verification tool to test synthesize the entire design. Some simulation results on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits are also included with a comparison of the results with some earlier works.

Intra-system optical interconnection module directly integrated on a polymeric optical waveguide

A new intra-system optical interconnection module directly integrated on a polymeric optical waveguide is suggested. A polymeric optical waveguide plays a role in the propagation path of optical signals from the transmitter to the receiver and in a platform integrated with various optical/electrical devices such as a vertical cavity surface emitting laser, photodiode, very large scale integrated circuit chips, and electrical connectors. Because the polymeric optical waveguide is simultaneously used as an integrated platform, the fabrication process of the optical interconnection module is very simple, and the proposed process is compatible with the conventional printed circuit board process. The suggested optical interconnection was also successfully demonstrated with a 5-Gb/s data transmission through the module directly integrated on a polymeric optical waveguide.

Nondestructive Evaluation of Thermal Phase Growth in Solder Ball Microjoints by Synchrotron Radiation X-Ray Microtomography

In high-density packaging technology, one of the most important issues is the reliability of the microjoints connecting large scale integrated circuit chips to printed circuit boards electrically and mechanically. The development of nondestructive testing methods with high spatial resolution is expected to enhance reliability. An X-ray microtomography system called SP-μCT has been developed in Super Photon ring-8 GeV (SPring-8), the largest synchrotron radiation facility in Japan. In this work, SP-μCT was applied in the nondestructive evaluation of microstructure evolution, that is, the phase growth due to thermal cyclic loading in solder ball microjoints. Simulating solder microjoints used in a flip chip, specimens were fabricated by joining a Sn–Pb eutectic solder ball 100 μm in diameter to a steel pin in the usual reflow soldering process. The phase growth process was determined by observing the computed tomography (CT) images obtained consecutively at the fixed point of the target joining. In the reconstructed CT images, the distribution of the constituent phases in the Sn–Pb eutectic solder was identified based on the estimation value of the X-ray linear attenuation coefficient. Consequently, the microstructure images obtained nondestructively by SP-μCT provided us with the following useful information for evaluating the reliability of the solder microjoints. First, each phase involves not dispersing particles but a three-dimensional monolithic structure like a sponge. Second, the phase growth proceeds in such a way that the average phase size to the fourth power increases proportionally to the number of cycles. Finally, in the vicinity of the joining interface, more rapid phase growth occurs compared to the other regions because local thermal strain due to the mismatch of thermal expansion leads to a remarkable phase growth.

Multi-picture system for high resolution wide aspect ratio screen

Two novel LSI (large-scale-integrated circuit) chips for multi-picture function have been developed. These are an aspect ratio converter of IDTV (improved-definition TV) signals and a picture-in-picture processor for HDTV (high-definition TV) and NTSC signals. This IC system has achieved a multi-picture function on a wide-aspect-ratio screen.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The generation of three-dimensional bipolar transistor models for circuit analysis

The results of a two-dimensional bipolar numerical device-analysis program are processed by identifying three regions of the transistor: the intrinsic transistor, the sidewall transistor, and the extrinsic base collector diode. The key parameters which describe each of these regions are extracted using a linking program and fed into a quasi-three-dimensional device analysis program referred to here as the Model Generation Program (MGP). The MGP first generates a large equivalent-circuit distributed network which simulates the three-dimensional geometry of an actual transistor. This distributed network is then analyzed using the existing Advanced Statistical Analysis Program (ASTAP) for circuit analysis. Finally the MGP extracts parameters from the ASTAP analysis to characterize the elements of a lumped-model equivalent circuit, which is then suitable for the circuit design of large-scale integrated circuit chips. The MGP is sufficiently flexible that transistors with a variety of geometries can be generated without repeating the two-dimensional analysis.

Large scale integrated circuit chip for an electronic organ

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Large scale integrated circuit chip for an electronic organ

Large scale integrated circuit chip for an electronic organ

Master control LSI clip

In an electronic organ or the like constructed of a plurality of large scale integrated circuit (LSI) chips, the present disclosure relates to a master control LSI chip having a counter providing multiplexing drive outputs and also having a read only memory (ROM) programmed to provide rhythm voice patterns.

Envelope control causing damper effect on percussive voices of electronic musical instrument

A large scale integrated circuit chip is provided with internal tone generators and digital attack and decay features interconnected with external capacitors for controlling the attack and decay of tones. External diodes are wired to the chip and to the external capacitors and have a circuit completed by a damper switch. According to the position of the switch the capacitors will discharge slowly for long sustain of tones, or will discharge very rapidly through an additional discharge path on the chip upon key release to produce very rapid decay.

Automatic chord control circuit for electronic musical instruments

An automatic chord control system is readily incorporated in an electronic organ by means of large scale integrated circuit chips. The automatic chord control causes a chord or group of notes within an octave played on the lower manual keyboard to play through the upper manual voice in the octave below the lowest melody note being played on the upper manual keyboard. The proposed automatic chord control system has two operating modes. In the first mode, the notes transferred to the upper manual are generated in direct correspondence to the keys activated on the lower manual. In the second mode, the notes transferred to the upper manual are generated by a set of preset chords activated by single lower manual keys.

Electronic musical instrument using plural programmable divider circuits

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An Accumulator Chip

A large-scale integrated-circuit chip has been designed under the sponsorship of the Air Force Avionics Laboratory. The chip was developed as part of a logic synthesizer effort of the Design Automation group at Litton Systems, Inc., Guidance and Control Systems Division. It was designed as a type or category to be multiply used with one other gating type chip whose format is prescribed by the logic synthesizer. A major goal of this effort will be to design a complete digital system by design-automated techniques using only these two types of chips in a large-scale array.