Kogge Stone Research Articles

Design and FPGA Implementation of High Speed Vedic Multiplier

is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing respective algorithms. The below two algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on Xilinx Spartan 3 and Spartan 6 FPGA kit using Xilinx ISE 9.1i. The propagation delay of the implemented architecture is obtained to be 28.699ns and 15.752ns respectively.

A highly sensitive and ultra low‐power forward body biasing circuit to overcome severe process, voltage and temperature variations and extreme voltage scaling

SummaryDynamic voltage scaling is one of the most popular methods used to reduce energy consumption in today's digital electronic systems. However, addressing process, voltage and temperature variations at subthreshold voltages has become an inevitable procedure. Using a variation‐sensitive and ultra low‐power design, this paper proposed a novel technique capable of sensing and responding to process, voltage and temperature variations as well as dynamic voltage scaling by providing an appropriate forward body bias so that energy‐delay product of the whole system was improved. Theoretical analysis for process variation probability, confirmed by post‐layout HSPICE (Synopsys, Inc., Mountain View, CA) simulations for an 8‐bit pipelined Kogge–Stone adder, showed that the circuit performance was enhanced in severe variations and extreme voltage scaling situation. For this adder, for example, assuming a voltage scaling from 0.8 to 0.3 V and temperature changes of −15 to 75 °C, the proposed technique brought about a seven times less delay variation, whereas energy‐delay product improved by 23% compared with a zero body biased adder. Copyright © 2013 John Wiley & Sons, Ltd.

Efficient Carry Select Adder Design for FPGA Implementation

Digital adder with optimum area and speed is one of the important areas of research in VLSI system design. This paper discusses about the efficient implementation of parallel adder with optimized area and propagation delay for FPGA applications. Our approach uses carry select adder configuration and parallel adder approach for the implementation of fast adder. There are different choices for implementing carry select adder. We compare some of these methods and choose the one appropriate for FPGA implementation. Two different approaches for implementing linear carry select adder using Kogge Stone configuration are discussed here and compared in terms of area and speed. Both approaches are implemented on an FPGA and the performance is compared. Simulation results are used to verify the theory.

Comparative Study of High performance Braun’s Multiplier using FPGAs

Multiplication is one of the essential operations in Digital Signal Processing (DSP) applications like Fast Fourier Transform (FFT), Digital filters etc. With the advancements in technology, research is still going on to design a multiplier that consumes less power or has high speed or occupies less area or a combination of these in a single multiplier. This makes the multipliers to be used for high speed or low power VLSI applications. The Braun’s multiplier is one of the parallel array multiplier which is used for unsigned numbers multiplication. The dynamic power of the multiplier can be reduced by using the bypassing techniques. The delay can be reduced by replacing the ripple carry adder in the last stage by fast adders like Carry look ahead adder and Kogge stone adder. This paper presents a comparative study among different types of bypassing multipliers for 4*4, 8*8 and 16*16 bits and their architectural modifications using different FPGAs like Spartan – 3E, Virtex – 4, Virtex – 5 and Virtex – 6 Lower power using Xilinx 13.2 ISE tool from which we get the delay and the dynamic power and cell area reports are obtained using RTL Compiler from Cadence in 90 nm technology.

Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system

In this paper, a new model based on an improved Brent Kung (BK) parallel prefix network (PPN) algorithm is proposed and realized in the field programmable gate array (FPGA). This model is employed in the implementation of 20 Gb/s differential quadrature phase-shift keying (DQPSK) precoder in 40 Gb/s polarization division multiplex (PolDM) DQPSK system. In the computation process, the computation complexity (area) optimization with fan-out limited is achieved. In the implementation, 770 FPGA slice registers are utilized, which save about 60% logic resources compared with the previous Kogge Stone (KS) algorithm.