Ka-band Power Amplifier Research Articles

A Ka-band 27.6-dBm power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology

This paper presents a Ka-band power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology. The amplifier employs a quad-branch topology based on zero-degree power combiners/splitters, with each branch comprising two differential stages, each containing four stacked FETs. With a compression-state large-signal matching approach, this design achieves the saturated output power (Psat) of 27.6 dBm with 14.1 % peak power added efficiency (PAE), output 1-dB compression point (OP1dB) of 20.1 dBm at 35 GHz, according to electromagnetic simulation (EM) results. Additionally, it exhibits a peak gain of 39.2 dB at 33 GHz and a 3-dB bandwidth across 32–38 GHz. Offering a low-cost solution suitable for phased array radars and satellite communications.

Area Efficient and Linear MMIC Based Ka Band Power Amplifier for 5G Communication Systems

This work presents a monolithic microwave integrated circuit (MMIC) based power amplifier (PA) with single 150 nm GaN high electron mobility transistor (HEMT) using broadband matching. For the proposed amplifier, two stage L-type biasing network is designed. In order to provide good linearity, low Q, broader bandwidth and optimized chip area, band pass filter (BPF) type matching network is proposed. The topology and parameter selection is done by performing proper load pull analysis. This helps in achieving wide band matching to maintain low Q factor. Thus the proposed amplifier is evaluated with post layout EM simulation data. For the 26 GHz band of 5G communication, proposed amplifier has a small signal gain of 11 dB for 21-27.4 GHz. The amplifier offers 33.42 dBm saturated output power and good linearity. The designed PA provides 31.35 dBm output power, 26% power added efficiency (PAE) and 29% drain efficiency (DE) at 1 dB compression with IP3 of 39.67 dBm for 26 GHz band. The designed PA has less complexity and small chip area of 4.3 mm2.

Design of a Ka-band power amplifier

This paper introduces the design of a type of power amplifier working in the Ka-band, which has three stages based on 45nm CMOS technology. The operating frequency is 25-27GHz, and it has good efficiency and linearity. Among them, the driving stage adopts a cascode structure, the power stage adopts common source structure, and the matching network adopts a transformer structure. Using Cadence Virtuoso for simulation at the operating voltage of 1.8V, power gain of the single-ended power amplifier is 44.76 dB, saturation output power is 14.66 dBm, the output power at the 1dB compression point is 12.9dBm, and corresponding power-added efficiency is 22.19%.

A Ka-band Power Amplifier with On-chip Power Detector in 0.15 μm GaAs pHEMT Technology

A three stage 28 GHz power amplifier (PA) with on-chip power detector is presented. A 0.15 μm GaAs pHEMT process is used to implement the power amplifier. The chip size is 2.09 mm × 1.28 mm including the on-chip power detector and I/O pads. The PA die chip is attached on a commercial open cavity QFN package to evaluate the performances in surface mount use. The on-chip power detector is designed with directional coupler using diode rectifier to monitor available output power from the PA. The detector output voltage is very coherent to the output power in the operation frequency from 26.6 GHz to 29.2 GHz, where the deviation of the detector output voltage is lower than ± 3.7 % up to 27.4 dBm output power. The output PSUB1dB/SUB is over than 26.9 dBm, saturated output power is over 27.4 dBm, and the PAESUBmax/SUB is 25~30 % across the operation frequency.

A 26–40 GHz Wideband Power Amplifier With Transformer-Based High-Order Matching Networks in 28-nm CMOS FD-SOI

This letter presents a wideband two-stage full Ka-band power amplifier (PA) with transformer-based matching networks (TMNs) in 28-nm CMOS fully depleted silicon on insulator (FD-SOI) technology. By considering the loss of the transformer, which has usually been ignored in previous works, methods to compensate for the nonflat gain in TMNs are studied and based on that, the initial guess for wideband TMNs design is extracted. Wideband performance in terms of gain and output power is delivered by designing wideband TMNs in the PA design and frequency-independent optimum load selection for the power cell. Measurement results show that the PA achieves 19 dB maximum gain with 13.8 GHz (42%) 3-dB bandwidth (BW), 16.1 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathbf {out-1dB}}$ </tex-math></inline-formula> with 13 GHz 1-dB BW, 17.1 dBm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{\mathbf {sat}}$ </tex-math></inline-formula> with 12 GHz 1-dB BW, and 25.3% peak power-added efficiency.

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

A Yield-Improvement Method for Millimeter-Wave GaN MMIC Power Amplifier Design Based on Load—Pull Analysis

Process fluctuations can significantly affect the yield of millimeter-wave circuits based on submicrometer semiconductor processes. A yield-improvement design that incorporates passive circuits is well established. However, how to consider the process fluctuation in active circuit designs (e.g., power amplifiers) and improve yield is still a challenge. In this article, a yield-improvement load-pull design method, which can be used to find optimum load impedance accounting for high yield while maintaining good output performance, is presented. The yield-improvement load-pull theory is described using an analytical model of transistor large-signal performance considering the process fluctuation. A method of the yield-improvement load-pull for the practical microwave monolithic integrated circuit (MMIC) design is introduced in detail. For demonstration purposes, a high-performance Ka-band power amplifier MMIC is designed. The results show that with the proposed yield-improvement load-pull method, an obvious improvement of yield can be observed with only minimal sacrifice of the output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and the power added efficiency ( η <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PAE</sub> ), respectively. As a result, the method of this article can be used to improve the yield of millimeter-wave/terahertz integrated circuits (ICs).

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave. It adopts a three-stage single-ended structure at 28GHz. An analog predistortion linearization method is used to improve the linearity of the power amplifier (PA). As a result, there is a significant improvement in power-added efficiency (PAE) and linearity is achieved. The Ka-band PA is implemented in TSMC 65nm CMOS process. At 1.2V supply voltage, the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%. After linearization, the output power at the 1dB compression point is increased by 2dBm, with efficient gain compensation performance.

Ka band power amplifier and a low noise amplifier for a transmitter

Ka band power amplifier and a low noise amplifier for a transmitter

Ka대역 50 W급 고출력증폭기(SSPA) 설계 및 제작

Ka대역 50 W급 고출력증폭기(SSPA) 설계 및 제작

Design and Development of InP DHBTs With High Breakdown Voltage for Ka-Band PA Applications

Type-I (straddled) InP DHBT devices have been fabricated to study the impact of different base-collector junction transition layer designs on the collector to emitter breakdown behavior, breakdown voltage, BVceo and the device output performance such as knee voltage, Vknee at high collector current densities, Jc. An abrupt breakdown behavior with BVceo of 11V and Vknee less than 1V at Jc>100kA/cm2 are achieved using an optimized base collector junction transition layer design. Using 2D numerical simulations, components of leakages dominating Iceo at low and high collector to emitter bias voltages are explained. It is further shown that the optimized device exhibits good RF and power performance achieving f $_{T}$ of 115GHz and f $_{max}$ of 150GHz at emitter width >1um. An MMIC power amplifier (PA) is also designed and fabricated using the optimized Type-I InP DHBT device. At 28GHz, good power performance is achieved with PAE of 54% and Psat of 26dBm. Thus, it is shown that InP DHBTs developed in this work are a good candidate for the next phase of 5G millimeter wave Ka-band power amplifier applications.

In-Band Digital Predistortion for Concurrent Dual-Broadband Phased Array Transmitters

This letter proposes a novel in-band digital predistortion technique to linearize the concurrent dual-broadband phased array transmitters, which can remove the in-band distortion with reduced processing bandwidth compared to conventional methods. Based on $1\times 4$ phased array antennas fed by a Ka-band power amplifier, a concurrent dual-band signal with modulated bandwidth of 200 MHz at 27 and 28.2 GHz can be effectively linearized with the processing bandwidth of only 240 MHz. The proposed method presents great effectiveness and a bright prospect for ultrabroadband multiband applications in future communication systems.

A Novel 4-D Artificial-Neural-Network-Based Hybrid Large-Signal Model of GaAs pHEMTs

A novel hybrid large-signal model of GaAs pseudomorphic HEMTs (pHEMTs) is proposed for monolithic microwave integrated circuit design. This new model is based upon accurate electromagnetic (EM) description and creative multi-path artificial neural network (ANN) optimization. To precisely describe the EM effect in the high-frequency range, the extrinsic part of this model includes both lumped and distributed components. In order to re-grid the discrete data, the bias-dependent intrinsic elements are determined by ANNs rather than traditional interpolations. The dispersion effect is represented by nonlinear sources with the multi-path-dependent integration technique, which is described by processed multi-bias S-parameters. This proposed approach can be applicable to different bias conditions, which is also verified by different types of GaAs pHEMTs with good agreement. In addition, a class-AB Ka-band power amplifier and a Ka-band switch using a 0.15- $\mu {\text {m}}$ GaAs pHEMT process were designed based on the novel hybrid model for further practical verification.

The Design of Fast Pulse Power Generator with Low Voltage

In recent years, nanosecond pulse power techniques used in the millimeter-wave solid-state pulse power amplifiers attracted much attention. The rise- and fall-time of the pulse, the flatness of pulse-top and the stability of pulse-to-pulse, which have play important roles in a nanosecond pulse power generator techniques, and directly determine the system performance. In this paper, a method using the outbreak current with low-voltage to drive MOS-FETs is proposed. The measured results show that the rise- and fall-time of the output pulse is less than 1.5 ns with a pure resistance 0.5Ω, and it only needs two 12V power supply to give a output current of 20A with a pulse width of 160 ns at a repetition rate of 540 kHz in continuous mode. A flatness of 3% for the output voltage was obtained,which meet the requirements of ka-band solid-state millimeter-wave pulse power amplifier.

A 27 GHz, 14 dBm CMOS Power Amplifier Using 0.18 $\mu {\rm m}$ Common-Source MOSFETs

A Ka-band three-stage CMOS power amplifier was designed and fabricated using 0.18 mum gate-length common-source transistors. For low loss and accurate matching networks for the amplifier, a substrate-shielded microstrip-line was used with good modeling accuracy up to 40 GHz. The measured insertion loss was 0.5 dB/mm at 25 GHz. The three-stage amplifier achieved a 14.5 dB small-signal gain, 14 dBm output power, and 13.2% power-added-efficiency at 27 GHz in a compact chip area of 0.84 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured gain was the highest for Ka-band power amplifiers using common-source transistors. These results were achieved at a voltage compatible with deep sub-micrometer CMOS technology.

Accurate Small-Signal Model Extraction for pHEMT on GaAs

An accurate small-signal modeling approach applied to GaAs-based pHEMT devices is presented. The procedure for extracting equivalent-circuit model parameters is illustrated in detail. A genetic algorithm (GA) program is developed to optimize the model parameters in order to improve the modeling accuracy. The validity of modeling approach is verified by comparing the simulated and measured result of two pHEMTs and a fabricated ka-band power amplifier. The conclusion can be drawn that the proposed modeling method is rather accurate and efficient.

A Ka-band power amplifier based on a low-profile slotted-waveguide power-combining/dividing circuit

In this paper, a Ka-band power amplifier based on a resonant slotted-waveguide-to-microstrip power-dividing/combining circuit is presented. The advantages of this structure are its low profile, ease of fabrication, as well as its potential for high power-combining efficiency. In addition, efficient heat sinking of monolithic microwave integrated circuit (MMIC) devices is achieved. A slotted-waveguide power amplifier using eight MMIC amplifiers was designed and fabricated. The measured power-combining efficiency at 33 GHz is 72%. In addition, simulation results predicting the performance degradation of the slotted-waveguide power amplifier due to multiple device failure are presented.

A Ka band extended resonance power amplifier

A Ka-band power amplifier based on an extended resonance power combining technique is presented. This technique enables the design of planar microstrip power amplifiers that are much more compact than those based on traditional quarter-wave hybrid designs. The extended resonance power combining amplifier presented here combines four GaAs MESFETs at 32.8 GHz using a planar structure that is more than 40% smaller than a quarter-wave hybrid power combining amplifier design, while the power-combining efficiency is 92%. The measured small-signal gain at 32.8 GHz is 4.6 dB, and at 1-dB compression the output power is 23.3 dBm with a power-added efficiency of 12.8%.

A high-power and high-efficiency monolithic power amplifier at 28 GHz for LMDS applications

A high-power and high-efficiency monolithic power amplifier operating from 27.5 to 29.5 GHz is presented for local multipoint distribution service. Using 0.15-/spl mu/m InGaAs/AlGaAs/GaAs pseudomorphic high electron-mobility transistor devices, the two-stage power amplifier on 4-mil GaAs substrate demonstrated greater than 16-dB small-signal gain, 32-dBm (1.6 W) power with 35% power-added efficiency. The amplifier attained peak output power of 33.9 dBm (2.4 W) and peak power-added efficiency of 37%. At the peak power level, the amplifier exhibited power densities in excess of 640 mW/mm, which is the highest output power density attained by Ka-band monolithic power amplifiers. At lower drain voltage, the amplifier attained 43% power-added efficiency with 30-dBm output power.

New results using membrane-supported circuits: a Ka-band power amplifier and survivability testing

This paper describes recent results which pertain to the integration and reliability testing of micromachined, membrane-supported transmission line circuits. These circuits employ a 1.4-/spl mu/m-thick dielectric membrane to support thin-film conducting lines above an air substrate. With regard to integration, the development of a Ka-band solid state power amplifier (SSPA) is presented. The design includes a membrane-supported Wilkinson power divider/combiner with 0.2 dB loss, along with a commercially available monolithic microwave/millimeter wave integrated circuit (MMIC) amplifier stage. Also reported are tests which investigated the survivability of membrane lines under space qualification conditions. No failures occurred as a result of thermal cycling and vibration testing at levels which reached 39.6 grms.