Junctionless Tunnel Field Effect Transistor Research Articles

Analytical Modeling of Triple-Material Trigate Junctionless Tunnel Field Effect Transistor

An analytical two-dimensional (2D) model is developed to obtain expressions for various parameters of triple-material trigate junctionless tunnel field-effect transistors (TMTG-JTFETs). The 2D Poisson’s equation uses the superposition approximation method to calculate the sum of potentials arising from different point charges. The electric field distribution in the channel is obtained from the gradient of the electric potential. The drain current of the device is calculated using the Kane’s model in the presence of an electric field and a band structure. The TMTG-JTFET, with a channel length of 40nm, exhibits significant electrical characteristics with very low off-current (Ioff) and high on-current compared to a dual-material double-gate TFET. To validate the model, analytical results are confirmed via comparison with technology computer-aided design simulation results.

Design and Analysis of a Multi Material Double Gate Junctionless Tunnel Field Effect Transistor

Design and Analysis of a Multi Material Double Gate Junctionless Tunnel Field Effect Transistor

An In0.53Ga0.47As/In0.52Al0.48As/In0.53Ga0.47As double hetero-junction junctionless TFET

In this paper, an In0.53Ga0.47As/In0.52Al0.48As/In0.53Ga0.47As double hetero-junction junctionless tunnel field-effect transistor (JL-TFET) is proposed, whose N+-channel is formed through the two-dimensional electron gas (2DEG) generated by the hetero-junction without directly implementing physical doping. It can not only effectively suppress the random dopant fluctuation in traditional JL-TFET, but also solve the problem that the electron tunneling is hindered by the wide tunneling barrier at the tunneling junction in conventional dopingless TFET. The existence of 2DEG at the source/channel junction for the proposed JL-TFET can decrease the lateral tunneling distance and enlarge the energy range for tunneling, thereby promoting the device performance. Investigations on effects of the thickness of channel layer (T c), the N-type doping concentration (N+D) in doping layer, and the gate dielectric on JL-TFET demonstrate that the optimal device characteristics can be obtained when T c = 2 nm, N+D = 1 × 1019 cm−3, and the high-K dielectric is adopted.

Ground Plane Electrostatically Doped Junctionless Tunnel Field Effect Transistor: Process Immune Design for Suppressed Ambipolarity

The incorporation of a highly doped Si layer below the Si film, termed as the ground plane, in the electrostatically doped junctionless tunnel field effect transistor (ED-JLTFET) with high-K gate stack. This allows the conceptualization and realization of highly reduced ambipolar behaviour with enhancement in the drive current. The deployed GP sinks the electric field induced at drain side, increases the effective channel length for the short channel devices, prevents the direct source-to-drain tunneling and also the channel-to-drain tunneling in reverse direction at negative gate voltages. A significant reduction of sub-threshold slope and DIBL is also reported for the considered device structure. Using a calibrated exhaustive TCAD study, the detailed sensitivity analysis is also carried for the proposed device with the parametric sweep method. Further, the device analog/RF performance is also comprehensively examined for its high frequency operations. Interestingly, it is also observed that the deployment of this GP also results in better volume depletion. Moreover, due to electrostatically doped structure, the reported device is also expected to have a lower thermal budget, immune towards the random dopant fluctuations (RDFs) effects and tolerant towards the velocity degradation effects as well. Hence, the reported device is a potential candidate for implementing ultra low power steep switching transistors.

Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

Performance enhancement in a novel amalgamation of arsenide/antimonide tunneling interface with charge plasma junctionless-TFET

In this article, a novel combination of an arsenide/antimonide tunneling interface using binary (InAs) and ternary (AlGaSb) compound semiconducting materials and junctionless tunnel field effect transistor (JLFET) has been explored to induce a charge-plasma based tunable bandgap source/channel (S/C) interface. The hetero-material JLTFET (H-JLTFET) depicts superior performance than conventional homo-material Si JLTFET in terms of DC characteristics showing ~128 and ~1.27 × 108 times higher ION and ION/IOFF along with ~10−6 times, ~50%, and 88% lower IOFF, Vth, and SS. The superior performance is attributed to the conduction band local minimum induced at the channel yielding to narrower tunneling barrier width at an optimized Al-mole fraction (0.15) of AlGaSb. Furthermore, 77 times higher gm of H-JLTFET led to 5 × 106 and 205 times higher device efficiency and fT along with ~66% reduction in the parasitic capacitance making it favorable for high-speed switching applications as compared to Si JLTFET.

Digital Performance Assessment of the Dual-Material Gate GaAs/InAs/Ge Junctionless TFET

FIn this article, a device called GaAs/InAs/Ge junctionless tunnel field-effect transistor (JL-TFET) is proposed and investigated by a numerical simulator. This device utilizes an InAs pocket at the source side and its digital performance parameters such as subthreshold slope (SS) and ON-state current to OFF-state current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) ratio have been improved in comparison with GaAs/Ge JL-TFET. Simulation results show that the electron tunneling mechanism is based on intraband tunneling and interband tunneling in GaAs/InAs/Ge JL-TFET, while the electron tunneling mechanism is interband tunneling in regular JL-TFET. To further reduce SS, we have proposed for the first time GaAs/InAs/Ge JL-TFET structure with a fixed gate (f-gate), the so-called dual-material gate (DMG) GaAs/InAs/Ge JL-TFET. The f-gate induces a local dip in the conduction band edge leading to more abrupt band bending at the vicinity of the InAs/GaAs interface. Simulation results show that DMG GaAs/InAs/Ge JL-TFET is turned on at lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> compared to GaAs/InAs/Ge JL-TFET, causing a SS is improved. A brief examination of the proposed device has been done on the impacts of both the variations of the f-gate work-function (φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> ) and the f-gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> ). The DMG GaAs/InAs/Ge JL-TFET with a channel length of 20 nm, φ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</sub> = 3.7 eV, and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f-gate</sub> = 5 nm showed the average SS of SS = 2.1 mV/dec, and ON-state current of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 0.51 mA/μm. The SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of the DMG GaAs/InAs/Ge device are improved by 150% and 76%, respectively, compared to the GaAs/Ge JL-TFET device with similar dimensions. The DMG GaAs/InAs/Ge JL-TFET device proposed in this article can be a reasonable candidate for digital applications.

Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

To overcome the fabrication complexity and achieve a better switching ratio is a major grave concern for applications in semiconductor devices. In this regards, a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) has been investigated in this manuscript. This structure serves as an alternative solution to improve the performance of device. For this, device structure has comprised of two isolated gates such as polarity gate and control gate with the platinum (work-function = 5.93 eV) and hafnium (work-function = 4.3 eV) respectively, over the N+-type doped silicon substrate for the formation of Tunnel Field Effect Transistor as a like doped conventional TFETs (Tunnel Field Effect Transistors) to overcome fabrication complexity. Since ON state current plays important role in switching ratio and subthreshold swing. Therefore, a dual layer oxide (stack) has introduced in junctionless TFETs to get further improvement in ON state current due to the better capacitive coupling between gate and substrate. Under this condition, the performance improvement is still required of dual oxide juntionless TFETs. Hence, a live strip has inserted at the source side in dual oxide layer to improve the ON state current which helps in gain of device and design of analogue and RF circuits. Moreover, we have also examined the impact of low work-function of live strip on dual oxide Junctionless TFETs in terms of DC, analog/RF and linearity figures of merit (FOMs) of the device. All simulation have been carried out using the technology computer aided design (TCAD) tool. This study shows that proposed device is an appropriate for ultra low power high frequency applications.

Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications

This paper investigates the reliability of a dual metal gate-hetero-material junctionless tunnel FET (DMG-HJLTFET), by using a novel combination of III–V compound semiconducting materials, $$\mathrm{InAs}$$ (lower bandgap) in the source region and $$\mathrm{GaAs}$$ (higher bandgap) in the channel and drain regions. We applied bandgap engineering and dual material gate engineering to improve the linearity metrics and distortion parameters by optimizing an appropriate lower work function tunnel gate toward the source and higher work function supplementary gate toward the drain and compared all the results with SMG (single metal gate)-HJLTFET and Si-JLTFET. The DMG-HJLTFET showed marked improvements in terms of ION, ION/IOFF, SS, $${g}_{\mathrm{m}}$$ , $${g}_{\mathrm{m}3}$$ , VIP2, VIP3, and 1-dB compression point. The input power, IIP3 of DMG-HJLTFET, is 158% greater than SMG-HJLTFET and is 154.7% greater than Si-JLTFET. The distortion power, IMD3 of DMG-HJLTFET, is 171.8% and 20.5% lower than SMG-HJLTFET and Si-JLTFET, respectively, thereby making it suitable for low-power distortion-free wireless communication systems.

Linearity performance analysis of junctionless nanotube tunnel field effect transistor

The article provides linearity performance parameter of junctionless nanotube TFET (JL-NT-TFET) for the application of ultra-low standby power and radio frequency ICs (RFICs). The proposed charge plasma device uses an inner gate with a similar workfunction as the outer gate electrode. The inner gate of the device provides better electrostatic controllability, increases turn-on capability. JL-NT-TFET shows the subthreshold swing of 20.5 mV decade, minimum leakage current, and higher current as compared to junctionless nanowire TFET (JL-NW-TFET). Linearity performance analyzed in terms of VIP2, VIP3, IIP3 and 1-dB compression point. Results obtained from JL-NTTFET is further compared to JL-NW-TFET. Simulation results of both the devices indicate that the JL-NT-TFET shows better linearity performance, hence it can be applied to low power high-frequency applications.

RF Analysis of Double-Gate Junctionless Tunnel FET for Wireless Communication Systems: A Non-quasi Static Approach

The optimum and acceptable combination of control gate (CG) process parameters, such as dielectric materials, thickness, and metal work function for a double-gate junctionless tunnel field-effect transistor, remain a subject of great interest among researchers. We report here on the significant impact of CG process variations on the radio-frequency (RF) parameters of this device structure. Studies carried out using a non-quasi-static model with CG process variations have been analyzed for current gain (h21) and unilateral power gain with the help of a Silvaco Atlas device simulator. Systematic investigations reveal that the combination of CG process parameters, such as dielectric material (SiO2) with the thickness of 2 nm and CG metal (aluminum-〈100〉), provide the optimum RF characteristics, i.e., fT (2.9 GHz) and fmax (15 GHz), while maintaining the switching ratio (0.161 × 109), intrinsic capacitances (Cgg = 0.7 fF), and transconductance (3.8 μS) at the bias conditions of Vgs (1 V) and Vds (1 V). The results have been thoroughly interpreted from energy band diagrams and the associated band-to-band tunneling rate. The studies reported here may prove to be useful for further exploring the use of the suggested device structure for Internet of Everything communications and other related applications.

Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises

This paper reports the investigation of conventional junctionless tunnel FET (JL-TFET) and N+ pocket-doped junctionless vertical tunnel FET (JL-VTFET). The investigation is done by analyzing the effect on the ID–VGS characteristics (a) under a wide range of temperature and (b) in the presence of acceptor interface trap charges. This work also examines the performance of noise and its impact on the digital inverter. Comparison has been made on the TCAD simulated results of both the devices. It is observed that the degradation of drain current (ID) is less in JL-VTFET and also it has better noise performance than that of conventional JL-TFET. Its net drain current noise spectral density (Sid) reaches 10–15 A2/Hz till 1 MHz and decreases with further increase in frequency. The contributions of generation–recombination noise and flicker noise are found to be more in low and moderate frequency, whereas diffusion noise dominates at high frequency. Furthermore, the impact of interface traps is studied using complementary JL-VTFET digital inverter application and compared with the one without interface traps. The transient characteristics show an average delay of 15 ps and 27 ps in the absence and presence of interface traps, respectively.

Design and Investigation of Junctionless DGTFET for Biological Molecule Recognition

This work utilizes the dielectric modulated detection technique within a junctionless tunnel field-effect transistor (JLTFET) to detect various charged and neutral biomolecules. The electrostatic properties of the proposed dielectric modulated junctionless double gate JLTFET (DM-JL DGTFET) are observed and analyzed to determine the biomolecules like uricase (k = 1.54), Glucose oxidase (k = 3.46), APTES (k = 3.57), keratin (k = 8) and gelatin (k = 14) lipid, carbohydrate, nucleic acid (DNA and RNA), and protein, etc. The SiO2 (gate oxide) is etched and a cavity is shaped under the gate electrode in which the analytes are injected and thus the effective dielectric of the gate oxide is modulated. The injected charge or neutral analytes of the various biomolecules in the immobilized states are responsible to change the electrostatic characteristics of the DM-JL DGTFET device by varying the gate capacitance. The drain current, ION/IOFF, subthreshold slope, and sensitivity of the DM-JL DGTFET are estimated to recognize the biomolecules. The DM-DGJLTFET shows noticeable sensitivity outcomes 15.2 × 1011 for the charged biomolecules, especially the positively charged analytes.

Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source

In this work, we demonstrate the design of a dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET). Unlike the conventional dual-material gate heterostructure junctionless tunnel field-effect transistor (DMG-HJLTFET), the proposed structure uses a Gaussian-doped source and adopts InAs/GaAs0.1Sb0.9 as a heterojunction at the source and channel interface, where a polarization electric field is induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 Zinc blende crystal. At the same time, the control gate electrode of the proposed structure is divided into two parts, namely tunnel gate (TG) and auxiliary gate (AG). In this structure, TG is located near the source side and has a lower work function, while AG is located near the drain side and has a higher work function, which not only improves ON-state current (Ion) but also decreases the OFF-state current. The performance of the proposed device is analyzed and compared with that of DMG-HJLTFET; simulation results show improvements in Ion, subthreshold swing, transconductance (gm), cut-off frequency (fT) and gain bandwidth (GBW). Compared with conventional DMG-HJLTFET, the maximum Ion and gm of the DMG-GDS-HJLTFET are 4.1 × 10−4 A μm−1 and 1.27 × 10−3 S μm−1 at 1.2 V gate-to-source voltage (Vgs); further, average subthreshold swing of DMG-GDS-HJLTFET is only 13.6 mV Dec−1 at low drain voltages. Also, DMG-GDS-HJLTFET could obtain a maximum fT of 193 GHz at Vgs = 0.8 V and a maximum GBW of 55.7 GHz at Vgs = 1.12 V, respectively.

Low-Power Efficient p+ Si0.7Ge0.3 Pocket Junctionless SGTFET with Varying Operating Conditions

A new low-power Si1−xGex pocket junctionless single-gate tunnel field-effect transistor (JLSGTFET) is designed to achieve steep subthreshold performance and a better ION/IOFF ratio (∼ 108) in sub-20-nanometer technology node. The mole fraction of Ge represented by x is kept at 0.3 for the SiGe pocket region. The proposed JLSGTFET shows better performance with a Ge mole fraction value x = 0.3. The mole fraction value affects various electrical parameters in terms of leakage current, junction capacitance and transconductance of the channel region. The device exhibits reduced switching capacitance due to the smaller-bandgap pocket region between the source and channel. Analysis of the JLSGTFET is carried out for DC and AC parameters at room temperature. Temperature analysis plays a vital role in determining reliable ON- and OFF-state performance in transistors. Therefore, the proposed pocket JLSGTFET is investigated under harsh temperature conditions to characterize the performance for DC and subthreshold parameters. The sensitivity of the device is analyzed under different temperature conditions over a range of 250–400 K to observe subthreshold performance including transfer characteristics, output characteristics, ION/IOFF ratio, subthreshold slope (SS) and drain-induced barrier lowering (DIBL). The JLSGTFET demonstrates a small variation in DC and subthreshold parameters, indicating good prospects for future analog and digital applications. All the analysis of the proposed JLSGTFET is carried out on a 2D/3D VisualTCAD device simulator.

Silicon-On-Nothing Electrostatically Doped Junctionless Tunnel Field Effect Transistor (SON-ED-JLTFET): A Short Channel Effect Resilient Design

This work investigates the novel device structure, silicon-on-nothing electrostatically doped junctionless tunnel field effect transistor (SON-ED-JLTFET) with high-K stacked hetero-gate technology for its short channel effects (SCEs) immune properties. Here, its analog/RF device performance metrices are also analyzed using calibrated 2-D technology computer-aided design (TCAD) simulation study. This device is expected to exhibit the fundamental advantages of SON technology, i.e. it should be more immune towards SCEs, like threshold voltage roll-off, drain induced barrier lowering (DIBL) even for devices with less than 10 nm channel length. Moreover, owing to its electrostatic doping instead of metallurgical doping, the detrimental doping control issues, such as mobility degradation, higher fabrication thermal budget and statistical random dopant fluctuations (RDFs) can no more degrade the device performance. This helps in realization of more process variations immune design. Here the detailed device sensitivity analysis with respect to the various crucial devices dimensional parameters variation is also carried out.

Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate

In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, respectively, where ΦM1 = ΦM3 &lt; ΦM2. Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to 9.04 × 1 0 − 6 A/μm, and the maximum gm (which determine the analog performance of devices) of DMMG-HJLTFET is 1.11 × 1 0 − 5 S/μm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (fT) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum fT of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation

An improved subthreshold analytical model of Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) with stacked / hetero-dielectric gate oxide structure is proposed. The stacked gate oxide structure comprises of Silicon-dioxide (SiO2) and Titanium Oxide (TiO2). The high-K gate stack engineered device overcomes the Short Channel Effects (SCEs) caused by the ultrathin silicon devices. The subthreshold analysis is carried out by solving a two-dimensional Poisson’s equation using Parabolic approximation method. These characteristics are analyzed against various device parameters. Also, the impact of different high-K gate oxide materials with SiO2 is also studied. A comparative analysis of short channel effects for DMDG TFET and DMDG JLTFET has been carried out. The results reveal that the proposed device provides better ION current, low leakage current and improved Transconductance-to-drain current ratio. Using TCAD Sentaurus device simulator, the subthreshold analytical model results have been simulated and verified with other TFET models.

Design of Low Power Si0.7Ge0.3 Pocket Junction-Less Tunnel FET Using Below 5 nm Technology

This work proposed the design of low power Si0.7Ge0.3 pocket Junction-less TFET (JLTFET) on bulk silicon using below 5 nm technology. The inclusion of junction-less regions improves ON-state current with lesser effect on OFF-state current. The p-type pocket regions added to improve device performance in subthreshold region showing reduction in OFF-state leakage current leading to good value of ON/OFF current ratio as compared to other similar TFET structures. A high-value ION/IOFF ratio and good subthreshold behavior are observed for pocket JLTFET with 2 nm gate length and body thickness 0.5 nm. The proposed JLTFET is further optimized for different gate contact and oxide materials. The temperature analysis plays major role in deciding a reliable ON-state and OFF-state performance of transistors. So, the proposed pocket JLTFETis investigated for harsh temperature conditions to characterize the performance for DC and AC parameters. The sensitivity of proposed JLTFET is analyzed under different temperature conditions in range of (200–400) K to observe subthreshold performance such as transfer characteristics, Output characteristics and ION/IOFF ratio. The proposed designs for JLTFETs have been simulated using TCAD 2D/3D device simulator.