Junction Field Effect Research Articles

A method for fault diagnosis of nonlinear circuits

PurposeThe purpose of this paper is to develop a method for multiple soft fault diagnosis of nonlinear circuits including fault detection, identification of faulty elements and estimation of their values in real circumstances.Design/methodology/approachThe method for fault diagnosis proposed here uses a measurement test leading to a system of nonlinear equations expressing the measured quantities in terms of the circuit parameters. Nonlinear functions, which appear in these equations are not given in explicit analytical form. The equations are solved using a homotopy concept. A key problem of the solvability of the equations is considered locally while tracing the solution path. Actual faults are selected on the basis of the observation that the probability of faults in fewer number of elements is greater than in a larger number of elements.FindingsThe results indicate that the method is an effective tool for testing nonlinear circuits including bipolar junction transistors and junction field effect transistors.Originality/valueThe homotopy method is generalized and associated with a restart procedure and a numerical algorithm for solving differential equations. Testable sets of elements are found using the singular value decomposition. The procedure for selecting faulty elements, based on the minimal fault number rule, is developed. The method comprises both theoretical and practical aspects of fault diagnosis.

Tunneling field-effect junctions with WS2 barrier

Transition metal dichalcogenides (TMDCs), with their two-dimensional structures and sizable bandgaps, are good candidates for barrier materials in tunneling field-effect junctions (TFEJ) formed from atomic precision vertical stacks of graphene and insulating crystals of a few atomic layers in thickness. We report first-principles study of the electronic properties of the Graphene/WS2/Graphene sandwich structure revealing strong interface effects on dielectric properties and predicting a high ON/OFF ratio with an appropriate WS2 thickness and a suitable range of the gate voltage. Both the band spin-orbit coupling splitting and the dielectric constant of the WS2 layer depend on its thickness when in contact with the graphene electrodes, indicating strong influence from graphene across the interfaces. The dielectric constant is significantly reduced from the bulk WS2 value. The effective barrier height varies with WS2 thickness and can be tuned by a gate voltage. These results are critical for future nanoelectronic device applications.

Performance prediction of four-contact vertical Hall-devices using a conformal mapping technique**Project supported by the Natural Science Foundation of Jiangsu Province, China (Nos. BK20131379, BK20141431) and the Graduate Research and Innovation Projects of Jiangsu Province (No. SJLX_0373).

Instead of the conventional design with five contacts in the sensor active area, innovative vertical Hall devices (VHDs) with four contacts and six contacts are asymmetrical in structural design but symmetrical in the current flow that can be well fit for the spinning current technique for offset elimination. In this article, a conformal mapping calculation method is used to predict the performance of asymmetrical VHD embedded in a deep n-well with four contacts. Furthermore, to make the calculation more accurate, the junction field effect is also involved into the conformal mapping method. The error between calculated and simulated results is less than 5% for the current-related sensitivity, and approximately 13% for the voltage-related sensitivity. This proves that such calculations can be used to predict the optimal structure of the vertical Hall-devices.

A Compact Behavioral Simulation Model for CMOS Vertical Hall-Effect Devices

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model’s simulation results are in good agreement with the reported experimental results.

A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature.

A computationally efficient numerical model of the offset of CMOS-integrated vertical Hall devices

This paper describes a computationally efficient numerical model to study effects determining the offset of five-contact vertical Hall sensors (VHS). It applies a two-dimensional finite element model implemented in COMSOL Multiphysics and allows to take into account the junction field effect (JFE) altering the depletion layer width between n-well and p-doped regions as well as resistive asymmetries due to contact shifts. Doping profiles of realistic devices were extracted using SYNOPSYS TCAD simulations based on three sets of process parameters with different doping doses of the n-well and p+-diffusions. The VHS offset was compared with experimental results obtained using complementary metal oxide semiconductor (CMOS)-based VHS and analyzed as a function of the input voltage. It was shown that the linear offset components are modeled adequately by resistive imbalances caused by lateral contact shifts in the nanometer range. The JFE in turn is responsible for the nonlinear effects of dominantly quadratic dependence on the input voltage. Both effects contribute additively to the overall offset. According to the simulations, the nonlinear contribution is strongly reduced at higher n-well doping concentrations.

Analysis of the offset of semiconductor vertical Hall devices

This study investigates the origin of the offset voltage of five-contact vertical Hall sensors (5C-VHS) by modeling these devices as a simple lumped resistor circuit. The model with the shape of a four-contact Wheatstone bridge was enhanced by asymmetries caused by the mismatch of the lumped resistors. Further, the junction field effect was taken into account by modulating the resistances of the lumped elements with the average of the voltages applied at their contacts. The linear and quadratic components of the offset versus drive voltage characteristics in four operation modes were successfully traced back to the modeled asymmetries and nonlinearities. The measured offset characteristics of 5C-VHS is satisfactorily described and methods for reducing this undesired signal component are inferred.

Piezoresistive Response of Vertical Hall Devices

This paper reports on the piezoresistive response of CMOS-based five-contact vertical Hall sensors (VHS) under mechanical stress. Single sensor elements and coupled sensor systems comprising four individual VHS were exposed to normal in-plane stress σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xx</sub> along the sensor axis using a four-point bending bridge setup. The resulting stress sensitivity of the offset signals at an input voltage of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> = 3 V was below 2 μV/MPa. In addition, an inhomogeneous stress distribution was generated by applying vertical forces close to the sensor systems using an SU-8 pillar. A resulting maximum offset increase by 109 μV/N at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> = 3 V was measured. In conclusion, the influence of mechanical stress on the offset behavior of VHS is small compared to other offset sources such as the junction field effect and variations in sensor geometry.

Self-trapping of electrons at the field-effect junction of a molecular crystal

We consider the interface of a molecular crystal with a polar dielectrics. Coulomb interaction of free electrons in the molecular crystal with surface polar phonons of the dielectrics can lead to self-trapping of carriers. For typical parameters of molecular field-effect transistors the binding energy is found to be high enough to allow for the formation of a strongly coupled polaron. The effect is further enhanced in the presence of a bias electric field.

Polarons at the field-effect junctions

We consider the interface of a molecular crystal with a polar dielectrics. Coulomb interaction of free electrons in the crystal with surface polar phonons of the dielectrics can lead to self-trapping of carriers. For typical parameters of field effect transistors the binding energy is found to be high enough t o allow for formation of a strongly coupled polaron. The effect is further enhanced at presence of the bias electric filed.

Atomic interface structure-property investigations

Our current understanding of the relationship between interfacial structure and the resulting properties remains very rudimentary.This is a concern for many fields and applications, includingmetal/semiconductor contacts, insulator/semiconductor field effect junctions, magnetic multilayers, ferroelectric thin films, and semiconductor heterostructures. The situation is slightly improved in the case of epitaxial growth where a deposited layer follows the structure of the underlying substrate. However, even with these systems the interfacial properties are difficult to predict accurately, even when impurities and defects can be ignored. This paper highlights a number of recent examples of interface structure-property investigations that have attempted to understand how the interface formation determines the relevant film or interface property.PACS Nos.: 68.55.Jk, 68.55.Ln, 68.65.+g

Atomic interface structure-property investigations

Our current understanding of the relationship between interfacialstructure and the resulting properties remains very rudimentary.This is a concern for many fields and applications, includingmetal/semiconductor contacts, insulator/semiconductor field effectjunctions, magnetic multilayers, ferroelectric thin films, andsemiconductor heterostructures. The situation is slightly improvedin the case of epitaxial growth where a deposited layer followsthe structure of the underlying substrate. However, even withthese systems the interfacial properties are difficult to predictaccurately, even when impurities and defects can be ignored. Thispaper highlights a number of recent examples of interfacestructure-property investigations that have attempted tounderstand how the interface formation determines the relevantfilm or interface property. PACS Nos.: 68.55.Jk, 68.55.Ln, 68.65.+g

Hot carrier Hall devices in CMOS technology

The sensitivity of Hall devices for a given bias current is often limited by short circuiting effects due to the finite length of the structure. The reduction of the sensitivity is especially important in small devices where contacts occupy a large part of the active zone. In the present work, we present a novel method to enhance the current-related sensitivity. This is done by increasing the current till saturation which leads to the enhancement of the input impedance and thus to the limitation of short circuit. In sufficiently small devices the carrier velocity saturation is the main cause of the resistance increase. Other contributions to the sensitivity increase such as junction field effect and heating have been taken into account. With the help of computer simulations, we have separated the different contributions. The velocity saturation effect leads up to 40% increase in sensitivity near the breakdown voltage as compared to the low electric field Hall voltage. Although the sensitivity increases the overall performance has degraded when operating in the hot carrier regime.

High impedance unit gain amplifiers using field effect junction transistors†

This communication discusses the use of F.E.T. input stages in high impedance unit gain amplifiers. The circuits rely mainly on the use of matched transistors to achieve temperature and d.c. off-set compensation.

Mosfet FM Tuner Design

Dual-gate MOSFETs in an FM tuner provide many advantages over bipolar, junction field-effect, and single-gate MOS field-effect transistors. RF amplification and mixing are aided by use of a low-feedback-capacitance transistor with low noise figure and large dynamic range. A second gate is available for either AGC or local oscillator injection. High stable RF and conversion gains are easily obtained with inexpensive, commercially available coils and without need for neutralization. This paper presents test data and design tips which can be used to design with the SFB8970* dual-gate MOSFET at 100 MHz. The SFB8970 is an N-channel, depletion mode, dual-gate, MOS transistor with integral back-to-back zener diodes between both gates and the source to eliminate the need for special precautionary handling procedures.