ISE Design Suite Research Articles

Implementation of the communication protocols SPI and I2C using a FPGA by the HDL-Verilog language

Currently, the most used serial communication protocols to exchange information between different electronic embedded devices are the SPI and I2C. This paper describes the development and implementation of these proto- cols using a FPGA card. For the implementation of each protocol, it was taken into account different modes of operation, such as master/slave mode sending or pending data mode. For the implementation of the I2C protocol was neces- sary to perform a tri-state buffer, which makes a bidirectional data line for a successful communication between devices, allowing to take advantage of these sources provided by the FPGA. Verilog is a hardware description lan- guage better known as HDL and it was used in the work to implement and sim- ulate these communication protocols with the software version 14.7 of Xilinx ISE Design Suite.

Implementation of Adaptive Digital Beamforming using Cordic

Sonar imaging is one of the simplest technique for detection of under water drowned bodies. There is a need for design of conventional beamforming which are robust and simple. Adaptive beamformer is used to improve the quality of the sonar image. As a result we get an image containing more useful and correct information. The CORDIC computing technique a highly efficient method to compute elementary functions like sine, cosine, translate, rotate values using CORDIC algorithm. The system simulation was carried out using ModelSim and Xilinx ISE Design Suite 9.2i.. Matlab code is used to implement sin and cos using cordic angles and amplitude response of beamformed data by optimized method in order to enlarge the validity region of beamforming. Synthesis results of cordic shows the reduced memory requirement and less power consumption.

High Performance Architecture for LILI-II Stream Cipher

Proposed work presents high performance architecture for LILI-II stream cipher. This cipher uses 128 bit key and 128 bit IV for initialization of two LFSR. Proposed architecture uses single clock for both LFSRs, so this architecture will be useful in high speed communication applications. Presented architecture uses four bit shifting of LFSRD in single clock cycle without losing any data items from function FC. Proposed architecture is coded by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and targeted hardware is Xilinx Virtex5 FPGA having device xc4vlx60, with package ff1148. Proposed architecture achieved throughput of 224.7 Mbps at 224.7 MHz frequency. General Terms Hardware implementation of stream ciphers

High Performance VLSI Architecture for Three-Step Search Algorithm

Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity. The proposed architecture minimizes the area while maintaining the speed requirements for real-time video processing. Implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 14.1, the critical path in the hardware is 6.536 ns and the equivalent area is calculated to be 2.3 K gate equivalent.

Fault-Tolerant Routing Algorithm Simulation and Hardware Verification of NoC

Various software and hardware faults can destroy data transmission on the network, so it is essential to study fault-tolerant methods of Network-on-Chip (NoC). In this paper, a modified fault-tolerant routing algorithm is proposed based on the XY algorithm, which can achieve an efficient route way by resetting the route rule when error occurred on the path of chain or between the nodes. This performance shows that the fault tolerant bypassed the fault path of chain or the error nodes. A hardware design of the modified fault-tolerant routing algorithm is also introduced, aimed at the elaborating of hardware structure principle and simulating of fault tolerant routing algorithm of NoC based on FPGA. The proposed algorithm was simulated and verified on the platform of ISE Design Suite 13.3. The simulation results showed that the proposed modified algorithm is feasible. Because of the algorithm, the overall performance has improved obviously without using virtual channel, especially for the area and power consumption. At last, the proposed algorithm was verified on the FPGA platform of Nexys2 multiple sets of validate data proved that the proposed modified algorithm was reliable and feasible, and the quality of this NoC performed very well.

Efficient Low-Power Compact Hardware Units for Real-Time Image Processing

This paper presents efficient low-power compact hardware designs for common image processing functions including the median filter, smoothing filter, motion blurring, emboss filter, sharpening, Sobel, Roberts, and Canny edge detection. The designs were described in Verilog HDL. Xilinx ISE design suite was used for code simulation, synthesis, implementation, and chip programming. The designs were all evaluated in terms of speed, area (number of LUTs and registers), and power consumption. Post placement and routing (Post-PAR) results show that they need very small area and consume very little power while achieving good frame per second rate even for HDTV high resolution frames. This makes them suitable for real-time applications with stringent area and power budgets.

Enhancing Performance of Iris Recognition Algorithm through Time Reduction

Nowadays, for providing the secure facilities and services to the user, the accurate identification is necessary. The Iris recognition is one of the attractive approach for user’s identification, provides high level of security and convenience then the other methods of identification like traditional ID and password, which can be lost or transferred. However, the iris recognition algorithms are implemented on general purpose sequential processing systems, such as generic central processing units (CPUs). Parallel processing is an alternative offers an opportunity to enhance the performance of system by increasing the speed. The most time consuming part of Iris recognition algorithm is matching part, which is implemented using Verilog HDL through ISE Design suit (14.2), achieved significantly reduction in execution time. The proposed design is suitable for integration either in ASIC or FPGA.

Design and Implementation of Multi-Standard Video Encoder Supporting Different Coding Standards

In this paper we develop the VLSI architecture of Multi-standard video encoder which supports different video coding standards such as MPEG 2/4, VC-1, H.264/AVC and AVS. A multi-standard transform unit with reduced path delay generates transform coefficients for different video coding standards through static reconfiguration. It is suitable for the real-time processing of videos with less motion such as video calls. This architecture is synthesised in Xilinx ISE Design Suite and implemented in FPGA Virtex 5 board.

English

Digital image processing(DIP) is the use of computer algorithms to perform image processing on digital images. The basic operation performed by a simple digital camera is, to convert the light energy to electrical energy, then the energy is converted to digital format and a compression algorithm is used to reduce memory requirement for storing the image. This compression algorithm is frequently called for capturing and storing the images. This leads us to develop an efficient compression algorithm which will give the same result as that of the existing algorithms with low power consumption. Image compression is useful as it helps in reduction of the usage of expensive resources, such as memory, or the transmission bandwidth required. But on the downside, compression techniques result in distortion and also additional computational resources are required for compression- decompression of the medical image data. In this, we proposed DHT based image compression technique. The computational complexity is further reduced by using pipelined CORDIC architecture for computation of sin and cos terms in DHT. The CORDIC based DHT is partially simulated and synthesized by using Xilinx ISE design suite and the same was implemented on targeted FPGA. The hardware requirements and gate delay values are observed and noted down.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Multiplier less high-speed squaring circuit for binary numbers

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth’s algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Design, Modeling and Implementation of 8-bit Processor for Intelligent Automatic Chocolate Vending Machine (AVM)

ABSTRACT This paper describes the design, modeling and simulation of an 8-bit dedicated processor for a Chocolate Automatic Vending Machine (AVM). The proposed dedicated processor is modelled by writing appropriate programs in. The system supports 8 different 8-bit instructions. System simulation was carried out using Xilinx ISE Design Suite 14.6. After accepting the user input which is in the form of desired amount (Re.1, 5, 10 or 20) and second input i.e. choice of the chocolate, the system formulates the chocolate using pre-programmed appropriate proportions and vends it automatically to the user. The system would formulate the recipes with embedded logic. Each recipes involves mixture of various other ingredients which finally results in the desired type of chocolate formation. The Chocolate AVM unlike most other vending machines, prepares chocolate instantly. When the entire process is complete, the vending machine should produce the chocolate and return if any change left.

Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm

A Parallel and pipelined Fast Fourier transform(FFT) processor for use in the orthogonal frequency division multiplexer .it is important to develop a high performance FFT processor to meet the requirements of the real time and low cost in many different systems. Un like being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. here we simulated and synthesized the 256 bit 64 point FFT with radix 4 using VHDL coding and simulation and synthesis done by Modelsim ISE and Xilinx ISE design suite respectively.

Designing of BIST Architecture of Generic Multipliers

The aim of this paper is to present the BIST architecture of generic multipliers. The generic architecture of all the four multipliers i.e. array, column bypass, wallace tree and booth multiplier has been designed .The verification of all these four different multipliers has been done by using BIST controller.The LFSR (linear feedback shift register) has been designed, which will generate the automatic inputs.Then the BIST controller has been designed which will check these multipliers by using input patterns obtained from LFSR. BIST controller will verify these four generic architectures whether they are faulty or not By using it, the logics or design of these multipliers need not to be verified by any other means.This is the advantage of this design that it does not require third party verification.The simulation has been carried out on ModelSim (Student Editon) EDA tool 10.0c and synthesis has been carried out on ISE Design Suite 14.4.

Designing and Simulation of 32 Point Fft Using Radix-2 Algorithm for Fpga

The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the applications of the fast Fourier transform include Signal analysis, Sound filtering, Data compression, Partial differential equations, Multiplication of large integers, Image filtering etc. Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). This paper concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation-In- Time (DIT) domain, Radix-2 algorithm, this paper uses VERILOG as a design entity. The input of Fast Fourier transform has been given by a keyboard using a test bench and output has been displayed using the waveforms on the Xilinx Design Suite 13.1 and synthesis results in Xilinx show that the computation for calculating the 32- point Fast Fourier transform is efficient in terms of speed. I. Introduction This proposes the design of 32-points FFT processing block. The work of the project is focused on the design and implementation of FFT for a FPGA kit. This design computes 32-points FFT and all the numbers follow fixed point format of the type Q8.23, signed type input format is used.The direct mathematical derivation method is used for this design. In this project the coding is done in VHDL (8) & the FPG synthesis and logic simulation is done using Xilinx ISE Design Suite 13.1. The Discrete Fourier Transform (DFT) plays an important role in the analyses, design and implementation of the discrete-time signal- processing algorithms and systems it is used to convert the samples in time domain to frequency domain. The Fast Fourier Transform (FFT) is simply a fast (computationally efficient) way to calculate the Discrete Fourier Transform (DFT). The wide usage of DFTs in Digital Signal Processing applications is the motivation to Implement FFTs. Almost every branch of engineering and science uses Fourier methods. The words frequency, period, phase, and spectrum are important parts of an engineer's vocabulary.The Discrete Fourier transform is used to produce frequency analysis of discrete non periodic signals. The FFT is another method of achieving the same result, but with less overhead involved in the calculations. Fig1:

High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

One of the most popular standards for protecting confidential information is the Data Encryption Standard (DES). Although it has been replaced by the Advanced Encryption Standard (AES), it is still widely used in Automatic Teller Machines (ATM’s), smartcards, and mobile phone SIM cards. In this paper, we present area-efficient and high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design suite. In fact, we propose modifications on the fastest DES design reported in the literature and achieve 1.1 times higher speed. Also, we introduce an 8-stage pipelined design that needs only 0.75 times the registers and consumes 0.65 times the power of a similar 16-stages pipelined design. High-speed design and synthesis optimization techniques including pipelining, register retiming, and logic replication are used. Post- layout synthesis results show that the proposed implementations achieve high throughput-to-area ratio. To make a fair comparison, the proposed designs were synthesized using matching FPGA devices as being used by other implementations reported in the literature.

Design and Performance Analysis of 32 and 64 Point FFT using Multiple Radix Algorithms

Always technical designers choice includes algorithms, flowcharts, programming etc., and end users requires the given input and application output. Based upon this view, this paper focus on the advancement of the Fast Fourier Transform (FFT), by doing design and observing the performance analysis of the 32 FFT[1] and 64 point FFT, using Radix-2, Radix-8[17] and Split Radix algorithm. The algorithm is developed by Decimation-In-Time (DIT) of the Fast Fourier Transform (FFT), using VHDL as a design entity and synthesis are performed in Xilinx ISE Design Suite 13.2 version. Using synthesis results performance analysis is done between 32 and 64 point Fast Fourier Transform (FFT)[16] in terms of speed and computational complexity. General Terms Decimation -In-Time (DIT), Fast Fourier Transform (FFT), VHDL

Diseño en VHDL de un controlador HDLC

This research presents the design of an embedded hardware module with functionality of a HDLC controller to an E1digital line interface. The designed system performs the tasks of a transmitter-receiver, responsible for actions such as insertion and detection of start and end flags of frame, the insertion and detection of zeros to avoid the existence of the sequence of flags in the data field and the frame check. It also incorporates an interface with a microprocessor for setting the initial parameters and through it control data’s are acquired to be transmitted or received. Each of the blocks in the system has been designed through the hardware description language VHDL using Xilinx software ISE Design Suite 12.4. Finally, research is carried through in the development board Spartan3 Starter Board Kit and the results are validated with the appropriate verifications.

A Control Path Design of Communications Processor

With the widespread popularity of wireless mobile devices, the demands of emerging applications have been proposed, such as video telephony and HD video play. The next generation of wireless mobile computing devices needs to have higher data transfer rate, more complex algorithms, as well as low power consumption. This paper gives out a variable-width SIMD processor architectures controller and data transfer module designing method. The controller designing focused on controlling the program flow and initializing the data transfer module. By simulating the architecture on Xilinx ISE Design Suite, the fundamental modules have been designed and tested. The results of simulation verify the correctness of the controller and data transfer module design.

Designing of 8-bit Synchronous FIFO Memory using Register File

FIFO is implies first in first out using queue methodology for memories read and write of any information and data using some control logic. The whole work of FIFO is fully dependent on the control circuitry and clock domain. It is often used to control the flow of data from source to destination by the transition of every clock. Basically FIFO differentiate by clock domain either Synchronous or Asynchronous. There are various methods to designing and synthesized FIFO but here fully focused on the memory which is used to store the data in domain of clock either sync. and async. or single and multiple clock cycles. This paper will differentiate the design, synthesize and analyze a Synchronous FIFO using Register file memory by older version of Synchronous FIFO. In this paper, conclude the effect of using register file instead of random access memory for storage of data in FIFO memory. This work shows change the parameters like on-chip components (clock, signal, input and outputs etc), clock domain, type of resources, and how to minimize and optimize hierarchy of the device. The RTL description for the FIFO is written using Verilog HDL (hardware description language). And design is simulated and synthesizes in Xilinx ISE Design suit 12. 4. The RTL code simulated in ISim Simulator.