ISE Design Suite Research Articles

GMC-crypto: Low latency implementation of ECC point multiplication for generic Montgomery curves over GF(p)

Elliptic Curve Cryptography (ECC) is the front-runner among available public key cryptography (PKC) schemes due to its potential to offer higher security per key bit. All ECC-based cryptosystems heavily rely on point multiplication operation where its efficient realization has attained notable focus in the research community. Low latency implementation of the point multiplication operation is frequently required in high-speed applications such as online authentication and web server certification. This paper presents a low latency ECC point multiplication architecture for Montgomery curves over generic prime filed GF(p). The proposed architecture is able to operate for a general prime modulus without any constraints on its structure. It is based on a new novel pipelined modular multiplier developed using the Montgomery multiplication and the Karatsuba-Offman technique with a four-part splitting methodology. The Montgomery ladder approach is adopted on a system level, where a high-speed scheduling strategy to efficiently execute GF(p) operations is also presented. Due to these circuit and system-level optimizations, the proposed design delivers low-latency results without a significant increase in resource consumption. The proposed architecture is described in Verilog-HDL for 256-bit key lengths and implemented on Virtex-7 and Virtex-6 FPGA platforms using Xilinx ISE Design Suite. On the Virtex-7 FPGA platform, it performs a 256-bit point multiplication operation in just 110.9 us with a throughput of almost 9017 operations per second. The implementation results demonstrate that despite its generic nature, it produces low latency as compared to the state-of-the-art. Therefore, it has prominent prospects to be used in high-speed authentication and certification applications.

ASIC Design and Implementation of Automated Coffee and Tea Brewing System with FPGA Validation

Abstract: This paper presents a pioneering approach to enhance the efficiency of automated coffee and tea brewing systems through the integration of an ASIC-GDSII and FPGA validation. Leveraging the power of 45nm CMOS Technology, the design achieves substantial reductions in area, power consumption, and delay. The Verilog HDL code undergoes meticulous verification using Cadence tools like Genus and Innovus, ensuring optimal design performance. Innovus validates timing constraints, ensuring adherence to acceptable delay parameters. The resulting compact design not only minimizes power consumption but also effectively addresses leakage issues. These comprehensive optimizations meet stringent performance, area, and power requirements, elevating the operational efficiency of automated brewing systems. Furthermore, the control algorithm is synthesized and implemented using Xilinx's ISE Design Suite, followed by validation on SPARTAN 6 FPGA, providing invaluable insights for future synthesis and implementation endeavors.

Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado

SRAM-based FPGA(Field Programmable Logic Arrays) requires external memory since its internal memory gets erased when power is cut off. The process of transmitting the circuit netlist in bitstream from external memory during power-up in FPGA is vulnerable to malicious attacks such as bitstream theft and tampering. Previous FPGA reverse-engineering methods focus on FPGAs, supported by ISE (ISE Design Suite). This is because ISE provides XDLRC (Xilinx Design Language Routing Configurable logic) and XDL (Xilinx Design language) files, which are essential for reverse engineering. However, Vivado Design Suite (Vivado) does not offer those files, making it impossible to extend the coverage of reverse engineering to the FPGAs supported by Vivado. In this paper, we propose a method to generate XDLRC and XDL through Vivado. According to experimental results, the XDLRC and XDL generated through Vivado, respectively, match 99% and 75% with those generated in ISE for Artix-7 100T. As a result, this paper has expanded the scope of reverse engineering from being mainly focused on ISE to now also include Vivado. It is important to note that this paper does not encourage bitstream attacks through reverse engineering but rather highlights the risk associated with malicious attacks and emphasizes the importance of security.

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

<span>A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. <br /> The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. <br /> The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.</span>

High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. 
 The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms.
 In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Implementation of Ripple Carry Adder Design for Optimal VLSI Performance

In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital signal processing use these carry adders. The carry output of every finished adder stage is useful as a carry input to the one behind it. This procedure is continued until the last complete adder stage is reached. Each carry output bit in an entire adder is therefore rippled to the next stage. An exact (forward) carry adder be linked with the proposed structure to generate hybrid adders with tunable accuracy levels. The practical implementation of proposed model is carried out using Xilinx ISE Design Suite 13.4, showcasing its feasibility for real-world applications.

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

AbstractElliptic curve point multiplication is the main primitive required in almost all security schemes using elliptic curve cryptography (ECC). It is the leading computationally intensive operation that sets the overall performance of the associated cryptosystem. This work presents a highly novel area–time efficient elliptic curve point multiplier over a general prime field . It is based on an efficient radix‐23 parallel multiplier, which performs a ‐bit multiplication in clock cycles. On the system level, the twisted Edwards curves with unified point addition using projective coordinates are adopted, where an efficient scheduling technique is presented to schedule several operations on deployed modular arithmetic units. Due to the introduced optimization at different stages of the design, latency, hardware resource requirement, and total clock cycle count are reduced significantly. Synthesis, and implementation of the proposed design over different Xilinx FPGA platforms are completed using the Xilinx ISE Design Suite tool for key sizes of 192, 224, and 256 bits. The 256‐bit Xilinx Virtex‐7 FPGA implementation reveals that it completes a single point multiplication operation in 0.8 ms and occupies 6.7K FPGA slices in a clock cycle count of 132.2K. It produces significantly better area–time product and throughput per slice than the contemporary designs. The proposed design also has the potential to counter simple power analysis and timing attacks. Thus, it is an elegant solution to develop ECC‐based cryptosystems for applications, where both speed and hardware resource consumption are important.

Design and Implementation of Intelligent Car Washing System with Water Saving Technique

This paper discusses an FPGA-based intelligent car washing system. The system provides washing services that are rapid, convenient, and effective. A flow chart for controlling an automated car washing system with four working modes is given in this paper. The car washing system was built with the help of Xilinx Vivado in the software ISE Design Suite using the hardware description language Verilog HDL. In this project, a special feature for water conservation by biologically recycling the water is implemented.

Enhanced AES-256 cipher round algorithm for IoT applications

Objectives: Networks have become a significant mode of communication in recent years. As a result, internet security has become a critical requirement for secure information exchange. Cryptography is used to securely send passwords over large networks. Cryptographic algorithms are sequences of processes used to encipher and decipher messages in a cryptographic system. One of those is the Advanced Encryption Standard (AES), which is a standard for data encryption in hardware and software to hide sensitive and vital information. The main objective is to design an AES system with modifications by the addition of primitive operations which can withstand several attacks and is more efficient.Method: AES works with three different key lengths: 128-bit keys, 192- bit keys, and 256-bit keys. The early rounds of AES have a poor diffusion rate. Better diffusion properties can be brought about by putting in additional operations in the cipher round and key generation algorithm of the conventional AES.Findings: The diffusion characteristics of the conventional AES and the proposed methodology are compared using the avalanche effect. The proposed AES algorithm shows an increased avalanche effect, which proves it to be more secure than the conventional AES. The proposed algorithm is executed on Vivado 2016.2 ISE Design Suite and the results are targeted on Zybo–Zynq Z-7010 AP SoC development board.Novelty: In addition, this paper also proposes an improved AES algorithm that was accomplished by altering the sub-bytes operation. This change was made to make it more reliant on round keys. This algorithm was also extended to a higher key length of 256 bits which makes the algorithm less vulnerable to attacks.

Power, Performance and Area Analysis of Sponge Based Lightweight HASH Function

The Internet of Things refers to uniquely distinguishable devices communicating with each other. Communication is largely on resource-constraint devices which would generate large volumes of data, the security, authenticity, and integrity of devices being essential. SPONGENT-88 variant of the SPONGENT family is a lightweight Hash algorithm suitable for authenticating resource-constrained devices in an IoT environment or WSN (Wireless Sensor Network) as it has the smallest footprint in comparison with the sponge-based Hash algorithm. Conventionally most of the security primitives are realized using more sequential logic which leads to an increase in the area occupied and latency. This work proposes a serialized architecture with a balance in sequential and combinational logic that uses lesser flipflops with a 21% increased performance for throughput/slice in comparison with reported works on target LUT-6 technology on FPGA, realized on the 14.2 ISE design suite. The work has a 4.6% decrease in quiescent power and dynamic power reported on the 14.2 ISE design suite for LUT-6 technology. This work has also achieved a Gate-Equivalence (GE) utilization for the proposed design on TSMC180 technology for a data path of 88-bit, while the proposed work reports 1204GE. In this work, a scaled-up architecture of the proposed SPONGENT-88 is realized for SPONGENT-128 and SPONGENT-224 as these variants provide improved security bound and is in comparison with the security provided by SHA-1 and SHA-2 algorithms. The scaled architecture for the latter variants of SPONGENT algorithms has achieved reduced Gate-Equivalence (GE) in comparison with the reported work.

РЕАЛИЗАЦИЯ В БАЗИСЕ ПЛИС РЕЛЯТОРНЫХ КОНТРОЛИРУЮЩИХ ОПРОСНЫХ УСТРОЙСТВ ЦИФРОВЫХ СИГНАЛОВ

The requirements for modern means of technical control and functional diagnostics ofequipment for critical applications are formulated, one of which is the processing of diagnosticinformation at a real-time pace. It is noted that for working with digital diagnostic signals, relational monitoring polling devices based on the apparatus of ordinal logic, which gives a significanttime gain over traditional binary logic, are promising. The hardware implementation of ordinal-logical polling devices in the FPGA basis, along with the obvious advantages of the developmentstage, will allow for operational reconfiguration of the internal structure to adapt to thechanging operating conditions of the control object. The hardware implementation of two knowndevices is considered. A variable priority device is used to identify the sensor that has detected afailure or malfunction, with the possibility of setting the sensor number from which the survey willbegin, and the direction of traversing the sensor tuple. The device of centralized control of a groupof objects is used to search for an extreme (maximum or minimum) digital diagnostic signal withsimultaneous determination of the number of the corresponding sensor in one clock cycle of themonitoring and diagnostic system. The development of combinational data schemes of monitoringsurvey devices was carried out by means of ISE Design Suite 14.7. The positive results of testingthe algorithms of the created models are presented, summarized in tables of the states of the inputsand outputs of the circuits and illustrated by time diagrams of binary signals at the terminals ofthe circuits. An estimate of the required FPGA resource costs is given, expressed in the number oflogical elements and user contacts. Also, using the example of low integration devices and themost resource-intensive samples, the upper and lower estimates of the number of FPGAs of varioustypes of the Xilinx Spartan-6, Xilinx Virtex-4 families and the domestic 5576/5578 series ofJSC KTC Electronics are given. It is established that with the number of diagnostic sensors up to200, depending on the FPGA family, up to 17 low integration chips and up to 7 resource-intensivechips are required to implement one monitoring polling device.

MAMDANI-TYPE FUZZY CONTROLLER TO DETERMINE BLOOD PRESSURE LEVELS BY REFLECTION PPG

This document presents the design of a fuzzy control system applying photoplethysmography techniques to generate input data and Mamdani-type fuzzy logic for its processing and generation of system output values, through which blood pressure levels can be indicated based on the parameters recommended by the medical area for an adult person. The integral design of the system includes the acquisition of the input signals, obtained through the reflection photoplethysmography technique, by means the optical coupling between IR light-emitting diodes and photo receptors, which allow the flow of current proportional to the amount of reflected light by blood, which is related to the flow level of the cardiac cavities, derived from the systolic and diastolic stages of the cardiac cycle. The fuzzy control was designed with two inputs and one output of 5 triangular membership functions each using the hardware description language (VHDL), the fuzzification, inference, aggregation and defuzzification stages were designed using the COSAA method. The response values ​​obtained using the Test Bench tool of ISE Design suite were compared with theoretical values ​​and with values ​​obtained with the Fuzzy Logic Designer tool of Matlab, the results showed an excellent approximation.

Multiple Stuck At Fault Diagnosis System For Digital Circuit On FPGA Using Vedic Multiplier and ANN

In an electronics circuit, the presence of a Fault leads to undesired or unexpected results. The output of many nodes on the circuit is changed due to the presence of the Fault at one node. So, it is necessary to detect the nature of the Fault present in a particular faulty node. To detect the fault present in the digital circuit, it is necessary to understand logical behavior using mathematical modeling. After the successful modeling, parameters are extracted, and the database is generated. The mathematical model uses Hebbian Artificial Neural Network algorithms [1] [2]. The database generated is used by the fault detection system to find the masked and multiple faults. A fault detection system monitors the faults present in the test circuit and finds the origin and nature of the Fault [3] [4]. The database generated for single stuck-at faults is used to find the multiple faults present in the faulty circuit. In this paper, Modified Vedic Multiplication [5] [4] method is used to optimize the utilization of the proposed system. In this proposed design multiplier of {N x N} bit input and {N} bit output is used, due to which device utilization is decreased, which is the expected outcome from the design. This system is designed using ISE Design Suite and implemented on Spartan-6 FPGA [6] [7].

An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA

This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-parallel multiplier in the proposed design results in high-speed (in terms of both clock frequency and latency). Consequently, the proposed BHC architecture, integrated with a least-significant-digit-parallel multiplier, is 1.42 times faster and utilizes 1.80 times lower FPGA slices when compared to the most recent BHC accelerator architectures.

Analysis of Velocity Measurement of Radar Signal in Space Vehicle Application using VLSI Chip

The objective of the project is to design a low cost Spectral Monitor for a Space vehicle velocity measurement application, based on Doppler Shift principle by generating an radar signal source from earth station towards moving target device in space and processing received high speed analog 200MHz radar signal from target vehicle device through Antenna, analog pre-processing and FPGA based spectral analyzer. The hardware reconfigurable spectral analyzer design consist of ADC(500MSPS) Interface block, SRAM Memory(1024×16) block, Radix-2 FFT (16 bit DSP block) and LCD Display (Monitoring) driver algorithm implemented On-Chip SOC-FPGA system. The proposed algorithm can be used to meet the need of many real time application such as space exploration, wideband communication, command and control application. The desired algorithm is implemented on-chip reconfigurable hardware SOC-FPGA while keeping the cost, power and area of device low compared to general purpose processor and Embedded based microcontroller. The code architecture is described using hardware description language, VHDL and synthesized and simulated using Xilinx 12.2 ISE Design suite.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

— Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)

High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

AbstractElliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high‐speed parallel re‐configurable finite field multipliers: PIMD‐2 and PIMD‐3 over prime field (Fp) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high‐speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD‐2 and PIMD‐3 designs are reduced simultaneously. The proposed Fp multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex‐5 and Virtex‐6 field programmable gate array (FPGA) platforms for common ECC key sizes 160–521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3× improvement in latency with lower area‐delay product and higher throughput per FPGA slice as compared to the state‐of‐the‐art.

Neural net implementation of steam properties on FPGA

Real time applications like model predictive control, monitoring and data reconciliation of power plants and industrial processes employ nonlinear mathematical models and require thermodynamic properties and their derivatives of working fluids. Applications like super heater temperature control based on energy balance and real time data reconciliation, require an efficient and a compact method for simultaneous estimation of thermodynamic properties, and their partial derivatives suitable for implementation in field-programmable gate array (FPGA). However, the complex mathematical formulations of these properties prohibit direct implementations in FPGAs. Single artificial neural network (ANN) architecture is used to replace the entire code in higher level languages, running into a few thousand lines. FPGA implementation of a compact neural network for the entire range of thermodynamic properties is presented. Large arguments in sigmoid function are factored into a product of integer and a fractional part which is represented using series approximation with five terms only and the integers are represented in look up table (LUT). This ensures optimum storage and computational burden for the above applications. The ANN is implemented in IEEE 754 floating point with synthesis in Xilinx ISE design suite using Verilog HDL. The results are presented for a typical pressure versus saturation temperature.

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC

In this manuscript, new quadrant-based search algorithm with zero motion prejudgment is proposed for motion estimation (ME) in HEVC (High Efficiency Video Coding) standard. The HEVC standard is used to obtain efficient output with low motion estimation time. The proposed quadrant-based search algorithm is a fast block matching algorithm that obtain better block matching amid the current block and reference block. The zero motion prejudgment (ZMP) method is used to find the block, whether it is motion or static and it is used for decreasing the computational complexity (CC) in the proposed quadrant-based search algorithm. The proposed quadrant-based search algorithm with ZMP technique for motion estimation in HEVC is implemented on the FPGA hardware platform. The entire architecture is executed in Verilog HDL with Virtex-5 technology and integrated with Xilinx ISE Design Suite 14.5. The results are integrated into the CIF (352 × 288 pixels) and HD (1280 × 720 pixels) video input sequence. The evaluation metrics like PSNR, Motion estimation time, sum of absolute difference (SAD) value are analyzed with existing method like hexagon, adaptive root pattern algorithm, and diamond search algorithm. Then the hardware parameters like power consumption and maximum operating frequency are measured. The hardware utilization is reduced and the power consumption of the proposed model is diminished to 0.143 W. The maximal operating frequency of the proposed model is 440.470 MHz. The experimental outcomes demonstrate that the proposed motion evaluation approach in HEVC is more effective than existing algorithms.

Magnitude Comparison and Sign Detection based on the 4-Moduli Set {2n+1, 2n−1, 2n+3, 2n−3}

The 4-moduli set residue number system (RNS),{2n+1, 2n−1, 2n+3, 2n−3}, with a wide dynamic range, has recently been proposed as a balanced 4-moduli set for utilizing the cases that demand fast calculations such as deep learning and implementation of asymmetric cryptographic algorithms. Up to now, only an unsigned reverse converter has been designed for this moduli set. Thus, there is a need for two separate units, a sign detection circuit, and a comparator to use this set in cases requiring sign and comparison. Nevertheless, the existence of these components demands high hardware that makes the implementation of the RNS impractical. Therefore, this paper presents the design of a sign detection circuit and a signed reverse converter that can overcome this problem by reusing the hardware. To achieve an integrated hardware design, first, we optimized the previous unsigned reverse converter for this 4-moduli set and next, we derived an approach from the structure of the reverse convertor for detecting signs and recognizing comparators. Finally, using the sign signals extracted from the reverse converter, we change reverse convertor into a unit that perform sign detection and comparison. The simulation has been conducted using ISE Design Suite 14.7 tool and the Spartan6 family technology. Empirical results show that, the proposed multifunctional unit has an approximately identical performance with respect to delay and area compared to the previous reverse converter. Besides, the proposed signed reverse converter relies on a 46% and 28% reduction in area and delay compared to the previous unsigned reverse converter which uses a comparator and also a multiplexer to detect a sign in the output.