Interrupt Service Routine Research Articles

Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction

To address the balanced requirements of performance, power consumption, and area in embedded systems, this paper introduces a 32-bit out-of-order processor based on the RISC-V instruction set, and the processor supports interrupt handling. This processor is designed to support the RV32IMC instruction subset and utilizes a four-stage pipeline structure featuring sequential instruction fetching, out-of-order execution, and out-of-order write-back. The main contributions are as follows:1) The segmented exclusive or G-share branch prediction scheme for embedded processors is proposed, which provides high branch prediction accuracy when the capacity of pattern history table (PHT) is small. 2) The work undertaken by hardware and software during interrupt response is reasonably divided, which allows for fast interrupt response with minimal resource consumption. Furthermore, the interrupt response time in vectored mode is reduced by simultaneously stacking the control and status registers (CSRs) and obtaining the interrupt service routine (ISR) entry address. Executing branch prediction-related programs within an identical environment, the processor detailed in this paper demonstrates an average prediction accuracy improvement of 1.2 % over G-share and 0.6 % over bi-mode branch prediction when employing the segmented exclusive or G-share branch prediction scheme. Building on this foundation, the on-chip debugging system and memory management unit have been implemented. The processor reaches 1.389 Dhrystone/MHz and 2.802 Coremark/MHz.

An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

Abstract Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.

PERFORMANCE COMPARISON OF USART COMMUNICATION BETWEEN REAL TIME OPERATING SYSTEM (RTOS) AND NATIVE INTERRUPT

Comunication between microcontrollers is one of the crucial point in embedded sytems. On the other hand, embedded system must be able to run many parallel task simultaneously. To handle this, we need a reliabe system that can do a multitasking without decreasing every task’s performance. The most widely used methods for multitasking in embedded systems are using Interrupt Service Routine (ISR) or using Real Time Operating System (RTOS). This research compared perfomance of USART communication on system with RTOS to a system that use interrupt. Experiments run on two identical development board XMega A3BU-Xplained which used intenal sensor (light and temperature) and used servo as external component. Perfomance comparison done by counting ping time (elapsing time to transmit data and get a reply as a mark that data has been received) and compare it. This experiments divided into two scenarios: (1) system loaded with many tasks, (2) system loaded with few tasks. Result of the experiments show that communication will be faster if system only loaded with few tasks. System with RTOS has won from interrupt in case (1), but lose to interrupt in case (2).

Implementing DDS Listeners using CAN Driver and its State manager

This paper addresses the Data Distribution Service DDS publish/subscribe middleware, which uses CAN driver and its State manager under µCOSII real-time operating system. Our research work consists on developing a real-time middleware in the C language. Starting with the Object Management Group (OMG) specification, which is developed in interface description language (idl) file, we use the idl to C mapping rules to create the Data Centric Publish Subscribe Application Programming Interface (API). We attach a special attention to DDS listeners and we give an approach to establish low-level communication using listeners, callback functions and CAN state manager. We specially focus on the default response of DDS entities following the ISR (Interrupt Service Routine) as communication behavior.

Synchronised carrier-based SVPWM signal generation scheme for the entire modulation range extending up to six-step mode using the sampled amplitudes of reference phase voltages

The issues in synchronised implementation of space vector-based pulse width modulation (SVPWM) signal generation are addressed on a conventional DSP platform. With the present day digital signal processors (DSPs) with clock over 10 MHz, it is possible to include additional tasks for synchronisation in the interrupt service routine (ISR). Also, the task of the synchronisation can be easily accommodated within the same ISR without disturbing the time critical pulse width modulation (PWM) operation. The authors systematically present the additional software requirements to determine the time period proportional to the half carrier switching time interval that is required for the synchronisation. First, the DSP implementation of the conventional multi-level SVPWM based on the sampled amplitudes of reference voltages is presented and then the additional requirements to maintain the PWM in synchronisation are discussed. The simulation results as well as experimental results are presented for a five-level PWM signal generation. A five-level inverter configuration, using a 1.5 kW open-end winding induction motor drive, is used for experimentally verifying the SVPWM.