Interprocessor Communication Mechanism Research Articles

Real-time million-synapse simulation of rat barrel cortex.

Simulations of neural circuits are bounded in scale and speed by available computing resources, and particularly by the differences in parallelism and communication patterns between the brain and high-performance computers. SpiNNaker is a computer architecture designed to address this problem by emulating the structure and function of neural tissue, using very many low-power processors and an interprocessor communication mechanism inspired by axonal arbors. Here we demonstrate that thousand-processor SpiNNaker prototypes can simulate models of the rodent barrel system comprising 50,000 neurons and 50 million synapses. We use the PyNN library to specify models, and the intrinsic features of Python to control experimental procedures and analysis. The models reproduce known thalamocortical response transformations, exhibit known, balanced dynamics of excitation and inhibition, and show a spatiotemporal spread of activity though the superficial cortical layers. These demonstrations are a significant step toward tractable simulations of entire cortical areas on the million-processor SpiNNaker machines in development.

Performance evaluation of inter-processor communication for an embedded heterogeneous multi-core processor

Embedded systems often use a heterogeneous multi-core processor to improve performance and energy efficiency. This multi-core processor is composed of a general purpose processor (GPP), which manages the program flow and I/O, and a digital signal processor (DSP), which processes mass data. An inter-processor communication (IPC) mechanism is thus required to exchange data between a GPP and a DSP. This paper uses comprehensive experiments to evaluate the IPC performance of an embedded heterogeneous multi-core processor under different design strategies. We further develop the IPC performance model and suggest dynamic adjustment of IPC strategies under environmental parameters and system resource constraints. Based on the results and findings, we improve the IPC performance of a voice over IP (VoIP) phone. Experimental results demonstrate that the GPP workload decreases significantly by 35% without sacrificing the functionalities and voice quality of the VoIP system. Moreover, we apply the concept of dynamic adjustment of IPC strategies to an embedded media gateway. The simulation results demonstrate that the dynamic IPC strategy can considerably improve the system performance of the media gateway compared with the static IPC design approach.

기가비트 라우터 시스템에서의 내부 데이터 처리를 위한 소프트웨어 구조

인터넷 사용자의 증가와 인터넷을 이용한 전자상거래(E-commerce)의 확산 그리고 네트워크 게임 등으로 인해 인터넷상의 사용자 데이터는 끊임없이 증가하고 있는 상태이다. 이러한 인터넷의 확산을 지원하기 위해 고속 통신을 가능하게 할 초고속 라우터가 상용화되는 추세이다. 고속의 패킷 라우팅 처리를 위해 고안된 라우터 구조를 살펴보면, 라인 인터페이스와 호스트 프로세서는 각각 제어용 프로세서를 가지고 있어 독립된 디바이스로 동작하며 패킷 스위칭과 고속의 패킷 포워딩, 신속한 FIB(Forwarding Information Base)처리 등을 구현하고 있다. 본 논문에서는 라우팅 정보를 관리하는 유니캐스트 및 멀티캐스트 라우팅 프로토콜과 OAM(Operation And Maintenance) 관련 패킷을 비포워딩(nonforwarding) 패킷으로 정의하고, 이를 처리하는 라인 인터페이스와 호스트 프로세서에서의 소프트웨어 구조를 제시하였다. 또한 분산 시스템에 요구되는 프로세서 간의 통신 메커니즘으로 프로세서간 통신 처리용 프로토콜(Inter-Processor Communication Message Protocol)을 설계 및 적용하여 기존의 UDP/IP를 이용하는 통신 메커니즘에 비해 성능이 향상됨을 확인하였다. Internet traffic is getting tremendously heavier due to the exponential growth of the Internet users, the spread of the E-commerce and the network games. High-speed routers for fast packet forwarding are commercially available to satisfy the growing bandwidth. A high-speed router, which has the decentralized multiprocessing architecture for IP and routing functions, consists of host processors, line interfaces and switch fabrics. In this paper, we propose a software architecture tuned for high-speed non-forwarding packet manipulation. IPCMP (Inter-Processor Communication Message Protocol), which is a mechanism for IPC (Inter-Processor Communication), is also proposed and implemented as well. Proposed IPC mechanism results in faster packet-processing rate by 10% as compared to the conventional IPC mechanism using UDP/IP.

Distributed System Design

Jie Wu CRC Press Publishing Company, Boca Raton, FL, 1998, 496 pp. ISBN 0-8493-3178-1, $74.95 The Distributed System Design is a superbly organized, comprehensive exposition of basic concepts, issues, and some possible solutions in the distributed systems design. Highly regarded author has meticulously selected the material from original sources of contemporary literature, new contributed papers by preeminent researchers in the field plus his own research results to provide state-of-the-art discussions on various important issues in distributed systems design. Graduate/senior undergraduate students in distributed systems design/advanced operating systems as well as computer professionals analyzing and designing distributed/open/parallel systems will find key insights into current trends and solutions of distributed systems likely to shape future directions of this important field. From the beginning, the author motivates the study of this subject well by pointing out that the future requirements for computing speed, system reliability, and cost-effectiveness entail the development of alternative computers to replace the traditional von Neumann organization. As computing networks come into being, one of the latest dreams is now possible—distributed computing. The twelve chapters of this book can be roughly divided into three parts. Part I (Chapters 1 to 3) introduces the necessary background material and foundations in the aspect of distributed system model, distributed programming languages and formal approaches to distributed systems design. The background material is comprehensive and the model that the author uses throughout the book is emphasized. This part gives the reader a perspective on past accomplishments and a global picture of the area. Part II (Chapters 4 to 11) addresses various important issues in distributed systems design such as mutual exclusion, deadlock, interprocessor communication mechanisms, reliability issue, static and dynamic load distribution and distributed data management. Each chapter concentrates on software elements of design that emphasize performance, flexibility, fault tolerance, and scalability. Each issue is put forward clearly by descriptions and diagrams. Possible solutions are presented with algorithms and explicit examples. Ample references are provided for further exploration of the issues. This part is beneficial to students/researchers on their research projects in distributed systems. Part III (Chapter 12) concentrates on the applications of distributed design in operating systems, file systems, shared memory systems, database systems and heterogeneous processing, which further demonstrate the significance of distributed systems. In addition, future research directions are listed that provide readers with the trend in this field. The exercises after each chapter are original, challenging and pertaining to the content just covered. They have a nice mix of theory, analysis, and design, which not only help readers refresh their knowledge but also widen their view scope of this subject. In summary, this book is a well-organized and thoroughly developed text with plenty of current issues and research results in distributed systems explained in supportive examples and illustrations. The major sections of the book are well ordered, as is each individual chapter. In a word, with a level of expertise simply unmatched in the field, Distributed System Design provides readers with a solid foundation to understand and further explore in this increasingly important area of technology. Xiao Chen Southwest Texas State University

The Chimera II real-time operating system for advanced sensor-based control applications

The Chimera II has been designed as a local operating system, to be used in conjunction with a global operating system. It executes on one or more single board computers in a VMEbus-based system. Advanced sensor-based control systems are both statistically and dynamically reconfigurable. As a result, they require many special features, which are currently not found in commercial real-time operating systems. Several design issues for such systems are presented as well as the features the authors have developed and implemented as part of Chimera II. These features include: a real-time kernel with dynamic scheduling, global error handling, user signals, and two levels of device drivers; an enhanced collection of interprocessor communication mechanisms, including global shared memory, spin-locks, remote semaphores, priority message passing, global state variable tables, multiprocessor servo task control, and host workstation integration; and several support utilities, including a UNIX C and math libraries, a matrix library, a command interpreter library, and a configuration file library.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multicast in hypercube multiprocessors

An efficient interprocessor communication mechanism is essential to the performance of hypercube multiprocessors. All existing hypercube multiprocessors basically support one-to-one interprocessor communication only. However, multicast (one-to-many) communication is highly demanded in executing many data parallel algorithms. A multicast algorithm should attempt to inform each destination in a minimum number of time steps while generating a least amount of traffic. In this paper, we first propose a graph theoretical model, the Optimal Multicast Tree (OMT), for interprocessor communication in distributed-memory multiprocessors. The problem of finding an OMT is conjectured to be NP-hard even for hypercube multiprocessors. A heuristic Greedy multicast algorithm which guarantees a minimized message delivery time is proposed. Simulation results show that the performance of the Greedy algorithm is very close to the optimal solution. Routing of multicast messages is done in a distributed manner. The hardware design of a VLSI router which supports all types of communications is briefly discussed.

A VLSI router design for hypercube multiprocessors

An efficient interprocessor communication mechanism is essential to the performance of hypercube multiprocessors. All existing hypercube multiprocessors only support one-to-one (unicast) communication. Multi-destination communication (multicast), which is highly demanded in many application areas, is not supported. Moreover, a store-and-forward routing scheme is usually used at each intermediate node, which further increases the communication delay. In this paper we present the hardware design of a VLSI router which is versatile in the sense that it supports unicast communication as well as multicast and broadcast communications. The router can handle messages with variable length and arbitrary number of destinations. For any type of communication, each destination will receive the source message in the minimum number of time steps. The total amount traffic created for message routing is minimum in the case of unicast and broadcast, and is very close to the optimal solution for multicast. Message passing is done in a distributed manner. The router handles message routing in a relay approach in which the routing decision is made immediately after the destination addresses are received. Architectural description of the router design is presented. A VLSI prototype design of the Message Handling Unit, an essential part of the router, is detailed.

Solving PDEs on loosely-coupled parallel processors

Partial differential equations (PDEs) account for a large part of scientific computing. As a special domain, they have a number of features which makes their solution on parallel computers particularly attractive. One is the highly-ordered structure of most solution algorithms; there is a regular pattern of memory access. Another is the wide range of solution algorithms from which to choose. Loosely-coupled parallel processors, using a message passing interprocessor communication mechanism, appear to match the data communication requirements of algorithms for PDEs. However, there are many unanswered questions: What is the best communication topology? How fast should the communication be relative to the floating-point speed? How much memory should each node have? The answers to these questions depend on the algorithms chosen. In this paper, we will look at three different classes of algorithms for PDEs and discuss their implications. From these results, we can make recommendations about the design of the next generation of these parallel computers.

Adapting Modula-2 for distributed systems

Modula-2 is a recently developed concurrent programming language designed primarily for implementation on a mono-processor. This paper reports on the changes found necessary, both to the source language and to the support environment, in order to allow the language to be used to program a tightly coupled, homogenous, distributed computing system. Specific areas covered are: the allocation of program code and data to processors, which is kept independent of the source code, allowing flexible re-allocation without re-compilation; the choice of an inter-processor communication mechanism, where the remote procedure call was considered to be the most flexible technique; and the selection of an inter-process communication mechanism, where, despite the distributed nature of the target, the monitor was found most suitable.

A distributed approach to the interconnection of heterogeneous computer networks

This paper describes a distributed architecture for the flexible interconnection of heterogeneous networks with a number of mini- and micro computers, in a research environment. The interconnected networks include the DARPA Internet, which uses the DoD protocols, and the X25-based networks PSS and SERCNET. The approach described here distributes the network access into a set of microcomputers acting as network frontends ("network access machines"), with a local area network (Cambridge Ring) as a common bus. Communication between the hosts and the network access machines uses an interprocessor communication mechanism with a standard transport-level virtualcall interface, which is described. This arrangement provides local hosts with flexible access to any of the networks, and supports a relay system which allows users on one network to access hosts and facilities on any of the other networks.

MODOSK: A modular distributed operating system kernel for real-time process control

The operating system kernel of a multiprocessor system based on 16 bit microcomputers is described. The multiprocessor system constitutes a node of a local computer network dedicated to the control of continuous or discontinuous industrial processes. The kernel makes available a virtual machine where processes allocated on different processors are executed in parallel, while processes which reside on the same processor are executed in a multitasking environment. The processes can cooperate by means of synchronization and message passing primitives; furthermore they can interact by means of short-term scheduling primitives which perform the creation, destruction, activation and termination of a process. The interprocessor communication mechanisms allow the primitives to make all process interactions transparent to the physical allocation of the interacting processes. The system has been completely implemented in the PASCAL language, excepting only few functions of the lowest level, coded in the assembler language. The distributed kernel has been developed and tested on a conventional monoprocessor machine (a DEC PDP11/34 computer under RSX11-M Operating System). Successively it has been transported on a microprocessor development system, where its time and space requirements have been evaluated.

On the development of a distributed operating system kernel for real-time applications

The operating system kernel of a multiprocessor system based on 16 bit microcomputers is described. The multiprocessor system constitutes a node of a local computer network dedicated to the control of continuous or discontinuous industrial processes. The kernel makes available a virtual machine where processes allocated on different processors are executed in parallel, while processes which reside on the same processor are executed in a multitasking environment. The processes can cooperate by means of synchronization and message passing primitives; furthermore they can interact by means of short-term scheduling primitives which perform the creation, destruction, activation and termination of a process. The interprocessor communication mechanisms allow the primitives to make all the process interactions transparent to the physical allocation of the interacting processes. The system has been completely implemented in the PASCAL language, excepting only few functions of the lowest level, coded in the assembler language. The distributed kernel has been developed and tested on a conventional machine (a DEC PDP11/34 computer under RSX11-M Operating System). The processes allocated on the same processor have been implemented as a single RSX11 task, and interprocessor communications have been simulated by means of intertask system primitives.