International Data Encryption Algorithm Research Articles

DESIGN AND IMPLEMENTATION OF IDEA ALGORITHM KEY SCHEDULE ON FPGA

In this paper the design and implementation of the International Data Encryption Algorithm (IDEA) key schedule is presented. The IDEA key schedule takes 128-bit input key and returns 52 subkeys each of 16 bits during the encryption or the decryption operation. The key schedule includes the design of the inverse modulo (216+ 1) multiplier and theinverse modulo 216 adder. The inverse modulo multiplier circuit is used to generate 18 inverse multiplicative keys and the inverse modulo adder circuit is used to generate 18 inverse additive keys. The inverse multiplicative key is calculated through multiplying the key to the power (216- 1) modulo (216+ 1). A 16 bit counter controls the inverse modulo multiplier circuit during the modulo multiplication process. A zero state problem is denoted during the generation of the inverse multiplicative keys because 216 is treated as zero during the modulo (216+ 1) multiplication in the encryption process. The IDEA key schdule is implemented on Xilinx FPGA Spartan II family and the target chip is XC2S100-5PQ208C.

Low‐power Implementation of an Encryption/Decryption System with Asynchronous Techniques

An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently in Wireless Encryption Protocols and high speed networks.

VOICE MAIL ENCRYPTION USING INTERNATIONAL DATA ENCRYPTION ALGORITHM

Nowadays, Electronic Voice Mail Services (EVMS) encryption is an area of a great interest due to the wide spreading of communication networks. If voice or some other analog signal must be conveyed with a high level of security then it should be digitized (A/D converted) and digitally encrypted. In the past, the digitization process was expensive so that analog scramblers found a place in the security business because of their lower cost and lower bandwidth requirements. The International Data Encryption Algorithm (IDEA) is one of the most secure block-ciphering algorithm. The key length of IDEA is 128 bits, which is hard to be broken with exhaustive search. There are no Substitution Code Boxes (S-boxes) in IDEA. Instead, there is a logical function that is especially designed in order to make the encryption algorithm itself the decryption algorithm, with another key. This means that the IDEA is asymmetric algorithm. This paper presents a study of using IDEA for speech encryption.

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm

A VLSI implementation of the International Data Encryption Algorithm is presented. Security considerations led to novel system concepts in chip design including protection of sensitive information and on-line failure detection capabilities. BIST was instrumental for reconciling contradicting requirements of VLSI testability and cryptographic security. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers, such as ECB, CBC, CFB, OFB, and MAC, are supported. In addition, new modes are proposed and implemented to fully exploit the algorithm's inherent parallelism. With a system clock frequency of 25 MHz the device permits a data conversion rate of more than 177 Mb/s. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM or FDDI.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>