Interlayer Dielectrics Research Articles

Fabrication of deep-sub-micrometer NbN/AlN/NbN epitaxial junctions on a Si-substrate

We have developed a novel fabrication process for ultra-small, full-epitaxial NbN Josephson junctions on a TiN buffered silicon (Si) substrate. We use an electron beam lithography for junction definition followed by a reactive-ion-etch (RIE). A chemical mechanical polishing process and an RIE by using CHF3 gas formed reliable electrical contacts for the junction electrodes. All junctions, with a junction size down to 0.27 μm in diameter, showed excellent current–voltage characteristics with a clear gap and small sub-gap leakage current. We have confirmed that the quality of the junctions was maintained after the removal of the SiO2 dielectric interlayer.

Flexible CMOS chip converted by a novel chip transformation process

In this Letter, the authors report a flexible CMOS chip converted by a novel chip transformation process. To realise a truly flexible CMOS chip, a two-step etching process was employed in the transformation process: (i) vapour etching to remove inter-dielectric layers followed by polymer encapsulation and (ii) plasma etching to remove the substrate of the chip. The I–V results measured after the chip transformation process show a voltage variance of <0.8% compared to the rigid chip. The bending test also revealed very small changes (0.6%) under strain conditions. Their results offer a viable route to use the foundry-fabricated CMOS chip for flexible chips; thus, a high-performance flexible chip can be realised. This technology will enable us to utilise various foundry-processed chips for future flexible applications such as health and environment monitoring, advanced mobile communication systems, and wearable electronics via a simple post-transformation process.

Multi-Stage Organic Logic Circuits Using Via-Hole-Less Metal Interconnects

Multi-metal interconnection is a crucial technology for the development of large-scale integrated circuits (ICs). However, organic semiconductors are not robust enough to be compatible with conventional lithography-and-etching-based via-forming methods. Thus, an alternative metal interconnect method is required for successful organic IC implementation. In-situ patterning of a dielectric polymer through a shadow mask while depositing in vapor phase possibly addresses the issues in both solvent susceptibility and process complexity. Here we report multi-stage organic logic circuits with a multi-level metal interconnection scheme based on patterned interlayer dielectrics via vapor phase deposition. We implement an exclusive OR circuit composed of four 2-input NAND gates and three-level metal interconnections to demonstrate the potential of the proposed solvent-free metal interconnection scheme.

Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation.

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

ZnO Nanowires on Single-Crystalline Aluminum Film Coupled with an Insulating WO3 Interlayer Manifesting Low Threshold SPP Laser Operation.

ZnO nanowire-based surface plasmon polariton (SPP) nanolasers with metal–insulator–semiconductor hierarchical nanostructures have emerged as potential candidates for integrated photonic applications. In the present study, we demonstrated an SPP nanolaser consisting of ZnO nanowires coupled with a single-crystalline aluminum (Al) film and a WO3 dielectric interlayer. High-quality ZnO nanowires were prepared using a vapor phase transport and condensation deposition process via catalyzed growth. Subsequently, prepared ZnO nanowires were transferred onto a single-crystalline Al film grown by molecular beam epitaxy (MBE). Meanwhile, a WO3 dielectric interlayer was deposited between the ZnO nanowires and Al film, via e-beam technique, to prevent the optical loss from dominating the metallic region. The metal–oxide–semiconductor (MOS) structured SPP laser, with an optimal WO3 insulating layer thickness of 3.6 nm, demonstrated an ultra-low threshold laser operation (lasing threshold of 0.79 MW cm−2). This threshold value was nearly eight times lower than that previously reported in similar ZnO/Al2O3/Al plasmonic lasers, which were ≈2.4 and ≈3 times suppressed compared to the SPP laser, with WO3 insulating layer thicknesses of 5 nm and 8 nm, respectively. Such suppression of the lasing threshold is attributed to the WO3 insulating layer, which mediated the strong confinement of the optical field in the subwavelength regime.

Terahertz Nonreciprocal Isolator Based on Magneto-Plasmon and Destructive Interference at Room Temperature

A terahertz isolator is demonstrated for the THz nonreciprocal reflections in the magneto-optical microstructure composed of InSb and metasurface with a dielectric interlayer. In the Voigt magnetic field configuration, the reflectance of the p-polarization waves obliquely impinging on the InSb wafer exhibits high nonreciprocity, while the reflectance of the s-polarized wave is reciprocal. Based on the unique magneto-plasmonic modes on the InSb surface, the nonreciprocal reflection in this device can be enhanced by using the destructive interference between the direct reflection and the multiple reflections in the resonance cavity between the InSb and metasurface. After the optimization, the isolation power of the device exceeds 55 dB with the insertion loss of only −3.92 dB under a very weak magnetic field of 0.2 T at room temperature. More importantly, the introduction of the metasurface can reduce the operating frequency of the isolator from 2.434 THz to 2.136 THz. This low-loss, weak magnetic field, room temperature operating, and high isolation THz isolator shows its broad potential in THz application systems.

A Chip Integrity Monitor for Evaluating Moisture/Ion Ingress in mm-Sized Single-Chip Implants

For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the packaging and lifetime prediction, the conventional helium leak test method can no longer be applied due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. Ingress of moisture/ions would result in changes in the resistance of the interlayer dielectrics (ILD) used within the chip and can be tracked using the proposed system, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18 μm 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. The system can measure the ILD resistance with values of up to 0.504peta-ohms, with controllable measurement steps that can be as low as 0.8M Ω. The system works with a supply voltage of 1.8V, and consumes 4.78mA. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chip's packaging.

Interlayer dielectrics based on copolyimides containing non-coplanar alicyclic-units for multilevel high-speed electronics

A series of copolyimides (CPIs) containing non-coplanar alicyclic units combined with fluorinated or rigid aromatic monomer segments is synthesized. The solid film samples display an elevated heat resistance as their degradation started at temperatures around 415 °C. Introduction into CPI backbone of bicyclic units, aromatic/aliphatic rings, angular bonds and/or low polarizable groups, determine the variation of the dielectric constant in the range 2.44–3.04 at 100 Hz. When using these CPIs as interlayer dielectrics (ILDs), it is revealed that resistance-capacitance delay is minimized (~10−11 s) determining faster response of the device. Atomic force microscopy scans of CPI samples show distinct macromolecular architectures, all containing nanopores with features depending on the chemical structure. Interfacial adhesion of investigated ILDs with copper wiring is highest for the samples lacking fluorine groups.

Effect of conditioner disc wear on frictional, thermal, kinetic and pad micro-textural attributes of interlayer dielectric and tungsten chemical mechanical planarization

A brand-new conventional diamond disc was subjected to 32 h of wear during which SEM images of active diamonds were taken, and pad cut rates (PCRs) were measured. Interlayer dielectric (ILD) wafers were polished before, midway through, and after the wear test (on a brand-new pad) at several values of polishing pressure and pad-wafer sliding velocities. Tungsten wafers were also polished midway through and after the 32 h wear. Polishing was accompanied by pad surface topography analysis via confocal microscopy. The disc experienced significant diamond tip micro-wear along with dried slurry accumulation on its substrate, causing the PCR to drop by a factor of 2. Despite this drastic change, over the duration of the wear test, there were no substantial changes in pad micro-texture, nor ILD or tungsten removal rates indicating the lack of any correlation between PCR and film removal rate during the first 32 h of wear.

Controlling the Charge Transfer across Thin Dielectric Interlayers

AbstractWhether intentional or unintentional, thin dielectric interlayers can be found in technologies ranging from catalysis to organic electronics. While originally considered as passive decoupling layers, recently it has been shown that they can actively promote charge transfer from the underlying metal to adsorbates. This charging can have profound effects on the surface chemistry of atoms, atomic clusters, and molecules, their magnetic moments, and charge injection at the contacts of organic devices. Yet, controlled studies required to understand the charge transfer process in depth are still lacking. Here, a comprehensive analysis of the phenomenon of charge transfer using the atomically controlled system of pentacene on ultrathin MgO(100) films on Ag(100) is presented. It is shown that the charge transfer process is governed by the charged and uncharged molecular species with distinct energy levels in the first monolayer. The experimental approach applied in this work allows to observe and control their ratio through direct tuning of either the work function or the thickness of the dielectric interlayer.

Development of adamantane-containing polybenzoxazines for dielectric interlayers applications

Low dielectric constant materials are appropriate solutions to address the propagation delay problem in ultra-large scale integrated circuits. Herein, adamantane is applied to improve the dielectric properties of polybenzoxazines. Monomers synthesized from bisphenol-A, 4,4'-diphenol and 1-amino adamantane are developed for understanding the properties of polybenzoxazines at molecular level. We found that incorporating adamantane results in much lower dielectric constant and loss factor without sacrificing the glass transition temperature and thermal stability, which are potential alternates as new dielectric interlayer materials.

PEN/BADCy Interlayer Dielectric Films with Tunable Microstructures via an Assist of Temperature for Enhanced Frequency Stability

Low dielectric interlayer films have become an important element to ensure the development of the microelectronics industry. A kind of flexible interlayer dielectrics, polyarylene ether nitrile/bisphenol A cyanate ester (PEN/BADCy) film, with good thermal stability and low frequency dependence, has been developed by solution casting method. Herein, materials were designed to incorporate bisphenol A cyanate ester as a part of blend, contributing to the frequency stability and structural integrity. The morphological study combined with electron microscopy revealed the uniform and flexible microstructure information with controllable morphology through self-polymerization of cyanate esters with different prepolymerization time and curing temperatures. The dielectric films could present high thermal stability with Tg>180 °C. Significant improvement in the dielectric properties was achieved for the dielectric constant and loss was much stabler than neat PEN over the frequency range from 100 Hz to 5 MHz. When the prepolymerization time was 3 h and final curing temperature reached 230 °C, the dielectric constant and dielectric loss of the films were 3.36 and 0.013 at 100 kHz, respectively. The dimensional stability (CTE = 53.67 × 10−6 K−1) was confirmed and considered beneficial to use as an interlayer dielectrics.

Quasi-3D Plasmonic Nanowell Array for Molecular Enrichment and SERS-Based Detection.

We report on a quasi-three-dimensional (3D) plasmonic nanowell array with high structural uniformity for molecular detection. The quasi-3D plasmonic nanowell array was composed of periodic hexagonal Au nanowells whose surface is densely covered with gold nanoparticles (Au NPs), separated by an ultrathin dielectric interlayer. The uniform array of the Au nanowells was fabricated by nanoimprint lithography and deposition of Au thin film. A self-assembled monolayer (SAM) of perfluorodecanethiol (PFDT) was coated on the Au surface, on which Au was further deposited. Interestingly, the PFDT-coated Au nanowells were fully covered with Au NPs with an ultra-high density of 375 μm−2 rather than a smooth film due to the anti-wetting property of the low-energy surface. The plasmonic nanogaps formed among the high-density Au NPs led to a strong near-field enhancement via coupled localized surface plasmon resonance and produced a uniform surface-enhanced Raman spectroscopy (SERS) response with a small relative standard deviation of 5.3%. Importantly, the highly uniform nanostructure, featured by the nanoimprint lithography and 3D growth of densely-packed Au NPs, minimizes the spatial variation of Raman intensity, potentially providing quantitative analysis. Moreover, analyte molecules were highly concentrated and selectively deposited in nanowells when a water droplet containing the analyte was evaporated on the plasmonic substrate. The analyte formed a relatively thick overcoat in the nanowells near the triple line due to the coffee-ring effects. Combining 3D plasmonic nanowell substrates with molecular enrichments, highly sensitive detection of lactic acid was demonstrated. Given its combination of high sensitivity and signal uniformity, the quasi-3D plasmonic nanowell substrate is expected to provide a superior molecular detection platform for biosensing applications.

Effect of Thermal Boundary Resistance between the Interconnect Metal and Dielectric Interlayer on Temperature Increase of Interconnects in Deeply Scaled VLSI.

Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10-8 to 1 × 10-7 m2 K W-1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.

Electro-Thermal Model for Thermal Disturbance in Cross-Point Phase-Change Memory

We developed an electro-thermal model for cross-point phase-change memory (X-PCM) and compared the calculation values with the experimental results. In order to simulate the electro-thermal phenomenon such as thermal disturbance (TDB) of victim cells and reset the current ( ${I}_{{\text {RESET}}}$ ) of aggressor cells in a fully confined cross-point structure, a three by three mini-array was constructed with the finite-elemental method. Unlike the conventional thermal model, which only shows the temperature gradient for TDB, our new model can predict the crystallization behavior of victim cells by combining the crystallization model for nucleation and growth. This makes it possible to compare the calculation results with the experimental ones through the crystalline fraction of the victim cell. The simulation results clearly reveal that our new model can closely estimate the victim cell’s crystalline fraction for TDB, with the variation of both pulse height (PH) and pulse width (PW) during the RESET operation. Applying the confirmed model for devices of smaller dimensions shows that TDB increases as the device scales down. The increase of TDB is particularly severe as cells become smaller than 16 nm. We suggest that TDB can be reduced not only by decreasing the thermal conductivity ( $\kappa $ ) of the interlayer dielectric (ILD), but also by minimizing the PW of the aggressor.

Giant optical activity in plasmonic chiral structure via double-layer graphene moiré stacking in mid-infrared region.

The plasmonic metamaterials and metasurfaces play a critical role in manipulating lights in the mid-infrared spectral region. Here, we first propose a novel plasmonic chiral structure with the giant optical activity in the mid-infrared spectral region. The chiral structure consists of the moiré patterns, which are formed by stacking double-layer graphene nanoribbons with a relative in-plane rotation angle. It is demonstrated that the graphene-based plasmonic structure with moiré patterns exhibits the strong circular dichroism. The giant chiroptical response can be precisely controlled by changing the rotation angle and Fermi level of graphene. Furthermore, a dielectric interlayer is inserted between two layers of graphene to obtain the stronger circular dichroism. Impressively, the strongest circular dichroism can reach 5.94 deg at 13.6 µm when the thickness of dielectric interlayer is 20 nm. The proposed structure with graphene-based moiré patterns can be superior to conventional graphene chiral metamaterials due to some advantage of rotation-dependent chirality, flexible tunability and cost-effective fabrication. It will advance many essential mid-infrared applications, such as chiral sensors, thermal imaging and chiroptical detectors.

Correlating Coefficient of Friction and Shear Force to Platen Motor Current in Tungsten and Interlayer Dielectric Chemical Mechanical Planarization at Steady-State Conditions

Following up our earlier work that highlighted the relationship between shear force (SF) and platen motor current (PMC), in parallel with the relationship between coefficient of friction (COF) and PMC for various tungsten and interlayer dielectric (ILD) chemical mechanical planarization (CMP) cases at non-steady-state conditions, we explored whether or not PMC could be used as a reliable indicator instead of SF and COF at steady-state conditions. For the 12 cases studied, 72 distinct steps were analyzed. It was determined that PMC somewhat mirrored SF and PMC for long time (i.e. 10 s or longer) intervals after data averaging and applying a trend matching algorithm. SF and PMC trends matched only about 64% of the time (ranges between 45% to 85%) for all 72 steps, while PMC and COF trends matched 62% of the time ranging between 42% and 85%. PMC-SF and PMC-COF correlations were fairly poor at 1-sec time intervals as evidenced by much lower percent match values. Such poor correlations proved that at small time intervals, PMC was not sensitive enough to capture important information regarding myriad fluid dynamics and tribological phenomena and the instantaneous stick-slip occurrences encountered in CMP.

Mathematical modeling based on contact mechanism due to elastic and plastic deformation of pad asperities during CMP

Technologies in semiconductor industry have been developed into a three-dimensional multilayer wiring for high integration of devices. Chemical mechanical planarization (CMP) process is one of the key technologies for achieving multilayer wiring, which enables global planarization. In addition, highly integrated devices can be realized by increasing the depth of focus in the photolithography process. However, in the inter-layer dielectric (ILD) CMP of the transistor, the uppermost oxide layer has the step due to the arrangement of the devices. The ideal material removal mechanism is to gradually remove materials from the top of the step height which allows for global planarization. However, in the CMP of the patterned wafers, simultaneous polishing of the upper and lower layers occurs when the step height reaches a certain height. This means that the polishing is strongly dependent on the structural characteristics of the pattern. Especially, the difference in the material removal rate depending on the pattern density acts as a constraint in terms of device layout. Therefore, it is essential to develop an accurate prediction model of material removal rate as a function of pattern density, size and arrangement. This study aims to define the mathematical planarization model according to contact mode between a polishing pad and patterned wafer. Considering that the real contact area between the actual polishing pad and the wafer is about 1 %, the mathematical model is derived based on the microscopic deformation of the pad asperities, not the macroscopic deformation of the bulk pad. Finally, we describe the verification between the theoretical material removal rate model and step height reduction and the actual CMP results. The root mean square error of the upper layer material rate, the lower material removal rate, and the step height reduction were 24.59 nm/min, 22.03 nm/min and 22.6 nm, respectively. Compared with the previous studies, the new model of this study improved the error by up to 50.9 %.

Schottky Barrier Height Engineering inβ-Ga2O3Using SiO2Interlayer Dielectric

This paper reports on the modulation of Schottky barrier heights (SBH) on three different orientations of $\beta$-Ga$_2$O$_3$ by insertion of an ultra-thin SiO$_2$ dielectric interlayer at the metal-semiconductor junction, which can potentially lower the Fermi-level pinning (FLP) effect due to metal-induced gap states (MIGS). Pt and Ni metal-semiconductor (MS) and metal-interlayer-semiconductor (MIS) Schottky barrier diodes were fabricated on bulk n-type doped $\beta$-Ga$_2$O$_3$ single crystal substrates along the (010), (-201) and (100) orientations and were characterized by room temperature current-voltage (I-V) and capacitance-voltage (C-V) measurements. Pt MIS diodes exhibited 0.53 eV and 0.37 eV increment in SBH along the (010) and (-201) orientations respectively as compared to their respective MS counterparts. The highest SBH of 1.81 eV was achieved on the (010)-oriented MIS SBD using Pt metal. The MIS SBDs on (100)-oriented substrates exhibited a dramatic increment ($>$1.5$\times$) in SBH as well as reduction in reverse leakage current. The use of thin dielectric interlayers can be an efficient experimental method to modulate SBH of metal/Ga$_2$O$_3$ junctions.

Contact etch process optimization for RF process wafer edge yield improvement

Radio-frequency (RF) process products suffer from a wafer edge low yield issue, which is induced by contact opening. A failure mechanism has been proposed that is based on the characteristics of a wafer edge film stack. The large step height at the wafer’s edge leads to worse planarization for the sparse poly-pattern region during the inter-layer dielectric (ILD) chemical mechanical polishing (CMP) process. A thicker bottom anti-reflect coating (BARC) layer was introduced for a sparse poly-pattern at the wafer edge region. The contact open issue was solved by increasing the break through (BT) time to get a large enough window. Well profile and resistance uniformity were obtained by contact etch recipe optimization.