Interface State Density Profiles Research Articles

Quantitative evaluation of plasma-damaged SiN/Si structures using bias-dependent admittance analysis

Plasma process-induced damage (PID) to SiN dielectric films was investigated by using an impedance (admittance)-based technique. Multi-layered equivalent circuits were introduced to assign the spatial and energy distribution of defects created in the SiN/Si system. We propose to use admittance as the principal parameter for damaged SiN/Si systems after Ar and He plasma exposures. The change in the border trap density was determined from the admittance in accumulation, whereas the interface state density and energy profile that was created was determined from the admittance in depletion. Plasma source-dependent damage-creation mechanisms are discussed. It was found that the extracted border trap density in the He plasma-damaged sample was larger than that in the Ar plasma-damaged sample under the same ion dosage. The proposed characterization scheme is useful for assessing PID to dielectric/Si systems.

Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor**Project supported by the National Natural Science Foundation of China (Grant Nos. 61574109 and 61204092).

Trap-assisted tunneling (TAT) has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor (TFET). In this paper, we assess subthreshold performance of double gate TFET (DG-TFET) through a band-to-band tunneling (BTBT) model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile (Dit) and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.

The role of cold carriers and the multiple-carrier process of Si–H bond dissociation for hot-carrier degradation in n- and p-channel LDMOS devices

We apply our hot-carrier degradation (HCD) model, which uses the information about the carrier energy distribution, to represent HCD data measured in n- and p-channel LDMOS transistors. In the first version of our model we use the spherical harmonics expansion approach to solve the Boltzmann transport equation (BTE), while in the second version we employ the drift–diffusion scheme. In the latter case the carrier energy distribution function is approximated by an analytic expression with parameters found using the drift–diffusion scheme. The model, which has already been verified with nLDMOS transistors, is used to represent the carrier distribution functions, interface state density profiles, and changes of the drain currents vs. stress time in pLDMOS transistor. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. We check the validity of the model by neglecting the effect of cold carriers in HCD modeling in the case of nLDMOS devices stressed at high voltages. In our model, cold carriers are represented by the corresponding term in the analytic formula for the carrier distribution function as well as by the multiple-carrier process of the Si–H bond dissociation. We show that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

Comparison of analytic distribution function models for hot-carrier degradation modeling in nLDMOSFETs

We analyze the applicability of different analytic models for the carrier distribution function (DF), namely the heated Maxwellian, the Cassi model, the Hasnat approach, the Reggiani model, and our own concept, to describe hot-carrier degradation (HCD) in nLDMOS devices. As a reference, we also obtain the carrier distribution function as a direct solution of the Boltzmann transport equation using the spherical harmonics expansion method. The DFs evaluated with these models are used to simulate the interface state generation rates, the interface state density profiles, and changes of the linear and saturation drain currents as well as the threshold voltage shift. We show that the heated Maxwellian approach leads to an underestimated HCD at long stress times. This trend is also typical for the Cassi and Hasnat models but in these models HCD is underestimated in the entire stress time window. While the Reggiani model gives good results in the channel and drift regions, it cannot properly represent the high-energy tails of the DF near the drain, and thus leads to a weaker curvature of the degradation traces. We show finally that our model is capable of capturing DFs with very good accuracy and, as a result, the change of the device characteristics with stress time.

Interface trap characterization of atomic layer deposition Al2O3/GaN metal-insulator-semiconductor capacitors using optically and thermally based deep level spectroscopies

Quantitative measurements of interface state density and energy distribution profiles within Al2O3/GaN interfaces were obtained by constant capacitance deep level transient spectroscopy and deep level optical spectroscopy (CC-DLTS/DLOS). The new application of CC-DLOS to interface state measurement is described, which allows interrogation of very deep interface states. A series of Al2O3/GaN metal-insulator-semiconductor (MIS) devices prepared as a function of Al2O3 thickness via atomic layer deposition, on NH3-MBE-grown n-type Ga-polar GaN layers enabled a systematic study. The overall shape and magnitude of the interface trap distribution, Dit, were determined to be nearly identical, independent of Al2O3 thickness. The Al2O3/GaN Dit spectra had an overall U-shape with Dit ∼1012 cm−2 eV−1 near the conduction band edge, ∼1011 cm−2 eV−1 mid-gap, and ∼1014 cm−2 eV−1 near the valence band edge. However, the interface states near the GaN conduction band showed a slight inverse dependence on Al2O3 thickness, suggestive of annealing effect during deposition. The high near valence band state concentrations are consistent with expectations from residual carbon impurities at the GaN surface. A method for discriminating between bulk and interface states in the CC-DLTS signal is demonstrated, using the results on MIS capacitors in combination with spectroscopy results on a Schottky diode structure.

InGaAs MOS Transistors Fabricated through a Digital-Etch Gate-Recess Process and the Influence of Forming Gas Anneal on Their Electrical Behavior

InGaAs channel Implant-Free Quantum-Well (IFQW) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) were fabricated and characterized using a digital etch gate-recess process. InGaAs surface morphology after the digital etching using different chemistries was investigated by Atomic Force Microscopy (AFM). The digital etch rate was characterized both electrically and physically. The resulting InGaAs surface properties were evaluated by characterizing the IFQW-MOSFETs with an atomic-layer-deposited (ALD) Al2O3 gate dielectric. Well-behaved MOSFET devices were demonstrated indicating the excellent surface properties after the digital etch. Impact of thermal anneals on the device performance was systematically studied and significant improvements were observed after forming gas anneal (FGA). The resulting interface state density (Dit) profiles were characterized applying the conductance method.

Effect of the frequency and temperature on the complex impedance spectroscopy (C–V and G–V) of p-ZnGa2Se4/n-Si nanostructure heterojunction diode

X-ray diffraction pattern and AFM results confirm the nanostructure of p-ZnGa2Se4/n-Si. The unit cell lattice parameters, the crystallite size L, the dislocation density δ, and the main internal strain e were calculated. The temperature and frequency-dependent electrical characteristics of the Al/p-ZnGa2Se4/n-Si/Al heterojunction diode (HJD) have been investigated to determine the interface states which are responsible for the non-ideal behavior of the characteristics of the diode. The capacitance–voltage (C–V), conductance–voltage (G–V), and series resistance–voltage (Rs–V) characteristics of the diode have been analyzed in the frequency range of 5 kHz–1 MHz and temperature range of 303–423 K. The interfaces states of the diode were determined using conductance–voltage technique. The interface state density profile for the diode was obtained as a function of temperature and frequency. The values of the built-in potential Vbi, the doping concentration Nd and the barrier height φb(C–V) of the diode were calculated at different temperatures and frequencies. Our experimental results revealed that both the series resistance and interface state density values must be taken into account in studying the impedance spectroscopy of HJD to stand up their performance for electronic applications characteristics.

Accurate Extraction of MOSFET Unstressed Interface State Spatial Distribution from Charge Pumping Measurements

The interface state density profile for an unstressed transistor has been carefully extracted. The experimental evidence of profile non-uniformity is presented. A scheme to separate the bulk oxide trap contribution from the total charge pumping current is suggested as an improvement to the conventional extraction procedure. The obtained information is of high importance in the context of hot-carrier degradation modeling in order to allow for a more detailed verification of the model.

Hot-carrier degradation caused interface state profile—Simulation versus experiment

Hot-carrier degradation is associated with the buildup of defects at or near the silicon/silicon dioxide interfaced of a metal-oxide-semiconductor transistor. However, the exact location of the defects, as well as their temporal buildup during stress, is rarely studied. In this work we directly compare the experimental interface state density profiles generated during hot-carrier stress with simulation results obtained by a hot-carrier degradation model. The developed model tries to capture the physical picture behind hot-carrier degradation in as much detail as feasible. The simulation framework includes a transport module, a module describing the microscopic mechanisms of defect generation, and a module responsible for the simulation of degraded devices. Due to the model complexity it is very important to perform a thorough check of the output data of each module before it is used as the input for the next module. In this context a comparison of the experimental interface state concentration observed by the charge-pumping technique with the simulated one is of great importance. Obtained results not only show a good agreement between experiment and theory but also allow us to draw some important conclusions. First, we demonstrate that the multiple-particle mechanism of Si–H bond breakage plays a significant role even in the case of a high-voltage device. Second, the absence of the lateral shift of the charge-pumping signal means that no bulk oxide charge buildup occurs. Finally, the peak of interface state density corresponds to the peak of the carrier acceleration integral and is markedly shifted from typical markers such as the maximum of the electric field or the carrier temperature. This is because the degradation is controlled by the carrier distribution function and simplified schemes of hot-carrier treatment (based on the mentioned quantities) fail to describe the matter.

Band offsets and band bending at heterovalent semiconductor interfaces

We present a comprehensive study of band offsets and band bending at heterovalent semiconductor heterointerfaces. A perfectly abrupt heterovalent interface is usually thermodynamically unstable, and atomic intermixing of materials with different numbers of valence electrons causes large variations in band offsets and local doping density, depending on the spatial arrangement of atoms at the interface. The studied prototypical II-VI/III-V semiconductor interfaces are $n$-doped ZnSe/GaAs (001) heterostructures with varied composition profiles close to the interface, which were realized by molecular-beam epitaxy with different amounts of Zn or Se predeposited on $n$-GaAs prior to $n$-ZnSe layer growth. The samples are characterized by temperature-dependent electrical transport across the interface, electrochemical capacitance-voltage profiling, Raman spectroscopy, and high-resolution x-ray diffraction. We find that the potential barrier in the conduction band at a Zn-rich $n$-ZnSe/$n$-GaAs interface is as high as 550 meV and it gradually decreases with Se predeposition down to about 70 meV. A large depletion region at the heterointerface, about 50 nm wide, is assigned to significant intermixing of acceptor-type atoms, resulting in an effective electron deficit of $1.5\ifmmode\times\else\texttimes\fi{}{10}^{13}\text{ }{\text{cm}}^{\ensuremath{-}2}$. The depletion width and the acceptor density around the interface are nearly independent from the growth start procedure. Se predeposition, however, partially shifts the depletion region at the heterointerface from GaAs into ZnSe, compared to Zn predeposition. The results are discussed on the basis of a band-bending model accounting for variable band offsets, interface state density and atomic interdiffusion profiles depending on growth start.

Effect of interface states on sub-threshold response of III–V MOSFETs, MOS HEMTs and tunnel FETs

The effect of interface states on the current–voltage characteristics in the sub-threshold region of three different types of III–V based transistor architectures has been studied using a drift–diffusion based numerical simulator. Experimentally extracted interface state density profile is included in the simulation to analyze their effect on the sub-threshold response of InGaAs based MOSFETs, MOS HEMTs and tunnel FETs. Based on the Fermi-level position at the oxide/semiconductor interface and the corresponding interface state density ( D it), the sub-threshold response for the three devices can vary, with tunnel FETs having the least sub-threshold degradation due to D it.

Electrical characterization and device characterization of ZnO microring shaped films by sol–gel method

Zinc oxide microrings formed nanoparticles were prepared on n-type silicon substrate by sol–gel method. The structure of ZnO film is confirmed by XRD analysis and ZnO film exhibits a polycrystalline grown with a hexagonal wurtzite-type. The optical band gap of the ZnO film deposited on silicon substrate was determined using the reflectance spectra by means of Kubelka-Munk formula and was found to be 3.22 eV. The structural properties of the ZnO film were investigated by atomic force microscopy. The AFM results indicate that the ZnO film is consisted of microrings with nanoparticles. A single phase of ZnO microring with outer diameter is ranging from 2.2 μm to 1.72 μm and inner diameters ranging from 125 nm to 470 nm was obtained. A Schottky diode having Au/n-type ZnO plus n-type silicon structure was fabricated. The current–voltage and impedance spectroscopy properties of the diode have been investigated. The barrier height ϕ b and ideality factor n values for the diode were found to be 0.80 eV and 2.01, respectively. The series resistance for the diode was calculated from the admittance behavior in accumulation region. The interface state density profile for the diode was obtained. The obtained results indicate that the electric parameters of the diode are affected by structural properties of ZnO film.

The influence of series resistance and interface states on intersecting behavior of I–V characteristics of Al/TiO2/p-Si (MIS) structures at low temperatures

In this study, we have investigated the intersection behavior of the forward bias current–voltage (I–V) characteristics of the Al/TiO2/p-Si (MIS) structures in the temperature range of 100–300 K. The intersection behavior of the I–V curves appears as an abnormality when compared to the conventional behavior of ideal Schottky diodes and MIS structures. This behavior is attributed to the lack of free charge at a low temperature and in the temperature region, where there is no carrier freezing out, which is non-negligible at low temperatures, in particular. The values calculated from the temperature-dependent forward bias I–V data exhibit unusual behavior, where the zero-bias barrier height (ϕb0) and the series resistance (Rs) increase with increasing temperature. Such temperature dependence of ϕb0 and Rs is in obvious disagreement with the reported negative temperature coefficient. An apparent increase in the ideality factor (n) and a decrease in the ϕb0 at low temperatures can be attributed to the inhomogeneities of the barrier height, the thickness of the insulator layer and non-uniformity of the interfacial charges. The temperature dependence of the experimental I–V data of the Al/TiO2/p-Si (MIS) structures has revealed the existence of a double Gaussian distribution with mean barrier height values () of 1.108 eV and 0.649 eV, and standard deviations (σs) of 0.137 V and 0.077 V, respectively. Furthermore, the temperature dependence of the energy distribution of interface state density (Nss) profiles has been determined from forward bias I–V measurements by taking into account the bias dependence of the effective barrier height (ϕe) and n. The fact that the values of Nss increase with increasing temperature has been attributed to the molecular restructuring and reordering at the metal/semiconductor interface under the effect of temperature.

Electrical transport characteristics of Sn/p-Si schottky contacts revealed from I– V– T and C– V– T measurements

The current–voltage ( I– V) and capacitance–voltage ( C– V) characteristics of metal–semiconductor (Sn/p-Si) Schottky contacts were measured in the temperature range 150–400 K. The effect of the temperature on the series resistances R S, ideality factors n, the barrier height Φ b and interface state density N SS obtained from the I– V and C– V characteristics were investigated. The n, Φ b, R S, and N SS values were seen to be strongly temperature dependent. The ideality factors, series resistances and interface state densities decreased with increasing temperature for all diodes and the values of n, R S, and N SS obtained from I– V and C– V measurements were found in the ranges of 2.024–1.108, 2.083–1.121; 79.508–33.397 Ω; and 2.14×10 13–0.216×10 13 cm 2 eV −1, 2.277×10 13–0.254×10 13 cm 2 eV −1, respectively. The temperature dependence of energy distribution of interface state density ( N SS) profiles has been determined from I– V measurements by taking into account the bias dependence of the effective barrier height and ideality factor.

Current transport mechanism in Al/Si 3N 4/p-Si (MIS) Schottky barrier diodes at low temperatures

The current–voltage ( I– V) and capacitance–voltage ( C– V) characteristics of metal–insulator–semiconductor (Al/Si 3N 4/p-Si) Schottky barrier diodes (SBDs) were measured in the temperature range of 80–300 K. By using the thermionic emission (TE) theory, the zero-bias barrier height Φ B0 calculated from I– V characteristics was found to increase with increasing temperature. Such temperature dependence is an obvious disagreement with the negative temperature coefficient of the barrier height calculated from C– V characteristics. Also, the ideality factor decreases with increasing temperature, and especially the activation energy plot is nonlinear at low temperatures. Such behaviour is attributed to Schottky barrier inhomogeneties by assuming a Gaussian distribution of barrier heights (BHs) at interface. We attempted to draw a Φ B0 versus q/2 kT plot to obtain evidence of a Gaussian distribution of the BHs, and the values of Φ Bo = 0.826 eV and α o = 0.091 V for the mean barrier height and standard deviation at zero-bias, respectively, have been obtained from this plot. Thus, a modified ln( I o/ T 2) − q 2 σ o 2/2( kT) 2 versus q/ kT plot gives Φ B0 and Richardson constant A * as 0.820 eV and 30.273 A/cm 2 K 2, respectively, without using the temperature coefficient of the barrier height. This value of the Richardson constant 30.273 A/cm 2 K 2 is very close to the theoretical value of 32 A/cm 2 K 2 for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I– V characteristics of the Al/Si 3N 4/p-Si Schottky barrier diodes can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights. In addition, the temperature dependence of energy distribution of interface state density ( N SS) profiles was determined from the forward I– V measurements by taking into account the bias dependence of the effective barrier height and ideality factor.

Electrical Evaluation of Defects at the Si ( 100 ) / HfO2 Interface

This work examines the electrical activity of defects at the interface with Si(100) for thin films (10-20 nm) deposited by injection metal oxide chemical vapor deposition. Based on an analysis of the capacitance-voltage response of structures, two clear peaks are detected in the interface state density profiles, at specific energies in the lower eV) and upper eV) bandgap. The densities of defects responsible for these peaks have been calculated as and respectively. These defects are present when the films were deposited at sufficiently low temperatures to prevent hydrogen passivation. The density of interface defects was not significantly different for films deposited on native oxide or hydrogen-terminated silicon surfaces. The position of these defects in the silicon bandgap corresponds to the location of dangling bond defects in the thermally oxidized system. films deposited at 450°C did not exhibit the prominent interface defects observed on films deposited at indicating hydrogen passivation during deposition. © 2004 The Electrochemical Society. All rights reserved.

The Impact of Rapid Thermal Annealing on the Properties of the Si (100)-SiO2 Interface

AbstractIn this work, we present results and analysis which demonstrate the influence of rapid thermal annealing (RTA) on the properties of the Si(100)-SiO2 interface. Polysilicon/oxide/silicon capacitor structures were subjected to RTA treatments, in a nitrogen ambient, over the temperature range 600-1050°C. The structures were examined using high frequency and quasi-static capacitance-voltage (CV) analysis to determine the interface state density profile across the energy gap immediately following the RTA step. The effect of hydrogen annealing subsequent to the RTA process is also presented. Based on the analysis of the interface state density profiles, it is suggested in this work, that RTA (T > 600°C) exposes silicon dangling bond (Pb) centres at the Si(100)-SiO2 interface. The implications of this work to the study of the Si-SiO2 interface, and the technological implications for silicon based MOS processes, are discussed.

Ensemble Monte Carlo study of interface-state generation in low-voltage scaled silicon MOS devices

An ensemble Monte Carlo (MC) model coupled with an interface-state generation model was employed to predict the quantity and lateral distribution of hot-electron-induced interface states in scaled silicon MOSFETs. Constant field and more generalized scaling methods were used as the basis to simulate devices with 0.33-, 0.20-, and 0.12-/spl mu/m channel lengths. The dependencies of interface-state generation on applied bias and electric field profiles were investigated. Hot-electron injection and interface-state density profiles were simulated at biases as low as 1.44 V (i.e., lower than the 3.1 V potential barrier at the Si/SiO/sub 2/ interface). These simulations demonstrate that "lucky electron" and/or electron temperature models are no longer accurate for predicting hot-electron effects in such regimes. Electron-electron scattering is shown to be a critical consideration for simulation of hot-electron injection at low drain to source bias voltages, where local interfacial barrier heights are greater than the energy gained by an electron from the applied electric field. Simulations indicate that a scaled decrease in the channel length of a device may be accompanied by an increase in the lateral electric field without incurring a penalty for higher hot-electron degradation. It is also shown that conventional hot-electron stressing using accelerated stress bias conditions may continue to be valuable for predicting the reliability of device designs scaled to 0.1-/spl mu/m channel lengths.

Extraction of interface state density profile from the maximums of the parallel conductance versus applied gate bias curves G p(Va), using the conductance technique

A fast method for extracting the interface trap density profile of the semiconductor-insulator interface in metal-insulator-semiconductor structures is proposed. The method is based on the well known conductance technique and extracts the interface state density profile from the maximums of the parallel conductance versus applied gate bias curves, Gp(Va). In addition, this method is directly applicable to fully automated experimental setups available in industrial environments.

Measurements of interface state density in partially- and fully-depleted silicon-on-insulator MOSFETs by a high-low-frequency transconductance method

The high-low-frequency (HLF) transconductance method is applied to determine the interface state density profile in small-geometry thick- and thin-film (fully depleted) MOSFETs formed on single-and multiple-oxygen implanted (SIMOX) Si substrates. By comparing the real part of the measured high-and low-frequency transconductance and using a static drain current-to-gate voltage measurement on a MOSFET operating in the linear region, the energy distribution of the interface state density is determined without knowing the doping profile in the channel. The results yielded the interface state density in the range of ∼5 to 10 × 10 10 eV −1 cm −2 for single implanted samples and 2 × 10 10 eV −1 cm −2 for multi-implanted samples. Interface state densities determined by the HLF transconductance method were found in good agreement with that determined by the charge pumping (CP) method.