Interface State Capacitance Research Articles

Comprehensive Capacitance–Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on Si<italic>x</italic>Ge1−<italic>x</italic> and In<italic>x</italic>Ga1−<italic>x</italic>As: Part I—Model Description and Validation

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C–V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi–Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance ( ${C}_{\mathsf {it}}$ ) is implemented using a common model for systems like Si and Ge. A more complex ${C}_{\mathsf {it}}$ model is also implemented for III–Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density ( ${D}_{\mathsf {it}}$ ).

The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces.

Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher C(max) hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated to be effective on the (110) surface for producing low D(it) high C(ox) MOSCAPs. Including TMA in the pre-ALD surface clean resulted in reduction of the magnitude of the interface state capacitance. The XPS studies show the role of atomic H pre-pulsing is to remove both carbon and oxygen while STM shows the role of TMA pre-pulsing is to eliminate H induced etching. Devices fabricated at 120 °C and 300 °C were compared.

Electrical conductivity and dielectric measurements of CoMTPP

Results of X-ray diffraction patterns (XRD) show that the powder of 5,10, 15,20-Tetrakis(4-methoxyphenyl)-21H,23H-porphine cobalt(II) (CoMTPP) has polycrystalline nature with triclinic structure. Miller's indices, (hkl), values for each diffraction peak in XRD spectrum are calculated. The electrical conductivity and dielectric properties of bulk CoMTPP have been investigated in the frequency range 42 Hz–5 MHz and in the temperature range 298–413 K. The frequency dependence of electrical conductivity, σ (ω, Τ), follows the Jonscher's universal dynamic law. The obtained results have been discussed in terms of the correlated barrier hopping (CBH) model, which is well adapted to CoMTPP semiconductor material. Complex impedance data are obtained at different frequency and temperature. The best fitting for the Cole–Cole plots can be represented by an equivalent circuit element composed of RQC. The conductivity in the direct regime, σdc, is described by the variable range hopping (VRH). The values of dielectric constant, ɛ′ (ω), and dielectric loss, ɛ″ (ω), are found to be decrease with increasing frequency due to the interface states capacitance.

Impact of Semiconductor and Interface-State Capacitance on Metal/High-k/GaAs Capacitance–Voltage Characteristics

The frequency dispersion of the maximum capacitance of GaAs metal-oxide-semiconductor (MOS) capacitors is studied. The frequency dispersion behavior observed in the capacitance-voltage characteristics of GaAs MOS capacitors is a result of low semiconductor capacitance and an interface-state capacitance that varies with frequency. The traditional approach for calculating interface-state capacitance does not result in frequency dispersion of the maximum capacitance. An interface-state capacitance model based on an extremely high number of interface states in a thin disordered interfacial region is presented to explain the frequency dispersion behavior. The model shows an excellent match with the experimental results. The model also suggests that maximum capacitance values in low-frequency capacitance-voltage characteristics may be determined by the capacitance associated with the interface traps rather than the semiconductor charge and does not necessarily indicate the presence of free carriers.

Characterization of interface states at Au/SnO 2/n-Si (MOS) structures

The purpose of this paper is to characterize the interface states in Au/SnO 2/n-Si (MOS) structures. The characteristic parameters of the interface states are derived from capacitance–voltage ( C– V) and conductance–voltage ( G/ ω– V) measurements as a function of frequency. The C– V and G/ ω– V measurements have been carried out in the frequency range of 1 kHz to 1 MHz at room temperature. At each frequency, the measured capacitance and conductance decrease with increasing frequency due to a continuous distribution of the interface states. The frequency dispersion in capacitance and conductance can be interpreted in terms of the interface state density ( N ss) and series resistance ( R s). Especially at low frequencies, the interface states can follow the ac signal and yield an excess capacitance. Due to a continuous density distribution of interface states, the C and G/ ω values decrease in depletion region with increasing frequencies. At high frequencies, the effect of series resistance on the capacitance is found appreciable due to the interface state capacitance decreasing with increasing frequency. Experimental results show that the locations of interface states between SnO 2/Si and series resistance have a significant effect on electrical characteristics of MOS structures.

Dielectric properties and ac electrical conductivity studies of MIS type Schottky diodes at high temperatures

Dielectric properties and ac electrical conductivity of the Al/SiO 2/p-Si (MIS) Schottky diodes were studied in the frequency and temperature range of 10 kHz–1 MHz and 300–400 K, respectively. Experimental results show that the dielectric constant ( ε′), dielectric loss ( ε″), loss tangent (tan δ), ac electrical conductivity ( σ ac) and the electric modulus were found a strong function of frequency and temperature. The values of the ε′, ε″ and tan δ decrease with increasing frequencies due to the interface states capacitance and a decrease in conductance with increasing frequency. Also, these values increase with increasing temperature. The σ ac is found to increase with increasing frequency and increasing temperature. The variation of conductivity as a function of temperature and frequency reveals non-adiabatic hopping of charge carriers between impurities localized states. In addition, the experimental dielectric data have been analyzed by considering electric modulus formalism.

Transport properties of InAs nanowire field effect transistors: The effects of surface states

It is shown that interface trap states have pronounced effects on carrier transport and parameter extraction from top-gated InAs nanowire field effect transistors (NWFETs). Due to slow surface state charging and discharging, the NWFET characteristics are time dependent with time constants as long as ∼45s. This is also manifested in a time-dependent extrinsic transconductance that severely affects carrier mobility and carrier density determination from conventional three-terminal current-voltage characteristics. Slow gate voltage sweep rates result in charge balance between carrier capture and emission from interface states and lead to reduced hysteresis in the transfer curves. The gate transconductance is thus increased and intrinsic NW transport parameters can be isolated. In the InAs NWFETs, a carrier mobility value of ∼16000cm2∕Vs was obtained from the transfer curves at slow sweep rates, which is significantly higher than ∼1000cm2∕Vs obtained at fast sweep rates. A circuit model that takes into account the reduction in the extrinsic transconductance is used to estimate an interface state capacitance to be ∼2μF∕cm−2, a significant value that can lead to underestimation of carrier mobility.

Influence of surface states on the extraction of transport parameters from InAs nanowire field effect transistors

The capacitive effects of interface trap states in top-gated InAs nanowire field effect transistors and their influence on the experimental extraction of transport parameters are discussed. Time resolved transfer characteristics exhibit transient behavior indicating surface state trapping and detrapping with long characteristic time constants of 45s. Varying gate voltage sweep rate results in a time-dependent extrinsic transconductance; a reduced gate voltage sweep rate leads to a charge neutral interface, reduced interface state capacitance, higher measured transconductance, and minimal hysteresis. These results demonstrate that measurements with a charge neutralized or passivated surface are key to extract intrinsic nanowire transport parameters.

High Electron Mobility InAs Nanowire Field‐Effect Transistors

Single-crystal InAs nanowires (NWs) are synthesized using metal-organic chemical vapor deposition (MOCVD) and fabricated into NW field-effect transistors (NWFETs) on a SiO(2)/n(+)-Si substrate with a global n(+)-Si back-gate and sputtered SiO(x)/Au underlap top-gate. For top-gate NWFETs, we have developed a model that allows accurate estimation of characteristic NW parameters, including carrier field-effect mobility and carrier concentration by taking into account series and leakage resistances, interface state capacitance, and top-gate geometry. Both the back-gate and the top-gate NWFETs exhibit room-temperature field-effect mobility as high as 6580 cm(2) V(-1) s(-1), which is the lower-bound value without interface-capacitance correction, and is the highest mobility reported to date in any semiconductor NW.

The C– V– f and G/ ω– V– f characteristics of Au/SiO 2/n-Si capacitors

Au/SiO 2/n-Si metal–insulator-semiconductor (MOS) structures with thermal growth oxide layer have been fabricated. The frequency dependence of capacitance–voltage ( C– V) and conductance–voltage ( G/ ω– V) characteristics of these structures have been investigated taking into account the effect of the series resistance and interface states. The C– V and G/ ω– V measurements have been carried out in the frequency range of 1 kHz–1 MHz at room temperature. The frequency dispersion in capacitance and conductance can be interpreted in terms of the interface states density ( N ss) and series resistance values ( R s). The interface states can follow the ac signal and yield an excess capacitance especially at low frequencies. The values of measured C and G/ ω decrease in depletion region with increasing frequencies especially in low frequencies due to a continuous density distribution of interface states. The C– V plots exhibit anomalous peaks due to the N ss and R s effect. It has been experimentally found that the peak positions in the C– V plot shift towards positive voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at high frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance ( C m) and conductance ( G m/ ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of interface states between Si/SiO 2 and series resistance have a significant effect on electrical characteristics of MOS structures.

The C– V– f and G/ ω– V– f characteristics of Al/SiO 2/p-Si (MIS) structures

The frequency dependence of capacitance–voltage ( C– V) and conductance–voltage ( G/ ω– V) characteristics of the Al/SiO 2/p-Si metal–insulator–semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance ( R s) and interface states ( N ss) at room temperature. The C– V and G/ ω– V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C– V plots exhibit anomalous peaks due to the N ss and R s effect. It has been experimentally determined that the peak positions in the C– V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance ( C m) and conductance ( G m/ ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N ss and R s have a significant effect on electrical characteristics of MIS structures.

Electrical characterization and process control of cost-effective high-k aluminum oxide gate dielectrics prepared by anodization followed by furnace annealing

A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectrics with equivalent oxide thickness (EOT) down to 14 /spl Aring/. Al/sub 2/O/sub 3/ was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650/spl deg/C in N/sub 2/ ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of k/spl sim/7.5 and leakage current of 2-3 orders of magnitude lower than SiO/sub 2/ are observed. The conduction mechanism in Al/sub 2/O/sub 3/ gate stack is shown to be Fowler-Nordheim (F-N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al/sub 2/O/sub 3/ gate stack/Si-substrate interfacial property. An optimal process control for preparing Al/sub 2/O/sub 3/ gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated.

Interface states capacitance in [formula omitted] Schottky contacts—A modified Schottky Capacitance Spectroscopy method

In this paper, limitations of the Schottky Capacitance Spectroscopy (SCS) method are discussed and modifications of the method for low forward bias and high frequency are proposed. It is shown that simplifications commonly accepted in the SCS method can lead to erroneous conclusions as to the cut-off frequency and hence the interface states parameters. A modified SCS method is used in the interface states capacitance measurements in AuPtTi nGaAs Schottky diodes.

Effect of Doping on the Interface States in Au Schottky Contact to p-In0.21Ga0.79As Grown on GaAs by Metal Organic Vapour Phase Epitaxy

ABSTRACTEpitaxial p-In0.21Gao0.79As/Au Schottky barrier type diodes were fabricated by evaporation of Au on chemically etched surfaces of In0.21Ga0.79As:Zn layers grown on highly doped GaAs substrate by MOVPE. 1 MHz capacitance-voltage (C-V) and Capacitance-frequency (C-f) measurements were performed in the frequency range 1 KHz-1 MHz at room temperature in Au Schottky diodes made on four epitaxial In0.2 Ga0.79As:Zn samples with doping concentrations between 6×1014cm−3 and 4×1017 cm−3. Under forward bias, a large frequency dispersion in the junction capacitance was observed which was attributed to the interface states in thermal equilibrium with the semiconductor. The interface states capacitance extracted from the C-f data was analyzed in terms of Lehovec's theoretical model of interface state continuum with single time constant, and the characteristic parameters of the interface states (energy density (Nss), relaxation time (τ) and hole capture cross-section (σh)) were determined. In the samples with doping concentration in the range 1.5×1017-4.3×1017 cm−3, Nss was about an order of magnitude higher than in the sample having a doping concentration of 5.8×1014 cm−3. Over the interface states energy range 0.40-0.65 eV, Nss decreased exponentially with energy in the highly doped samples and σh increased with energy in all the samples.

Study of extrinsic interface states at the Al/Si interface from capacitance-voltage characteristics

Al/c-Si(n) interfaces have been prepared by depositing Al on silicon washed in ordinary water (conductivity > 40 microsiemens cm -1) after etching. The capacitance-voltage characteristics of such junction devices have been studied for various frequencies. The C-V characteristics explicitly feature the interface state capacitance. The interface state density of ~1010cm-2 located at 0 · 52eV below the conduction band edge has been estimated from the C-V data. The capture cross section for the states has been estimated as ~10-14cm-2.

Frequency and temperature tests for lateral nonuniformities in MIS capacitors

Interface states and lateral nonuniformities produce very similar abnormalities in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> curves of MIS capacitors. Two <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> techniques are presented here to aid in distinguishing between them. The first technique is based on the frequency dependence of the interface-state capacitance and utilizes the resulting frequency dispersion of the "high-frequency" capacitance in the depletion regime, which occurs in a frequency range typically between a few hundred Hz and 1 MHz. The second method utilizes a freeze-in of carriers in the interface states at liquid nitrogen temperature. A sweep of bias from accumulation into deep depletion at low temperature produces a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> characteristic which, when compared with the corresponding ideal characteristic for the same semiconductor doping profile, reveals the presence of lateral nonuniformities. A complementary test is provided by temporary illumination of the deep-depleted structure followed by a sweep of bias from inversion into accumulation. A ledge in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> characteristic reveals the presence of interface states in the central half of the bandgap.