Interconnection Techniques Research Articles

An Evaluation of Gold and Copper Wire Bonds on Shear and Pull Testing

In microelectronic packaging technology wire bonding is a common interconnect technique. The quality and reliability of wire bonds are generally evaluated by ball shear and stitch pull testing. From the load versus time and load versus tool tip displacement plots of the shear test, three regions can be observed. Region I primarily exhibits elastic-plastic deformation occur, while crack nucleate in region II which propagates in region III which finally ends in a catastrophic failure. Fractographs reveal in the case of gold ball bonds shows fracture occurs in Al bond pad metallization close to Au-Al intermetallics. In Cu ball bonds of 1, 2, and 4ml wire sizes also Al bond pad metallization cracks but penetrate deeper into the pad which indirectly shows that the bonding layer is stronger than that of gold ball bonds. Optical microscopic observation of the sheared copper bond surfaces reveal sticking of Al which provides qualitative information of the area of the bond between the ball bond and the bond pad. In thermally aged gold ball bonds, the gold above the intermetallic layer fractures. The energy required to fracture a gold or copper ball bond of 1ml wire size is around 370J∕m2, while an aged gold ball bond consumes about 520J∕m2. Void nucleation and coalescence mechanism of ductile fracture takes place in the ball and stitch bonds, however, silicon particles may be the preferential void nucleation sites in bond pad aluminum metallization failures. To understand the second bond strength, a stitch pull test was conducted and the results showed the neck of the stitched wire cracks thus leaving behind a tail bond on the lead finger.

Lead-free interconnect technique by using variable frequency microwave

A novel lead-free interconnect technique using variable frequency microwave (VFM) was investigated. The lead-free solder interconnection between the component chips and the metal pads through VFM was first demonstrated. Comparison between the microstructures of the lead-free solder joints on Cu and Sn surfaces formed by a conventional thermal reflow process and VFM was conducted. The VFM heating technique successfully created the lead-free solder/Cu and Sn joints through their intermetallic compounds (IMCs), while maintaining the substrate temperature as low as 210°C.

The distributed virtual shared-memory system based on the InfiniBand architecture

Even though there have been strong research activities about distributed virtual shared-memory (DVSM) systems, their architectures have been not widely used in current high-performance computing markets. The reason is that the previously introduced DVSM systems use conventional interconnection technologies like Ethernet, which incurs high execution overhead due to process interruption at data communication for memory consistency. In this paper, we present the DVSM architecture based on the next generation of an interconnection technique, the InfiniBand Architecture (IBA). Because the IBA supports shared-memory programming semantics by means of remote direct-memory access (RDMA) and atomic operations in hardware, we can minimize the communication overhead for memory consistency on the DVSM system. For characterizing multithreaded applications on our IBA-based DVSM system, we examined two different shared-memory programming models, i.e. SPMD and OpenMP benchmarks. We show that our DVSM to use full features of the IBA can improve the performance significantly over the IPoIB-based DVSM system in all benchmarks, and also comparable to the bus-based shared-memory multiprocessor system in some benchmarks.

Embedded magnetics for microprocessor and multichip modules integrated power

A new transformer/inductor technology is introduced which is suitable for integrated power for multichip modules (MCM) and microprocessors. The transformer/inductor is embedded within the ceramic substrate, as are the chips and other components. For core, multipole core structures are employed in order to meet extremely low height requirements. The windings are constructed using high-density interconnect techniques such as laminating dielectric layers and depositing winding metals using sputtering followed by electroplating. Winding patterns are etched using photoresist and wet etching techniques, and multiple vias are used to connect different primary and secondary winding layers. A conformal metal mask is used to laser-drill through (large) holes for the posts of the top part of the core. An experimental 50-W, six-pole embedded transformer is described. It operates at 1.0 MHz with an efficiency approaching 98.7% and has a net height of less than 0.09 in. It provides for extremely tight secondary side circuit layouts with very low and fixed leakage inductance.

Readout of the LHCb pixel hybrid photon detectors

The LHCb experiment will use two Ring-Imaging Cherenkov counters equipped with pixel hybrid photon detectors (HPDs) to measure Cherenkov light generated by high-energy particles traversing a radiative medium. Data from these detectors must provide efficient pattern recognition whilst coping with the environmental demands of LHCb: 25 ns time precision, up to 4% channel occupancy and 1 MHz selective frame readout rate. Dedicated CMOS electronics have been developed to meet the requirements of the HPD, together with special packaging and interconnect techniques which withstand the harsh production processes of the detector. Successful prototypes have been fabricated and tested and results are presented. Large-scale production has started in collaboration with European hi-tech industry and the individual steps in the process are described.

A novel interconnection technique for manufacturing nanowire devices

This paper reviews a novel bridging technique that connects a large number of highly directional metal-catalyzed nanowires between pre-fabricated electrodes and extends the technique to an electrically isolated structure that allows conduction through the nanowires to be measured. Two opposing vertical and electrically isolated semiconductor surfaces are fabricated using coarse optical lithography, along with wet and dry etching. Lateral nanowires are then grown from one surface by metal-catalyst-assisted chemical vapor deposition; nanowires connect to the other vertical surface during growth, forming mechanically robust ‘nanobridges’. By forming the structure on a silicon-on-insulator substrate, electrical isolation is achieved. Electrical measurements indicate that dopant added during nanowire growth is electrically active and of the same magnitude as in planar epitaxial layers.

A Reduction Technique for RLCG Interconnects Using Least Squares Method

In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.

Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors

As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. We present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.

Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.

Control by Interconnection and Energy Shaping of the Timoshenko Beam

In this paper, the dynamical control of a mixed finite and infinite dimensional mechanical system is approached within the framework of port Hamiltonian systems. In particular, a flexible beam, modeled according to the Timoshenko theory and in distributed port Hamiltonian form, with a mass under gravity field connected at a free end, is considered. The control problem is approached by generalization of the concept of structural invariant (Casimir function) to the infinite dimensional case and the so-called control by interconnection technique is extended to the infinite dimensional case. In this way, finite dimensional passive controllers can stabilize distributed parameter systems by shaping their total energy, i.e., by assigning a new minimum in the desired equilibrium configuration that can be reached if a dissipation effect is introduced.

Development of flip-chip bonding technology for (Cd,Zn)Te

We developed a Flip-Chip-Bonding Technology for CdTe and (Cd,Zn)Te. The intention of this work was to choose a suitable chip interconnection technique for the fabrication of X-ray pixel-detectors to fit the material requirements of detector grade CdTe or (Cd,Zn)Te material. The proposed method based on a flexible core process, which permits the use of eutectic PbSn solder alloy or In solder. In particular PbSn solder bumping is attained by an electroplating process through a photo resist mask. A photosensitive polymer acts as passivation layer and solder stop mask on CdTe or (Cd,Zn)Te. The proposed process provides the opportunity to do all process steps in-house.

Optical interconnection using fiber-embedded boards and connection blocks fabricated by a micro-grooving technique for fiber insertion

We fabricated fiber-embedded boards using a micro-grooving technique for optical interconnects. This approach is quite cost effective and fully compatible with conventional PCB processes. U-shaped grooves were formed on FR-4 plates using a 90° V-shaped diamond blade. Polyimide-coated glass fibers were inserted in the grooves followed by a conventional lamination process. The 12 fibers embedded in the board showed a good uniformity in their position with a fluctuation below ±8 µm. Optical connection blocks were also fabricated using fiber segments embedded in a grooved silicon wafer piece in order to couple the light between a transmitter/receiver module and a fiber-embedded board. 45° mirrors were formed at the end of the connection blocks by mechanical polishing. An optical link of 2.5 Gb s−1 signals with a high coupling efficiency was demonstrated through the fiber-embedded connection blocks and a board.

Study of swing potential on deep submicron on-chip interconnect

The low energy limit of signal on deep submicron on-chip interconnect is deduced from Shannon's communication theorem considering the influence of noise. Based on this energy limit, the analytic model of minimum swing potential considering transmission line effects is constructed. Applying the analytic model to interconnect in deep submicron technology nodes from 0.18 to 0.05 μm, it is shown that the swing potential with present low-swing technique such as SDVST could be reduced further by 70–95% according to the analysis of this work. Correspondingly, by using the low-swing interconnect technique with the minimum swing potential obtained in this work, the decrement of interconnect dynamic power dissipation can be further decreased by about 10–20% of their original one by using SDVST technique, and that of interconnect propagation delay, by one third. Furthermore, the maximum interconnect length is evaluated with a minimum swing potential value in interconnect design. All the results are valuable for interconnect performance optimization, such as repeater insertion in deep submicron circuits. As an application, the design of low swing potential interconnect with interface circuit is introduced.

Advanced processing techniques for through-wafer interconnects

The fabrication of interconnects used in future microelectronic devices and for three-dimensional (3D) integration of these components will require advanced integrated circuit (IC) processing techniques. One attractive approach to providing increased connectivity is to use through-wafer interconnects. The primary challenge to implementing 3D stacking is the formation of these high aspect ratio interconnects with a sufficiently small diameter and, consequently, with sufficiently high density. Processing techniques to fabricate through-wafer interconnects in silicon for applications that require multichip stacking or contacts on both sides of the wafer will be described. The techniques used for fabrication of the vertical interconnects are compatible with complementary metal–oxide–semiconductor technology and executed within the thermal budget of a completed IC. The processing techniques to be described include: deep silicon etching (DRIE) to form small diameter vias, insulator lining, adhesion/barrier layer deposition, seed layer deposition, copper electroplating, and chemical mechanical planarization of copper. Through-wafer copper interconnects have been formed with via diameters of 50–100 μm on 4 and 6 in. silicon wafers containing no active devices and at temperatures no greater than 200 °C.

Evaluation of advanced chemical mechanical planarization techniques for copper damascene interconnect

According to rapid development of CMP technology, the difference of polishing methods would be applied for copper damascene interconnect. These methods include conventional rotary, linear, oscillation platform. The advantages of these platform would highlighted in uniformity control, stability of removal rate, planarization efficiency, throughput promotion, lower cost of ownership, even dishing and erosion effect integrated with slurry. This paper presented our experience to compare the uniformity, removal rate and planarization efficiency of Cu-CMP between various polishing platforms. In convection, the rotary or oscillation platform would be usually applied in oxide and tungsten CMP, due to the robust air-back carrier and rigid platen to polish the wafer, which performs the good reliability on wafer-to-wafer thickness and endpoint detection. However, the linear polisher is made of the air-bearing moving belt and self-rotated carrier and would provide the wider uniformity and planarization control window than others. In addition, the simulation model would explain the difference from mechanic design and wafer moving paths between various polishing techniques. Hence, the trade-off advantage and application between various platforms would be compensated and integrated with slurry, conditioners and coming thickness profile from copper plating. It can achieve the optimization of Cu-CMP process.

Evaluation of advanced chemical mechanical planarization techniques for copper damascene interconnect

According to rapid development of CMP technology, the difference of polishing methods would be applied for copper damascene interconnect. These methods include conventional rotary, linear, oscillation platform. The advantages of these platform would highlighted in uniformity control, stability of removal rate, planarization efficiency, throughput promotion, lower cost of ownership, even dishing and erosion effect integrated with slurry. This paper presented our experience to compare the uniformity, removal rate and planarization efficiency of Cu-CMP between various polishing platforms. In convection, the rotary or oscillation platform would be usually applied in oxide and tungsten CMP, due to the robust air-back carrier and rigid platen to polish the wafer, which performs the good reliability on wafer-to-wafer thickness and endpoint detection. However, the linear polisher is made of the air-bearing moving belt and self-rotated carrier and would provide the wider uniformity and planarization control window than others. In addition, the simulation model would explain the difference from mechanic design and wafer moving paths between various polishing techniques. Hence, the trade-off advantage and application between various platforms would be compensated and integrated with slurry, conditioners and coming thickness profile from copper plating. It can achieve the optimization of Cu-CMP process.

Fabrication of micronozzles using low-temperature wafer-level bonding with SU-8

This paper describes a method for fabricating micronozzles using low-temperature wafer-level adhesive bonding with SU-8. The influence of different parameters on the bonding of structured wafers has been investigated. The surface energies of bonded wafers are measured to be in the range of 0.42–0.56 J m−2, which are comparable to those of some directly bonded wafers. Converging–diverging nozzle structures with throat widths as small as 3.6 µm are formed in an SU-8 film bonded with another SU-8 intermediate layer to produce sealed micronozzles. A novel interconnection technique is developed to interface and test the micronozzles with a macroscopic fluid delivery system to demonstrate the feasibility of the fabrication process. Leakage test results show that this low-temperature wafer bonding process is a viable MEMS fabrication technique for microfluidic applications.

A transition-encoded dynamic bus technique for high-performance interconnects

This paper describes a transition-encoded dynamic bus technique that enables on-chip interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short-length buses, while obtaining energy savings at aggressive delay targets. On a 180-nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement using this technique.

Novel microfluidic interconnectors for high temperature and pressure applications

Reliable microfluidic interconnectors are one of the basic building blocks of integrated fluidic and chemical reaction systems-on-chip. Though many ideas have been proposed and implemented in the literature for creating different kinds of macro-to-micro fluidic connections, development of integrated on-chip connectors for high temperature and pressure microfluidic applications has not been properly studied. Such connectors will be indispensable in true on-chip chemical processing applications for reactions which require more severe operating conditions than those possible using currently available interconnection techniques. In this paper we present novel microfluidic interconnects that can be used in applications involving operating temperatures of up to 275 °C and pressures in excess of 315 Psi (21.43 atm). The only wetted surfaces in this design are teflon, silicon and pyrex glass, making the design inert to most chemicals. High-pressure leakage, pull-out and high-temperature durability tests conducted on the interconnect show that the connections obtained are superior to those reported in the literature using other techniques. Structural analysis of the interconnect is carried out to illustrate the effect of interconnect geometry on strength and high-pressure performance.

Ultra thin ICs and MEMS elements: techniques for wafer thinning, stress-free separation, assembly and interconnection

Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting.