Interpoly Dielectric Research Articles

Effect of interfacial fluorination on the electrical properties of the inter-poly high- k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al 2O 3) and hafnium oxide (HfO 2) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al 2O 3 and HfO 2 IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO 2 possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al 2O 3 dielectric is more effective to promote the IPD characteristics than fluorination of the HfO 2 dielectric. For future stack-gate flash memory application, the fluorinated Al 2O 3 IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO 2 IPD due to superior insulating properties.

Characteristics of the Fluorinated High-$k$ Inter-Poly Dielectrics

In this letter, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al2O3) and hafnium oxide (HfO2) inter-poly dielectric (IPD) are studied for the first time. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al2O3 and HfO2 IPDs, mainly ascribed to the trap density reduction and the smooth interface. Although HfO2 possesses higher dielectric constant to increase the gate coupling ratio, the results apparently indicate that the fluorine incorporation process is more effective to improve the dielectric characteristics of the Al2 O3 IPD than the HfO2 IPD.

Interface Study of SiO2/ HfO2/SiO2 Stacks Used as InterPoly Dielectric for Future Generations of Embedded Flash Memories

AbstractWe have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO2/HfO2/SiO2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO2/HfO2 interface.

Investigation of Program Saturation in Scaled Interpoly Dielectric Floating-Gate Memory Devices

This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides (ges 4 nm) , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.

A Technique to Extract High-$k$ IPD Stack-Layer Thicknesses From $C$– $V$ Measurements

We propose in this letter a simple technique based on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> measurements which allows the estimating of the thicknesses of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> and high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> layers of interpoly dielectric (IPD) stacks. We apply this technique to IPD Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -based stacks for floating-gate memory applications, finding a good agreement with TEM measurements. In addition, simulation results are provided to demonstrate the correctness of the basic assumption of this technique.

Improvement of Interpoly Dielectric Characteristics by Plasma Nitridation and Oxidation for Future nand Flash Memory

In this letter, plasma nitridation and oxidation on interpoly dielectric (IPD; SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -SiN-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) for cell programming speed and reliabilities are investigated. Nitrided top oxide with N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma shows excellent physical and electrical properties in terms of edge profile on IPD and fast programming voltage. However, plasma nitridation on a floating gate suffers from data retention problems that result from nitridelike residue along the word line. A method to densify and reoxidize bottom oxide with O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma oxidation is proposed for leakage path inhibition and data retention improvement.

Future challenges of flash memory technologies

Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.

Multi-layer high- κ interpoly dielectric for floating gate flash memory devices

We present a systematic simulation and experimental study of tunneling leakage current of the interpoly dielectric (IPD) layer in a floating gate (FG) type flash memory. IPD layers with different structural and material combinations such as HfLaO and 4% Tb-doped HfO 2 were studied. It is shown that compared with a conventional Al 2O 3–HfO 2–Al 2O 3 high–low–high barrier structure, the HfO 2–Al 2O 3–HfO 2 multilayer IPD stack with a low–high–low barrier structure has a lower leakage current due to the longer effective electron tunneling distance. Results also show that multilayer IPD structure has advantage of better thermal stability compared to the single layer IPD. Further work with simulations and experiments results suggest that the presence of a thin interfacial layer between polysilicon FG and IPD can increase the magnitude of leakage current by two or three orders. Nitridation of polysilicon floating gate reduced the leakage current by around two orders of magnitude at a constant equivalent oxide thickness. This is due to the elimination of the interfacial layer between polysilicon and high- κ IPD.

Performance and reliability of HfAlO x-based interpoly dielectrics for floating-gate Flash memory

This paper discusses the performance and reliability of aggressively scaled HfAlO x -based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45 nm non-volatile memory technologies. It is shown that a less than 5 nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3 V at 150 °C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed.

Use of Al 2O 3 as inter-poly dielectric in a production proven 130 nm embedded Flash technology

We have successfully integrated 2 Mb arrays with SiO 2/Al 2O 3 stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al 2O 3 grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high- k IPD. Despite several integration issues, these results demonstrate the high potential of Al 2O 3 IPDs in embedded Flash technologies.

On the Roll-Off of the Activation Energy Plot in High-Temperature Flash Memory Retention Tests and its Impact on the Reliability Assessment

In this letter, we discuss the experimental behavior of high-kappa interpoly dielectrics in floating gate memory devices with respect to the activation energy plot. It is shown that the Arrhenius extrapolation may overestimate the ten-year lifetime predictions. However, a clear correlation between the activation energy plot and the trap levels in the interpoly dielectric can be established, based on theoretical grounds. It is shown that a single-trap level typically follows an 1/T law, while a roll-off of the activation energy plot suggests the existence of various trap levels in the interpoly dielectrics. These findings have practical implications on the high-temperature retention testing methodology of novel nonvolatile memory with high-kappa interpoly dielectrics.

Characteristics of Inter Poly Dielectric (IPD) Prepared by Plasma Oxidation Treatment of LP-CVD SiO2 Film

AbstractTo improve the IPD reliability of NAND flash memory, plasma oxidation was introduced as the post-treatment process of ONO (Oxide/Nitride/Oxide) IPD. The LP-CVD SiO2 modified by plasma oxidation showed the excellent electrical properties. e.g., low leakage current, high breakdown voltage etc. By the analysis of Tof-SIMS and XRR, we could observe the several changes of physical characteristics such as the reduction of impurities (H, N etc.), the increase of oxide density, and the improvement of oxide surface roughness. We found out the appropriate treatment condition to be able to densify oxide layer without the addition of ONO Equivalent Oxide Thickness (EOT). The LP-CVD SiO2 prepared by plasma oxidation was used for the ONO IPD of 50nm NAND flash device and also compared with the conventional LP-CVD SiO2 in the aspect of the IPD reliability.

Impact of the High-Temperature Process Steps on the HfAlO Interpoly Dielectric Stacks for Nonvolatile Memory Applications

AbstractThis work reports on the performance of different Hafmiun aluminate (HfAlOx)-based interpoly dielectrics (IPD) for future sub-45nm nonvolatile memory (NVM) technologies. The impact of the thermal budget during the fabrication process is studied. The good retention and large operating window shown by this material, can be compromised by a high temperature activation anneal (AA) after the gate deposition. The AA step may induce phase segregation of the HfAlOxand outdiffusion of the Hf (Al) towards the floating gate/IPD and IPD/gate interfaces and subsequent formation of Hf (Al) silicates. These findings are supported by the low field leakage analysis, which shows large device to device dispersions. However, the effect of the spike anneal can be minimized if the HfAlOxlayer is crystallized prior to the AA. Devices with polysilicon or TiN gate are compared in terms of memory performance and reliability.

Investigation of hafnium-aluminate alloys in view of integration as interpoly dielectrics of future Flash memories

In this paper, we evaluate the potentialities of hafnium-aluminates (HfAlO) materials as possible candidates for the interpoly dielectrics of future Flash memory devices. HfAlO layers of different thicknesses and compositions are integrated in single-layers and in Oxide/HfAlO/Oxide (OHO) triple-layer stacks, and analyzed in terms of coupling and insulating capabilities. We demonstrate that increasing the Hf content allows reducing the leakage current at high voltages but it results in a stronger leakage current at low voltages. We also show that once normalized in electric fields, the leakage current characteristics are independent of the high-k thickness. The electron conduction modes in these materials, at different temperatures, are also investigated. The activation energy increases with the Hf concentration in the HfAlO alloy, resulting in a higher leakage current at elevated temperatures. Finally, it is demonstrated that the conduction in triple-layer stacks is limited by a Poole–Frenkel conduction in the high-k layers, while the trap contribution in the case of single-layers becomes dominant when the HfAlO layer is thicker than 8 nm.

Thickness Scaling and Reliability Comparison for the Inter-Poly High- $\kappa$ Dielectrics

In this letter, the inter-poly dielectric (IPD) thickness, scaling, and reliability characteristics of Al2O3 and HfO2 IPDs are studied, which are then compared with conventional oxide/nitride/oxide (ONO) IPD. Regardless of deposition tools, drastic leakage current reduction and reliability improvement have been demonstrated by replacing ONO IPD with high-permittivity (high-kappa) IPDs, which is suitable for mass production applications in the future. Moreover, metal-organic chemical vapor deposition (MOCVD) can be used to further promote dielectric reliability when compared to reactive-sputtering deposition. By using the MOCVD, the charge-to-breakdown (QBD) can be significantly improved, in addition to enhanced breakdown voltage and effective breakdown field. Our results clearly demonstrate that high- IPD, particularly deposited by MOCVD, possesses great potential for next-generation stacked-gate Flash memories.

High-k Materials for Tunnel Barrier Engineering in Floating-Gate Flash Memories

Replacing the tunnel oxide or interpoly dielectric of a floating gate Flash memory cell by an engineered tunneling barrier allows lowering the voltage necessary to program or erase the memory cell. We use dual layer dielectric stacks with different dielectric constant, allowing a high tunneling current at relatively low applied voltage while providing good data retention. Stacks consisting of SiO2 with HfO2 or Al2O3 have been studied in single poly memory cells, demonstrating both low voltage programming by tunneling and 10 years of data retention. These stacks have also been integrated as interpoly dielectric (IPD) in a 0.18μm HIMOSTM process for low voltage erasing by tunneling through the IPD.

High-k Materials in Flash Memories

The scaling down of Flash memories can be pursued using the conventional stacked gate architecture only with major changes of the active dielectrics, mainly the inter-poly dielectric (IPD).The required 4-6 nm EOT thickness for the IPD cannot be achieved by the conventional ONO (Oxide-Nitride-Oxide) technology which starts failing in the 10-12 nm range in terms of charge retention properties. Therefore high-k materials are currently investigated for IPD formation in future Flash memories. It is worth noticing that the requirements for IPD are very different from those of the gate dielectrics used in logics. Alumina and alumina based materials (like hafnium aluminates) are among the possible candidates. Promising and tunable electrical and structural properties are achieved for these materials by varying the high-k stack chemical compositions and post- deposition thermal treatments. Different material combinations have been selected as potential solutions for the replacement of the conventional ONO (Oxide-Nitride-Oxide) stack.

Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities

We review the main issues in scaling down the interpoly dielectric (IPD) for future floating gate Flash memory technology generations. The equivalent oxide thickness (EOT) of the IPD must reach the sub-10 nm range to enable lowering of the operating voltages and further scale device feature sizes. Additionally, the loss of control gate wrap around the floating gate for high density memories as device dimensions scale down will require a drastic reduction (up to 60%) in IPD EOT to maintain the same capacitive coupling. As the scalability of the conventional oxide-nitride-oxide (ONO) IPD’s is limited, we propose new solutions that exploit the opportunities offered by the high- κ dielectrics. Their effectiveness increases when midgap and p-type metals are considered, instead of the conventional polysilicon control gate. The optimal approach depends on the most critical requirement that the IPD has to fulfill, which in turn is application or device-structure dependent. The nonideal nature of the dielectric materials, however, may severely reduce the design window, calling for a sustained effort to improve their electrical properties by process optimization.

Characteristics of the Inter-Poly Al2O3 Dielectrics on NH3-Nitrided Bottom Poly-Si for Next-Generation Flash Memories

The effects of surface NH3 nitridation of the bottom poly-Si film, and post-deposition annealing (PDA) temperature, on the electrical properties and reliability characteristics of aluminum oxide (Al2O3) inter-poly capacitors, were evaluated in this study. The polarity-dependent dielectric properties of Al2O3 inter-poly dielectrics (IPDs) were strongly affected by both surface nitridation and the annealing temperature. For positive gate bias, IPDs with NH3 surface nitridation significantly suppressed the formation of an additional layer with a lower dielectric constant, during the post-annealing process, and obtained a smoother interface, compared to those without nitridation treatment. Furthermore, the presence of a thin Si–N layer made the PDA more effective in eliminating the traps existing in the as-deposited films, and improved dielectric characteristics, under negative polarity. As a result, the smoother interface and smaller electron trapping rate contributed to the drastically reduced leakage current, enhanced breakdown field, and charge to breakdown (Qbd) of the Al2O3 inter-poly capacitors with surface NH3 nitridation. Moreover, the electrical properties of Al2O3 IPD were heavily dependent upon the PDA temperature. The sample exhibited optimal quality in terms of leakage current, electron trapping rate and Qbd when annealed at 900°C. X-ray photoelectron spectroscopy and Auger electron spectroscopy analyses have shown that this occurrence arises from various compositions, under different annealing conditions and excess oxygen, which can act as an electron trapping center, playing an important role in determining IPD electrical properties.

Empirical model of data retention degradation in stacked-gate flash EEPROM cells with new interpoly dielectric of an Oxide–Nitride–Oxide–Nitride (ONON) layer

We have studied the reliability problems in the degradation of the data retention characteristics of the stacked-gate flash EEPROM devices with the new interpoly dielectric of an Oxide–Nitride–Oxide–Nitride (ONON) layer instead of a conventional Oxide–Nitride–Oxide (ONO) layer. Based on the experimental results of cell threshold voltage shifts measured as a function of bake time at various temperatures by the high-temperature accelerated test, an empirical model equation has been developed and evaluated, which explains the dominant mechanisms for the spontaneous electron leakage through the interpoly dielectric. Through the threshold voltage and temperature dependency of cell threshold voltage shift rate, the model clearly shows that cell threshold voltage shift during the baking test is caused dominantly by the electron leakage mechanism due to the thermally-activated direct-tunneling which electrons tunnel finally through the thin top oxide of the ONON layer to the control gate after detrapping the internitride trap-sites near the interface between the internitride and top oxide by the thermionic emission mechanism. The simulation results using the model equation were quite consistent with the measurement data at all the tested temperatures and times.