Integrated Circuit System Research Articles

Analysis of Integrated Circuit System s by An Innovative Wavelet-Based Scattering Matrix Approach

This paper proposes the use of scattering parameters (S-parameters) in the wavelet domain for the analysis of coupled multiconductor transmission lines, high-speed integrated circuits, and interconnects. S-parameters-based computing techniques are widely used in the analysis of networks characterized by a large number of integrated devices and interconnects. The theoretical and practical definition of the wavelet-based S matrix is shown, and then some numerical examples of its use and potential in the analysis of systems with linear and nonlinear terminations is shown and compared with other numerical techniques. The computational costs and the memory requirements of the wavelet representation of scattering matrix are also addressed

Hardware compilation of application-specific memory-access interconnect

A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.

Design of high-Q microcavities for proposed two-dimensional electrically pumped photonic crystal lasers

Electrically pumped photonic crystal lasers are of practical importance for future integrated photonic circuit systems. This paper proposes a methodology for achieving high quality (Q) factor photonic crystal defect cavities that allow current injection into their active regions. It is shown that by combining certain high Q-factor photonic crystal cavity designs with the technique of wet oxidation of (Al,Ga)As layers, Q factors of up to /spl sim/10/sup 4/ can be obtained within the scope of existing semiconductor planar process technology. The proposed device structures can be optimized through use of finite-difference time-domain methods to obtain optimal separation of the high refractive index substrate from the active core; furthermore, the effects of the top ohmic contact layer, the top and bottom cladding layers of the structure, and the current injection opening can be taken into account to achieve an optimal Q factor in electrically pumped lasers.

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.

Application of Metal-Ferroelectric-Insulator-Semiconductor Field-Effect Transistors (MFISFETs) in Non-Volatile Logic Integrated Circuits

New concept of non-volatile logic integrated circuit system using MFISFETs is proposed first in this paper, in which information in CMOS digital circuits can be protected from accidental or planned power outages and restored after the power recovers. The basic operation of the proposed system has been ascertained using Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. A HSPICE macro model of Metal- Ferroelectric-Insulator-Semiconductor Field-Effect Transistors (MFISFETs) using Schmitt trigger model is created and applied to the circuit simulation to test its validity. The states of logic nodes in the volatile CMOS digital circuits can be stored onto corresponding MFISFETs when power shuts off abruptly and be restored immediately when power-failure recovers, thus the whole system continues to work as if no power outrage had happened. As a result, the nonvolatile logic function is realized with MFISFETs and the feasibility of application in VLSI digital systems is demonstrated.

Special Issue on Vision and Mechatronics

The amount of information human beings obtain from the external world through their visual senses exceeds 80% of the total amount of information they take in. Robots and similar automatons must thus be provided with visual functions equivalent to those of human beings, enabling them to grasp external conditions accurately and to move appropriately based on such conditions. Computer and machine vision systems technologically and practically realize such visual functions, and studies of these vision systems have drawn attention and research since the 1970s. Studies on the human and other biological visual systems have progressed steadily under the stimulus of rapid advances in the brai sciences field. Such studies have brought to light new types of useful information related to biological vision systems and such information has been used to promote studies of artificial visual senses. In separate developments based on the progress of integrated circuit systems, visual sensors imitating the sensing of the human retina and the eyes of insects and animals have been developed and efforts made to apply such sensors to a variety of control systems. Human beings fuse information obtained through the visual and other senses with information collected by interacting positively with the external world to form in the brain necessary images (models) related to the external world. Based on such images and models, human beings make decisions and plan for appropriate action to take under specific circumstances. In such cases, the human senses, including the visual sense, interact mutually rather than independently. When a visual stimulus differing from ordinary stimuli is perceived, the effect of such a stimulus is recognized both by the sensory organs and sometimes by the motor organs. Human beings fuse information obtained through the visual and other senses with information collected by interacting positively with the external world to form in the brain necessary images (models) related to the external world. Based on such images and models, human beings make decisions and plan for appropriate action to take under specific circumstances. In such cases, the human senses, including the visual sense, interact mutually rather than independently. When a visual stimulus differing from ordinary stimuli is perceived, the effect of such a stimulus is recognized both by the sensory organs and sometimes by the motor organs. In the present natural environment, where numerous conditions artificially produced by numerous automation and visual systems are present simultaneously, it becomes important to study the interference and interaction among the sensory, motor, and physiological organs. The human visual function gradually develops with maturation and declines with age, following a downward curve with the years. Simple deviations in the focusing range due to myopia or hyperopia can be corrected almost completely using ordinary glasses for near-sightedness or far-sightedness. Stenosis in the focusing range, however, caused by aging and a decline in the elasticity of the eye lens cannot be corrected by the use of ordinary glasses. Such correction requires either the use of 2 types of glasses, i.e., those for near-sightedness and those for far-sightedness, alternately depending on the distance between the glasses user and the object viewed. Bifocals may also be used. The use of double lenses, however, may cause problems for the user, who must change from one pair of glasses to the other and vice versa. Biofocal lenses present problems related to the need to shift the gaze unnaturally, the presence of an unnaturally deformed whole-vision field, and the undesirable occurrence of sensations such as nausea required in attempts to adjust to changed visual fields. Take the case of fine soldering work at very close range and parts handling done at a medium range simultaneously, for example. This presents both far-sighted and near-sighted personnel with difficulties in the use of glasses. Symptoms of hyperopia generally begin to appear in those aged 40 to 45 years old. With society rapidly aging and the number of children – successors to the aging – the working population is also aging, making it vital from a social viewpoint to mechatronically solve the many problems related to hyperopia and other vision-related developments. It is with great pleasure that we present a number of articles in this special edition that should prove both informative and interesting to researchers in the fields of robotic engineering and mechatronics. These articles offer new insights into studies on welfare and human engineering and are sure to make important contributions to the progress of related R&amp;D.

A preamplifier-shaper-stretcher integrated circuit system for use with germanium strip detectors

A 16-channel integrated circuit readout electronics chip is being developed for use with a germanium strip detector. Such a system will provide superior energy resolution with 2-dimensional imaging in a single instrument that can be used for X-ray imaging and nuclear line gamma-ray spectroscopy. As part of the total ASIC development, prototype ICs of a typical channel have been designed, fabricated and tested. These integrated circuits include a low-noise, variable gain, preamplifier circuit that can detect both positive and negative going input charges, a 4-pole pulse shaper with variable peaking times and a stretcher circuit that can do a peak detect and hold for the different peaking times. The integrated circuits are fabricated in a 1.2 micron n-well CMOS process. The noise performance for this system was measured to be 185erms +14e/pF for a 2 /spl mu/s peaking time and gain at /spl sim/200 mV/fC. Linearity measurements in both inverting and non-inverting modes of operation were approximately +/-1%. Peaking times from 0.5 microseconds to 8 microseconds and gain adjustments to get up to 400 mV/fC per channel were done through digital switching.

Fabless-foundry partnership: models and analysis of coordination issues

The fabless-foundry partnership for integrated circuit (IC) manufacturing business is expected to grow from 12% in 1995 to approximately 17% (i.e., $45B) of the total IC market in 2000. The growth of this market will be even more significant for subquarter micron technologies-whose growth is driven by the multimedia industry. The customer base will extend beyond traditional fabless IC companies into vertically integrated IC manufacturers and system vendors. Given the rate of growth and the high technology profile of products, substantial investments in capital, technology, and skilled workforce have to be dedicated and managed effectively for ensuring a successful partnership. In this paper, we outline the potential coordination problems that may arise in such partnerships, and propose a framework for analyzing issues related to yield information sharing and yield improvement. Our analysis indicates that fabless-foundry contracts that are based on a fixed number of good dies, and better yield information are more profitable.

DNA biochip using a phototransistor integrated circuit.

This work describes the development of an integrated biosensor based on phototransistor integrated circuits (IC) for use in medical detection, DNA diagnostics, and gene mapping. The evaluation of various system components developed for an integrated biosensor microchip is discussed. Methods to develop a microarray of DNA probes on nitrocellulose substrate are discussed. The biochip device has sensors, amplifiers, discriminators, and logic circuitry on board. Integration of light-emitting diodes into the device is also possible. To achieve improved sensitivity, we have designed an IC system having each phototransistor sensing element composed of 220 phototransistor cells connected in parallel. Measurements of fluorescent-labeled DNA probe microarrays and hybridization experiments with a sequence-specific DNA probe for the human immunodeficiency virus 1 system on nitrocellulose substrates illustrate the usefulness and potential of the DNA biochip.

In application specific integrated circuit and data acquisition system for digital X-ray imaging

We have developed an Application Specific Integrated Circuit (ASIC) and data acquisition system for digital X-ray imaging. The chip consists of 16 parallel channels, each containing preamplifier, shaper, comparator and a 16 bit counter. We have demonstrated noiseless single-photon counting over a threshold of 7.2 keV using Silicon detectors and are presently capable of maximum counting rates of 2 MHz per channel. The ASIC is controlled by a personal computer through a commercial PCI card, which is also used for data acquisition. The content of the 16 bit counters are loaded into a shift register and transferred to the PC at any time at a rate of 20 MHz. The system is non-complicated, low cost and high performance and is optimised for digital X-ray imaging applications.

An application specific integrated circuit and data acquisition system for digital X-ray imaging

An application specific integrated circuit and data acquisition system for digital X-ray imaging

Extraction of the capacitance matrix of multiconductor interconnection lines for high-speed IC system design

A simplified and very effective method for the extraction of the capacitance matrix of multiconductor interconnection lines for high-speed integrated circuit (IC) system design is described in this paper. Because of the combination of the approximate spatial domain Green's function of multilayered dielectric media and the three physically meaningful charge basis functions per conductor edge, preprocessing can take place. Thus, the capacitance matrix can then be quickly computed with high accuracy. Examples show that this method is very efficient and accurate for circuit parameter extraction of high-speed IC interconnect structures.

Transmission loss of thick‐film conductor lines at microwave frequency

AbstractIn the hybrid integrated circuit systems which process the RF signal for communications, the transmission loss tends to increase as the frequency is increased, which is a significant problem in the circuit design. The authors have considered thick‐film conductors as conductor materials for the circuit because the thick film is of relatively low cost and can be mass produced. The transmission loss of the RF signal in such a circuit was evaluated experimentally up to 20 GHz.It was found that high‐purity alumina (99.5 percent) is suitable as ceramic substrate material, the transmission loss is too large to be practical in the Ag/Pd conductor system and the transmission losses are not very different and are in the practical range for Au, Ag, Ag/Pt, and Cu conductors. Contrary to the general belief, it was found that the transmission loss can be reduced if the surface of the ceramic substrate is made rough. In order to find the reason, the fine structures of the cross section of the thick‐film conductor was investigated.

Wave spreading evaluation of interconnect systems

This paper derives general multiport interconnect constraints and presents a new approach, wave spreading evaluation (WSE), which uses S-parameter based network techniques to analyze coupled, multiconductor interconnect systems for high speed analog and digital integrated circuits. WSE is based on the spreading process of voltage waves with initial spreading waves created by the sources. The spreading process is independent of input sources, and every step of wave spreading meets the constrains of KCL and KVL. The continual spreading of voltage waves will create accurate results. Since the spreading voltage waves is the process of energy attenuation, the WSE method is always convergent for passive networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An efficient method for computing the capacitance matrix of multiconductor interconnects in very high-speed integrated circuit systems

A new method for computing the capacitance matrix of multiconductor interconnects with finite metallization thickness is developed. Converting the vertical wall of the rectangular conductors into the equivalent horizontal strips allows the Green's function in the spectral domain and the FFT algorithm to be used, which makes the method more effective for computing capacitance matrix of the interconnects.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

OPTIMAL BURN-IN SIMULATION ON HIGHLY INTEGRATED CIRCUIT SYSTEMS

Bum-in, a screening technique to improve product reliability, is especially useful for highly integrated circuit systems. But, in most applications, the resulting systems reliability after burn-in is worse than what has been forecasted, because of “incompatibility” not only among components but also among different subsystems and at the system level. To deal with this phenomenon, we present a simulation method to compensate for the lack of field data. Also, a stress-strength model is implemented using weighted factors and a model based on nonlinear programming theory is designed to find the optimal burn-in policy that satisfies the reliability requirement and cost restriction. The program presented here can serve as an “IC Information Query System” for system designers to consider at the design stage.

4884122 Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer

The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Report: Computer-Aided Engineering and Design for Interconnection Technology

The vertical integration of the design and manufacturing elements of AT&T provides the right environment for developing and using an end-to-end computer-aided design process. We have applied this process to the design of the complete hierarchy of interconnection levels <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> — the integrated circuit (IC) package, circuit pack, backplane, multibackplane unit, frame, and system. Computer aids are available for the initial design phases (computer-aided engineering, or CAE) and the follow-on, detailed design phases and interfaces to manufacturing (computer-aided design, including computer-aided test design, or CAD.) The computer-aided design process has been in use throughout the AT&T R&D community for many years, <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and it is steadily enhanced to increase its benefits.

Silicon compilation: The future is now: Silicon compilers liberate the integrated circuit design process

Agreat deal of interest has recently been generated about a new integrated circuit (IC) design methodology called silicon compilation. Silicon compilation allows IC designers and system experts to quickly develop sure-fire, sophisticated, application-specific ICs with silicon efficiencies approaching those of handcrafted ICs.

Bonding wire discharges in integrated circuit packages

Electrostatic discharge damage to semiconductor devices may occur as a result unwanted charge entering the input circuity. Various input protection circuits offer some degree of protection from such occurences. Another source of discharge damage, which has not been widely reported, is that from breakdown of corona discharging between the bonding wires and earthed track which surrounds the edge of the circuit wafer. Such discharges have been experimentally recorded, and using Townsend sparking criteria, analysis of results shows that such breakdown discharges are possible within the confines of the integrated circuit system.