Integrated Circuit Structures Research Articles

Digital Etching of Molybdenum Interconnects Using Plasma Oxidation

AbstractMolybdenum (Mo) has a high potential of becoming the material of choice for sub‐10 nm scale metal structures in future integrated circuits (ICs). Manufacturing at this scale requires exceptional precision and consistency, so many metal processing techniques must be reconsidered. In particular, present direct wet chemical etching methods produce anisotropic etching profiles with significant surface roughness, which can be detrimental to device performance. Here, it is shown that polycrystalline Mo nanowires can be etched uniformly using a cyclic two‐step “digital” method: the metal surface is first oxidized with isotropic oxygen plasma to form a layer of MoO3, which is then selectively removed using either wet chemical or dry isotropic plasma etching. These two steps are repeated in cycles until the intended metal recess is achieved. High uniformity of plasma oxidation defines the etching uniformity, and small metal recess per cycle (typically 1–2 nm) provides precise control over the etching depth. This method can replace wet etching where high etching precision is needed, enabling the reliable manufacturing of nanoscale metal interconnects.

Power stabilization of a terahertz-frequency quantum-cascade laser using a photonic-integrated modulator

We demonstrate a technique to stabilize the emission from a 3.4-THz quantum-cascade laser against power drifts, using a recently developed photonic integrated circuit (PIC) structure formed by coupling a racetrack resonator with a ridge waveguide. This structure enables a dynamic power-control range of ±15% and locking over >600 s using a proportional–integral control loop. The resonator yields a 50% weaker perturbation to the laser emission frequency when compared with direct laser modulation, and hence offers the prospect of simultaneous, quasi-independent control of power and frequency. Progress towards integrating the PIC with a precision micromachined rectangular metallic waveguide module has also been demonstrated, with power modulation of the principal laser emission line being observed during pulsed operation.

ФОТОННА ІНТЕГРАЛЬНА СХЕМА ТА ЇЇ КАЛІБРУВАННЯ

The article proposes a new structure of a photonic integrated circuit for multiplying vector signals by a matrix. The architecture and principles of operation of modern photonic integrated circuits according to the given classification are briefly described. The proposed system consists of three layers, which includes a radiating, receiving and intermediate block with apertures. The connection of the photonic integrated circuit to the necessary electrical circuit for the investigation of the output signals of the photonic integrated circuit is described. With the help of the electrical circuit, we can monitor and control the input signals on each waveguide of the radiating unit, and track the change of the output signals that have passed through the system and fixed at the output of each waveguide. In the course of the study, we develop graphs of the levels of input and output signals of the system. With the help of which we represent the system errors and the change of signals, which makes it possible to calibrate the system. Calibration of the photonic integrated circuit is carried out by calibrating all electrical elements of the radiation and the receiving unit. In the emitting unit, it is necessary to select the same LEDs according to their characteristics, and with the help of variable resistors, which are connected to each pair of LEDs, calibrate the LED to the same brightness. We control the uniformity of brightness with the help of an IR camera. To calibrate the receiving unit, we fix the shadow noise and enter the reference coefficients for each receiver. After all the units were configured, the system was tested. A block with a specific aperture location was created, and the output signal was removed. Based on the results of the study, we proved that the system calibration is correct and that the system is operational.

Demonstration of a terahertz integrated planar network synthesis filter

At terahertz (THz) frequencies, there are few experimental works that demonstrate the viability of all-pole network synthesis filters to obtain desired frequency characteristics (i.e., Chebyshev, Butterworth, Bessel, etc.) using planar waveguides. This capability has been proven with non-planar waveguides, but has yet to be demonstrated using planar waveguides, which are desirable due to their integration capabilities similar to printed circuit board or monolithic microwave integrated circuit structures. In this paper, we use network synthesis methods from microwave engineering to fabricate three integrated planar low-pass filters for THz applications that have the same cut-off frequency (f c = 0.8 THz) but different orders (N = 3, 4, 5). We measure their response to a THz-bandwidth excitation pulse and find that the experimental results exhibit increasing roll-off rates with increasing filter order without incurring significant pulse distortion, which is aligned with theory.

Modeling of 1300 nm hybrid III-V/silicon lasers

In this study, the modeling of a III–V-Si hybrid semiconductor laser with an InGaAsP 80 nm thick active layer at a wavelength of 1300 nm was carried out using the LaserMOD commercial software program. The mesh, gain, optical output power, optical spectrum, transient response, and near-field and far-field of the laser designed as a result of the simulations were analyzed. It was observed that the light generated in the multi quantum well (MQW) layer can be successfully transferred to the Si waveguide, allowing for light transfer from one point to another in the photonic integrated circuit (PIC) structure. From the L-I curve of the hybrid laser, the threshold current and spectral width were found to be 5 mA and 13 nm, respectively. These results were compared with those of the InGaAsP/InP laser which had a threshold current of 30 mA and spectral width of 36 nm. This demonstrates that the hybrid laser outperforms the InGaAsP diode laser by having a significantly lower threshold current and better spectral coherence. The material gain peaks and the center wavelength of the optical spectrum were obtained around 1305 nm (0.96 eV), which is consistent with the design target of the laser. Additionally, in the transient response of the hybrid laser, it was observed that the oscillations that occur at the rising and falling edges of the light output were damped after approximately 500 ps. Finally, near-field and far-field results demonstrate that a single mode operation was achieved from the hybrid laser.

ОБЗОР ЛАЗЕРНЫХ СКАНИРУЮЩИХ МЕТОДОВ ИССЛЕДОВАНИЙ МИКРОЭЛЕКТРОННЫХ ПОЛУПРОВОДНИКОВЫХ СТРУКТУР

The development and widespread of high-tech microelectronic products impose increased requirements on the quality and reliability of microcircuits. The most effective methods for reliability improvement of electronic systems include diagnostic non-destructive testing (NDT) methods and selective destructive testing in special cases. Studies using visual inspection and electrical testing, consisting of functional and parametric testing, do not provide enough information to detect latent defects (for example, macro-defects in SiO 2 layers in CMOS chips) and to detect fakes and counterfeits. A fake integrated circuit (IC) may contain an undeclared malicious modification of the circuit, called hardware bugs. The common ICs studying tools are systems based on microfocus X-ray sources, scanning acoustic microscopes, optical and scanning electron microscopes, and X-ray fluorescence spectroscopes. Products destruction avoidance is a fundamental point, for example, for the technological process control in crystal manufacturing. Investigation of ICs using a light microscope is one of the most accessible and widespread method of microchip NDT. Semiconductor ICs structure scanning from the side of the device layer is limited by the shielding effect of metallization, since the metal is opaque for light. This limitation can be overcome by an alternative approach to microchip scanning based on irradiating the IC from the side of the substrate with laser sources in the near-IR range. This paper provides a brief overview of the major methods used in laser scanning microscopy to analyze the structures, responses, and features of the operating modes of semiconductor circuits. The main advantages and limitations in the use of optical methods are described, as well as what information about the product can be obtained as a result of laser scanning.

Fully connected aperture array design of the segmented planar imaging system

Compared with the traditional imaging systems, segmented planar imaging technology has the advantages of low mess, small size, and low power in the same resolution situation. To obtain relatively complete frequency domain coverage, the lenslet array requires a large number of lenslets, and the photonic integrated circuit board requires a large number of optical devices, which limits the application and development of the segmented planar imaging technology. In this paper, we introduce a novel, to the best of our knowledge, design of the photonic integrated circuit to ensure that each lenslet in the lenslet array can form a baseline with any other lenslets. This breaks the barrier between segmented planar imaging technology and the traditional synthetic aperture, giving segmented planar imaging technology a sufficient number of frequency domain samples and a concise photonic integrated circuit structure.

Improving Liquid Film Thickness Uniformity of Semiconductor Etching Equipment Using Flow Field Visualization and CFD Simulation

With the rapid development of semiconductor-based products, semiconductor and integrated circuit (IC) design industries have become indicators of global technological advance in this field. As IC structure becomes smaller and smaller, improved process technology and equipment are necessary to maintain and improve wafer yield rates and quality. Among them, the etching technology in the process has a close relationship with the size of IC structure. According to extensive research and analyses put forward by predecessors, the etching process and methods that affect the yield rates and quality of wafers have been well characterized. This study investigates the spray etching method of the single nozzle and double nozzle. Using computational fluid dynamics software developed by Ansys Fluent, the fluid is injected from the center as the starting point at the same flow rate and speed, and according to 2, 4, and 8 seconds of a different cycle and nozzle forms, moving back and forth to supply liquid on the surface of the 300 mm disc. It is assumed that fluid properties do not change with temperature. Additionally, the chemical reaction and thermal reaction of the etching process are not considered. Changes in the surface flow field resulting from different nozzles and cycle conditions are observed. This study involved setting up a set of flow field visualization systems, replacing the etching liquid with colored water, using a digital camera to capture the relationship between the gray index and the thickness of the water film, and calculate the film thickness. The average film thickness deviation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${t}_{avg}$ </tex-math></inline-formula> ) and variable quantity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${dt}$ </tex-math></inline-formula> ) were characterized and used as a means to compare performance. The results show that the average film thickness deviation of the double nozzles is higher than the single nozzle, and variable quantity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${dt}$ </tex-math></inline-formula> ) is lower than that of the single nozzles. In general, the double nozzles increase the thickness and stability of the liquid film thickness on the surface of the disc.

Photolithography methods for 3D microstructures and 3D stacking devices

A framework streamlining instrument for lithography is made and seemed to create 3D micro-arrangements utilizing light-film photo material resists. Since, the two technique confines in greyscale lithography: presentation partition theme and improvement timescale are settled in this way for a client indicated target 3D profile. This gives a proficient and persuading elective as opposed to standard experimentation-based framework plan. As far as possible were asserted by collecting assorted 3D micro-arrangements and the evaluations uncovered unimaginable quantized synchronization with the objective profile. Likewise, Edge-portrayed nm scale lines are organized in silicon utilizing optical lithography with benchmark materials and preparing device are impeccable with short warm copying through 3D three-dimensional (3D) Integrated Circuit structures. A CVD process is utilized to depict optical spacers with photo-resist spread to arrangement covered layers.

Coherent terahertz wireless communication using dual-parallel MZM-based silicon photonic integrated circuits.

Coherent terahertz (THz) wireless communication using silicon photonics technology provides critical solutions for achieving high-capacity wireless transmission beyond 5G and 6G networks and seamless connectivity with fiber-based backbone networks. However, high-quality THz signal generation and noise-robust signal detection remain challenging owing to the presence of inter-channel crosstalk and additive noise in THz wireless environments. Here, we report coherent THz wireless communication using a silicon photonic integrated circuit that includes a dual-parallel Mach-Zehnder modulator (MZM) and advanced digital signal processing (DSP). The structure and fabrication of the dual-parallel MZM-based silicon photonic integrated circuit are systematically optimized using the figure of merit (FOM) method to improve the modulation efficiency while reducing the overall optical loss. The advanced DSP compensates for in-phase and quadrature (IQ) imbalance as well as phase noise by orthogonally decoupling the IQ components in the frequency domain after adaptive signal equalization and carrier phase estimation. The experimental results show a reduction in phase noise that induces degradation of transmission performance, successfully demonstrating error-free 1-m THz wireless transmission with bit-error rates of 10-6 or less at a data rate of 50 Gbps.

Design and implementation of thermal collection networks in 3-D IC structures

The empirical affirmation in the electronics industry is that the power of chips per unit area is growing exponentially. The amount of heat generated is equal to the power; hence as power per unit area increases, so does the amount of heat generated within the chip. Thus, it necessary to mitigate the thermal problems of electronic systems. If not addressed or suppressed, thermal problems can lead to various issues including dielectric breakdown, electromigration, material creeping, unwanted chemical reactions, board warpage, drift in performance, and indirect heating. In this study, a dedicated thermal collection network (TCN) in the back end of the line area of an electronic chip was investigated. This network can help in creating a connection using a thermal through Silicon via (TTSV) to pump up the thermal energy to the heat-sink–fan assembly. Pre-empting heat from the sources could manage the thermal issues arising in chips as well as three-dimensional integrated circuit (3-D IC) structures. The finite-element method was the tool used for analysis. 31.62% of heat suction in TCNs of monolithic ICs, 11.36% in TCNs of 3-D IC structures, and 35.34% of heat suction in junctions of TTSVs compared with different approaches without the postulate used here. This procedure is expected to lead to a new path for redesigning electronic chips and 3-D IC structures.

A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{4}$ </tex-math></inline-formula> -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

High bit rate all-optical 4 to 1 multiplexer by cascading of AND and OR gates in two-dimensional photonic crystals

We present a design of an all-optical 4 to 1 multiplexer by cascading four stages of ψ-shaped three-input AND gates and a Y-shaped four-input OR gate on a square lattice photonic crystal with rods in air interface. The three-input AND gate was designed separately to achieve efficient logical output and integrated into the multiplexer, and the OR gate design was subsequently incorporated with the multiplexer design. The band diagram of the proposed structures was computed using the plane wave expansion method, and the electric field distributions were estimated using the finite-difference time-domain method. The all-optical three-input AND gate had a normalized intensity of 90% for logic “1” and 10% for logic “0,” a contrast ratio (CR) of 9.54 dB, a response time of 0.816 ps, and an operating bit rate of 1.224 Tb / s with a footprint of 189 μm2. The all-optical 4 to 1 multiplexer had a normalized intensity of 79% for logic “1” and 2% for logic “0,” a CR of 15.96 dB, a response time of 0.848 ps, and an operating bit rate of 1.179 Tb / s with a footprint of 1040 μm2. Therefore, the proposed 4 to 1 multiplexer design would be a desirable structure for optical signal processing and photonic integrated circuits.

Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures

Integrated circuits, systems on a chip are the key links in various industrial systems and state defense systems. The emergence of counterfeit integrated circuits, problems of piracy, overproduction, unauthorized interference in the design of microcircuit, hardware Trojans require the development of methods and means of their timely detection. Trojans can be introduced into the integrated circuits structure both on the development stage and during the production process, including the stages of specification, design, verification and manufacturing. The inclusion of additional elements in the integrated circuits structure jeopardizes the functional suitability and reliability of the system as a whole. For the purpose of hardware protection of projects, the methods of hardware coding are currently used.The paper discusses the features and reliability of logical coding of combinational circuits. An algorithm for cracking the code of combinational circuits is proposed, based on the description of encoded structure by the resolution function and reducing the problem to SAT CNF. The initial data for decoding the structure of a digital device is the structural implementation of encoded circuit, obtained, for example, by reverse engineering (prototype design), as well as an activated physical sample of an integrated circuit, when into protected from unauthorized access memory the correct key value is loaded. This sample can be used as a black box model. The main idea of breaking a key is to solve a problem without research on a large interval of values of input and output variables.

A Novel Thermal Modeling of Through Silicon Vias in 3-D IC structures

Heat mitigation is a major challenge in 3-D IC (ThreeDimensional Integrated Circuit) realization. A study of the analytical thermal behavior of the TSV (Through Silicon Via) is very important. Simple and compact yet other models were found deficient to solve this problem in the literature survey. In this paper resistance networks are used to model the heat transfer of the TSVs, in both vertical and horizontal directions, in simpler and compact models. The accuracy of such models is compared with commercially available CFD (Computational Fluid Dynamics) tool. The error of corrections between the tool and developed models are corrected by multiplication factors, resulted within 4.18% accuracy. Varying the thicknesses of a liner, filer, soldering and substrate materials are studied concerning heat transfer physical behavior of three planar TSV stacked systems. The major purpose is to incorporate both vertical and horizontal thermal resistance networks captured more accurately in heat dissipated paths. Proposed models of TSVs can be used in the active interposer simulations or in the face2face fabrication stacked methods of the 3-D IC structures.

Применение радиационно-термической обработки для подавления ч увствительности кремниевых микросхем к одиночным радиационным эффектам

The paper analyses the possibility to reduce the sensitivity of silicon integrated circuits (ICs) to single radiation effects by means of radiation-thermal treatment including irradiation in charged particle accelerators and subsequent low-temperature heat treatment. It is shown that reduction in sensitivity to single radiation effects is provided by formation of thermostable recombination centers in semiconductor IC structure in necessary concentrations. At the same time a decrease in primary photocurrent generated by heavy charged particles or high-energy protons, reduction in transfer coefficients of parasitic bipolar transistors forming thyristor structures, reduction in carrier avalanche multiplication coefficients at high electric field strengths can be provided. Radiationthermal treatment can be introduced in the manufacturing process of ICs of various classes at the end of the manufacturing cycle and does not require correction of the basic technology. A possible undesirable growth of inverse currents and preservation of values of other electrical parameters within acceptable values when using radiation-thermal treatment is provided by choosing optimal modes of irradiation and annealing which are established in the course of experimental tests. The calculated evaluation has shown that using radiation-thermal treatment in the technology of IC fabrication can provide a decrease in the effective collection length of non-equilibrium charge carriers generated under the influence of single radiation effects by at least 10 times which allows considering radiation-thermal treatment as an effective technological tool to suppress the sensitivity to single radiation effects.

Built-in self-repair structure for real-time fault recovery applications

Recent developments in high-tech industries have led to integrated circuits that are used increasingly in most of the critical applications such as medical supervisory systems and space applications. These systems are facing two major challenges, namely reliability and timing requirements. In other words, these systems have to operate correctly while meeting timing requirements even in the presence of several faults; therefore, they must be protected by real-time fault tolerance techniques to deal with both mentioned challenges. However, most of the existing approaches consider only one of these factors. In this paper, we have proposed a new reconfigurable application-specific integrated circuit (ASIC) structure with real-time fault-tolerance capability which repairs itself in two steps with a minimum delay. It includes some reconfigurable basic cells with self-repair capability which are used to implement the first recovery step. In the second step, the fault recovery process is done by replacing the faulty basic cell using a new reconfigurable routing network. According to the simulation results, our proposed structure can tolerate several permanent faults with minimum delay, power consumption, and area overhead.

Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers.

Fault localization in a 3D test assembly using voltage contrast imaging

As 3D-integration continues its acceptance as a next generation advanced packaging technology, characterization techniques regarding fault identification and localization require adaptation for the various geometries utilized. A particular challenge for 3D-stacked integrated circuit (IC) structures is the difficulty in cross-sectional fault localization using common techniques such as cleaving and focused ion beam (FIB) milling that are routinely used for planar IC failure analysis but are incompatible with the material removal challenges associated with multi-tier 3D-IC structures. The work presented here demonstrates the use of voltage contrast imaging in conjunction with backside chip thinning to gain access to and precisely identify inter-layer faults within a three-dimensional (3D) bonded, electrically testable stack structure. Subsequent cross-sectional TEM analysis performed on identified electrical continuity faults confirmed the lack of contact at fault locations between opposing Cu bonding structures which was attributed to particle contamination from the fabrication process. Several test samples did however exhibit sufficient contact and bonding which was evident by the self-diffusion of Cu across the bonding interface.