Thermomigration-driven Cu diffusion and asymmetrical growth of intermetallics in Cu–In system for reliable 3D interconnects

Three-dimensional integrated circuit (3D IC) packaging and heterogeneous integration have emerged as central pillars of contemporary semiconductor scaling. Yet, the multi-physics coupling inherent to stacked architectures manifesting as thermal hot spots, warpage-induced stresses, and interconnect aging demands monitoring and control capabilities that surpass traditional offline metrology. Although Digital Twin (DT) technology provides a principled route to real-time reliability management, the existing literature remains fragmented and frequently blurs the distinction between static multi-physics simulation workflows and truly dynamic, closed-loop twins. This critical review addresses these deficiencies through three main contributions. First, we clarify the Digital Twin hierarchy to resolve terminological ambiguity between digital models, shadows, and twins. Second, we synthesize three foundational enabling technologies. We examine physics-based modeling, emphasizing the shift from finite-element analysis (FEA) to real-time surrogates. We analyze data-driven paradigms, highlighting virtual metrology (VM) for inferring latent metrics. Finally, we explore in situ sensing, which serves as the “nervous system” coupling the physical stack to its virtual counterpart. Third, beyond a descriptive survey, we outline a possible hybrid DT architecture that leverages physics-informed machine learning (e.g., PINNs) to help reconcile data scarcity with latency constraints. Finally, we outline a standards-aligned roadmap incorporating IEEE 1451 and UCIe protocols to support the transition from passive digital shadows toward more adaptive and fully coupled Digital Twin frameworks for 3D IC manufacturing and field operation.

This article presents a novel D-band (110–170 GHz) monolithic millimeter-wave integrated circuit (MMIC) packaging solution based on the metallic multilayer coaxial line (MLCL) concept. The proposed MLCL-based packaging is formed by stacking multiple thin metal layers with specific patterns, and is a substrate-less, nonwelded method. A straight MLCL line is manufactured, and the measured results show a transmission loss of 0.027 dB/mm at D-band. A quartz substrate 50-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $</tex-math> </inline-formula> microstrip through-line chip is packaged as a proof-of-concept, and the measured results show that the average insertion loss is 2.34 dB from 110 to 160 GHz. A commercially active D-band low-noise amplifier (LNA) is verified and measured using the proposed concept, and the average gain of this LNA packaging module is 18.91 dB, which exhibits an average in-band loss of 0.69 dB. The proposed MLCL concept could be a suitable candidate for passive components and active components packaging, with potential for low-loss, low-cost, broadband, and highly integrated systems at the terahertz (THz) band.

In this study, the degradation behavior of mimicked power modules with silicon carbide (SiC)/sintered silver (Ag)/direct bonded aluminum (DBA) structure was investigated during power cycling under a junction temperature of 200<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C. To mitigate this degradation, a sintered Ag composite paste doped with micron-sized Al particles (sintered AgAl) was specifically developed for DBA substrates, leading to the proposed SiC/sintered AgAl/DBA structure. Power cycling results demonstrated that the degradation was effectively suppressed, attributed to the reduced coefficient of thermal expansion (CTE) mismatch between sintered layer and DBA substrate, as well as robust bonding among sintered Ag, DBA substrate, and Al particles. The SiC/sintered Ag/DBA mimicked power module failed after 9200 cycles. Compared to the initial values, transient thermal resistance and junction temperature increased by 39.9% and 123.0%, respectively. In contrast, for the SiC/sintered Ag15Al/DBA structure, the crack density is reduced and the crack spacing increased from 71.6 to 154.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m. CTE mismatch was also reduced from 12.4 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup>/K to 1.8 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup>/K at 200<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula>C. the newly developed SiC/sintered Ag15Al/DBA structure exhibited only a 0.5% and 7.6% increase in transient thermal resistance and junction temperature, respectively, after 10000 cycles. The results are significantly lower than that of SiC/sintered Ag/DBA structure.

Encapsulation is critical for ensuring the durability and reliability of integrated circuits (ICs) in modern electronics, with epoxy molding compounds (EMCs) being widely adopted due to their cost-effectiveness, adaptability, and robust mechanical properties. This review aims to provide a comprehensive analysis of EMC encapsulation processes in IC packaging by comparing wafer-level packaging (WLP) and component-level packaging (CLP) while addressing key challenges and exploring future research directions. The review assesses key encapsulation techniques, including transfer molding, compression molding, and underfill encapsulation, highlighting their advantages, challenges, and applicability across various packaging geometries. It also examines critical process parameters, optimization strategies, and reliability testing protocols to address defects like voids, warpage, and delamination. Emerging solutions, including bio-based resins and recyclable materials are explored to enhance sustainability. The study identifies significant challenges in EMC encapsulation, including material limitations, interfacial stress and environmental concerns. It also highlights the potential of advanced EMC formulations with improved thermal conductivity, three-dimensional (3D) integration, and Artificial Intelligence (AI) driven process control to address these issues. The review highlights the importance of interdisciplinary collaboration in advancing encapsulation technologies, ensuring reliability, miniaturization, and environmental responsibility in the semiconductor industry. This review provides a comprehensive and up-to-date analysis of EMC encapsulation processes, offering insights into both current challenges and future research potentials. The work emphasizes the need for innovative solutions to meet the evolving demands of the semiconductor industry, making it a valuable resource for researchers and industry professionals.

ABSTRACT This paper presents a waveguide‐to‐chip transition for monolithic microwave integrated circuit packaging, targeting millimeter‐wave and subterahertz applications. The proposed structure employs a flip E‐plane probe that interfaces directly with gold bumps, eliminating bondwires to minimize parasitic inductance and signal path length while reducing radiative leakage. An integrated air window cavity accommodates the chip and acts as a power dissipation shield, suppressing higher‐order modes to enhance broadband performance. Measurement results demonstrate that the transition achieves an average insertion loss of 0.73 dB and a return loss better than 10 dB across the D‐band (110–170 GHz), offering a compact and efficient solution for high‐frequency system integration.

As advancing power electronic modules increasingly operate at higher power densities, thermally and thermomechanically stable die-attach materials are required to ensure their thermal performance and reliability. This study conducted finite element (FE) simulations and substrates characterization, followed by low-temperature (LT) solid-liquid interdiffusion (SLID) bonding experiments. FE simulations qualitatively compared the thermal performance of Sn-Ag-Cu (SAC) solder, sintered Ag, and Cu-Sn SLID bonds, while additionally analyzing thermomechanical stress development during Cu-Sn SLID cooling phases. Three types of substrates were characterized in terms of warpage and surface roughness. Additionally, Cu-Sn-In LT SLID bonding process was applied to achieve thin die-attach layers. Dummy Si chips of varying sizes were bonded to the direct copper bonding (DCB) and active metal brazing (AMB) substrates, with bonded area percentage quantified by scanning acoustic microscope (SAM). Furthermore, large-sized functional insulated-gate bipolar transistor (IGBT) chips achieved up to 93% bonded area on insulated metal substrates (IMSs) with the LT SLID die-attach process. Microstructure analysis confirmed stable phase and reduced crack formation located at the corners of the LT bonded samples. The simulation and experimental results demonstrate that LT SLID bonding enables a thin die-attach layer with low thermal resistance and high melting point. However, the substrate technology improvements on warpage and surface roughness reduction remain necessary for implementing the new die-attach method in novel power modules.

The properties of ultrathin glass, including high electrical resistivity, high thermal stability, low surface roughness, and flexibility, render the material particularly intriguing for applications in the semiconductor industry. Notably, when employed in conjunction with through-glass via (TGV) technology, it finds application in the form of flexible functional layers and multilayer materials, thereby facilitating the implementation of novel advanced integrated circuit packaging strategies and complex circuit boards. Due to the complexity of thin glass microhole drilling processes using pulsed lasers, there is a strong demand for fast monitoring sensors and electronics that control the process pulse by pulse during machining to achieve high processing quality and high reproducibility. This is particularly evident in cases where the borehole diameter is reduced to single-digit micrometer level, as inaccuracies such as variations in the glass thickness or pulse energy in this range become increasingly apparent. In this work, the principle of a monitoring sensor based on back-reflected laser pulses for drilling TGVs in ultrathin glass (t = 30 μm) using an ultrashort pulsed laser system is presented. The investigations include the analysis of the time-varying back reflection intensities and the comparison to the changing borehole geometry during the percussion drilling process at different pulse energies. Based on these investigations, algorithms for process control can be developed in the future, which allow a dynamic adjustment of the pulse energy or a pulse-precise termination of the process depending on the drilling progress.

The power consumption required for semiconductors has increased to hundreds of watts due to the growing artificial intelligence (AI) and high-performance computing (HPC) industries. High temperatures resulting from high-power consumption can reduce the electrical performance of integrated circuit (IC) chips, therefore, the effective heat dissipation of IC packages is essential to enhance their performance and extend their life. The thermal interface material (TIM) is one of the critical key factors to thermally improved packaging. Many TIMs, such as polymer, graphite and metal TIMs, have been developed to provide the best thermal performance for packages. Among the various TIMs, indium-silver (InAg) alloy TIMs showed superior thermal performance because of their higher thermal bulk conductivity and much lower interfacial thermal resistance. However, it is also important to maintain the excellent performance even after board level long-term reliability tests. Therefore, the thermal performance of InAg alloy TIMs is described with two long-term reliability tests: 1) 2,000 cycles temperature cycling (TC) test at Condition K and 2) 2,000 hours high temperature storage (HTS) test at 135°C. Junction-to-case thermal resistance (ӨJC) measurements of 60 x 60-mm body lidded flip chip ball grid array (FCBGA) packages were performed with a water-cooled, cold plate cooling system. The 60 x 60-mm body lidded FCBGA thermal test vehicle (TTV) has a 25.6 x 25.6-mm die divided into 36 unit-cells with the temperature of each cell measured individually. The indium-silver alloy TIM thermal performance was quite different from polymer or graphite TIMs. The difference of the heat flow mechanism from the die to lid of both HTS and TC test conditions is described using three-dimensional (3D) thermal simulation to further understand the thermal characteristics of the metal TIM.

The polyimide (PI) and photosensitive polyimide (PSPI) were always regarded as protecting layer or insulation layer in semiconductor industry due to its high-temperature resistance, outstanding mechanical properties, chemical and radiation resistance, and excellent dielectric properties. The PI and PSPI had various usage methods and applications in organic light-emitting diode (OLED) display, integrated circuit (IC) and IC packaging based on its specific performance advantages. This paper introduced the usage method and application of PI film and PSPI in OLED display, IC fabrication and IC packaging. For PI film, the usage method including transfer patterning from a PR patterning layer and the laser for patterning technology, the PI was usually regarded as flexible substrate in OLED devices and insulation layer in IC packaging. For PSPI, the usage method in-cluding forming patterning based on photolithography technology, the PSPI was usually regarded as planarization layer, pixel definition layer and pixel supporting layer in OLED display, the PSPI was also regarded as protecting layer and insulation layer in IC fabrication and packaging.

Integrating thin film resistors into organic substrates for module and integrated circuit (IC) packaging presents a truly transformative approach to electronics design. This methodology offers many benefits, primarily from miniaturization and optimization of circuit components. By embedding thin film resistors directly within the organic substrate layers, the need for discrete resistors is significantly reduced, thereby conserving valuable surface area on the substrate.Furthermore, the elimination of vias, which are traditionally required for connecting different layers within a multilayer PCB, results in a remarkable reduction of signal path interruptions. This streamlined architecture facilitates a smoother signal transmission, which is particularly beneficial for high-frequency applications. The uninterrupted signal paths inherent in this design contribute to superior high-frequency response, with reduced parasitic capacitance and inductance, leading to improved signal integrity and performance.The manufacturing process of embedding thin film resistors requires a novel new resistive material. However, it utilizes traditional processing techniques, ensuring seamless integration into existing production lines without requiring specialized equipment or significant alterations to standard procedures. This compatibility with conventional fabrication methods ensures that the transition to this innovative design can be adopted with minimal disruption to current manufacturing workflows, making it a practical and feasible solution for the industry.This paper will describe the materials and processes used to make a prototype IC package. It will show the average resistor values and tolerance that can be obtained.In summary, using thin-film resistors embedded in organic substrates for modules and IC packaging is a forward-thinking solution that addresses the electronics industry’s ever-increasing demands for miniaturization, efficiency, and high-frequency performance.

Integration of electronic components into aerospace platforms offers the unique challenges of limited and constrained volumes. Utilizing non-planar surfaces allows for a drastic increase in the area available for electronics integration. Additive manufacturing (AM) can meet this need by working with a variety of substrate geometries to produce non-planar circuits capable of operating in harsh space environments. Here we demonstrate the use of aerosol jet printing (AJP) and dispense printing to integrate passive traces of a daisy chain to a silicon-based quad flat no lead (QFN) die onto curved 96% purity alumina substrates. Adhesion of multiple material interfaces was tested to determine the compatibility of different components. AJP was used to fabricate all traces and bond pads using silver-based ink. Assembly was completed by depositing a conductive epoxy to attach the die. Samples were placed in an environmental chamber and cycled between –55°C and 125°C for 10 cycles as per MIL-STD-883, M1010, Condition B. Afterwards, the change in resistance was measured for all lines in the fabricated daisy chain. All interfaces provided strong adhesion since the failure mode of most interfaces was adhesive failure and not cohesive failure between the deposited layers and substrate. The only interface which experienced consistent cohesive failure was the conductor on the dielectric pad. Despite the failure mode, this material was selected as the adhesive force was still acceptable. Two samples fabricated on convex and concave alumina substrates were subjected to thermal cycling to study the effect of temperature variation on the assembly, and the results found that no variance in the lines resistance exceeded a ±10% change in resistance. Overall, the devices performed well with changes in resistance being better mitigated by thicker conductive layers. The additive manufacturing techniques demonstrated in this work enhance the electronic industry by improving performance and reliability while simultaneously reducing the material cost and waste.

With the rapid growth in demand for data center, artificial intelligence, high-performance computing and autonomous vehicles, FCBGA (Flip Chip Ball Grid Array) technology is advancing toward larger die sizes and finer bump pitches. The need for higher I/O counts has driven the demand for smaller bump pitches to increase I/O density. The traditional bump pitches of 150μm are being reduced to 80μm or less. Finer bump pitch introduce significant cleaning challenges as it increases the likelihood of flux residue, affecting product performance and reliability. This article mainly explored the major factors of flux cleaning, including concentration of cleaner, clean speed and wash tank temperature. In this experiment, highly active halogen flux was used for the cleaning test. Due to its chlorine compounds and corrosive, the effects of flux residue can be easily observed through reliability testing. FCBGA packages were subjected to several reliability tests, including: JEDEC Level 3 preconditioning (MSL3); uHAST (96 hours); bHAST (264 hours); HTSL (1000 hours). After these, the functionality of the packages was evaluated using I/V tests. SAT (Scanning Acoustic Tomography) to examine internal structural integrity. If structural issues such as white bumps were detected, SEM (Scanning Electron Microscopy) and TEM (Transmission Electron Microscopy) were employed to observe package interface delamination. EDS (Energy Dispersive Spectroscopy) was used to analyze the elemental composition at delamination position. Overall, the findings of this study indicate that cleaner concentration and clean speed are key factors in flux cleaning process after die attach, that can be adjusted to effectively clean flux residues, thereby enhancing the reliability and performance of FCBGA packages.

Silicon nitride photonic integrated circuits were fabricated on glass substrates for the first time using reactive ion etched edge facets, demonstrating a minimum propagation loss of 2.4 ± 0.36 dB/cm and minimum edge coupling loss of 2.17 ± 0.79 dB. Two sets of processes were developed: one including high temperature steps (T &gt; 350°C) common to complimentary-metal-oxide-semiconductor (CMOS) foundry front-end-of-line tools and one including low temperature steps (T &lt; 350°C) compatible with CMOS foundry back-end-of-line tools. For both the high and low temperature samples, a CMOS foundry compatible process was also established for dry etching edge facets &gt; 85 𝜇m deep into SiO2 substrates using magnetically enhanced reactive ion etching with amorphous silicon hard masks without metal. Results show the viability of this glass interposer to help achieve Pbps co-packaged optics switch performance by addressing the material limitations of organic or silicon based interposers and enabling pick-and-place assembly of photonic die to package level integrated photonic waveguides.

Like many other industries, semiconductor packaging is also being impacted by increasing regulation around used of Perfluoroalkyl and Polyfluoroalkyl substance (PFAS) based materials in their supply chain. There have been increasing concerns over the years regarding hazards posed by PFAS. The regulatory bodies across the globe have taken notice and are acting on regulating the use of this chemical. On the other hand, semiconductor manufacturing has seen lot of advances in the recent years to keep pace with emerging requirements for power devices. With technology developing at rapid pace in consumer electronics and automation taking a dominant role in automotive and industrial sectors, the semiconductor devices that power these end applications need to demonstrate high performance and reliability. This high-performance requirement translates to the components and materials that are used to manufacture these devices since any weak link in the architecture of the semiconductor packages will lead to premature failure or low reliability of the device. This dual dynamics of PFAS-free regulation coupled with higher performance requirements has led to urgent demand for high performance PFAS-free material solutions.

To ensure the highest safety standards in modern automobiles, the industry is constantly adopting zero-defect frameworks, such as AEC-Q100, which aims for defective-parts-per-billion (DPPB) or grade-0 level reliability standards in automotive integrated-circuit (IC) packages. Most contemporary wire-bonded packages use either pure copper (Cu) or palladium (Pd)-coated copper (PCC) wires bonded to aluminum (Al) bond pads as interconnections. This choice is made due to their lower cost and superior electrical and mechanical performance, compared to traditional gold wire-based devices. However, these Cu–Al wire-bonded interconnections are prone to ion-induced lift-off/open-circuit corrosion failures when exposed to even trace amounts (<20 ppm) of extrinsic and/or intrinsic halide (Cl− and Br−) contaminants, decreasing device longevity. This study investigates corrosion failure mechanisms in Cu and PCC wire-based devices by subjecting non-encapsulated devices to a highly accelerated aqueous-immersion screening test containing 100 ppm chloride (Cl−), 100 ppm bromide (Br−), and a mixed-ion solution (MX: Cl− + Br−). The screening results indicate that even control PCC-Al devices with a Pd overlayer can be susceptible to Cl− and Br− induced corrosion, with 21 ± 1.6% lift-off failures in MX-solution. In contrast, applying a novel Cu-selective passivation reduced lift-off to 3.3 ± 0.6% and introducing phosphonic-acid-based inhibitor into the MX solution eliminated lift-off failures, demonstrating markedly improved reliability.

A sheet-type sinter-bonding material was developed to form thermally stable and highly heat-conductive joints suitable for wide-bandgap (WBG) semiconductor dies and high-heat-flux devices, and its bonding characteristics were investigated. To enhance the cost-competitiveness of the bonding material, Ag-coated Cu (Cu@Ag) particles were employed as fillers instead of conventional Ag particles. To facilitate accelerated sintering, a bimodal particle size distribution comprising several micron- and submicron-sized particles was adopted by synthesizing and mixing both size ranges. For sheet fabrication, a decomposable resin was used as the essential binder component, which could be removed during the bonding process via thermal decomposition. This approach enabled the formation of a sintered bond line composed entirely of Cu@Ag particles. Thermogravimetric and differential thermal analyses revealed that the decomposition of the resin in the sheet occurred within the temperature range of 290–340 °C. Consequently, sinter-bonding conducted at 350 °C and 370 °C exhibited significantly superior bondability compared to bonding at 330 °C. In particular, sinter-bonding at 350 °C for just 60 s resulted in a highly densified joint microstructure with a low porosity of 7.6% and high shear strength exceeding 25 MPa. The formation of the bond line was initiated by sintering between the outer Ag shells of the adjacent particles. However, with increasing bonding time or temperature, sintering driven by Cu diffusion from the particle cores to the outer Ag shells, particularly in the submicron-sized particles, was progressively enhanced. These results obtained from the fabricated sheet-type materials demonstrate that, even with the use of resin, rapid solid-state sintering between filler particles combined with the removal of resin through decomposition enables the formation of a metallic bond line with excellent thermal conductivity.

Third-generation wide-bandgap (WBG) semiconductor power electronics exhibit excellent workability, but high-temperature packaging technology limits their applications. TLP, TLPS, and nanoparticle sintering have the potential to achieve a high-temperature-resistant joint at a lower bonding temperature. However, a long bonding time, voids in the joint, powder oxidation, and organic solvent residues impede their application. A novel interlayer and other approaches have been proposed, such as preformed Sn-coated Cu foam (CF@Sn), a Cu-Sn nanocomposite interlayer, self-reducible Cu nanoparticle paste, bimodal-sized Cu nanoparticle pastes, organic-free nanoparticle films, and high-thermal-conductivity and low-CTE composite paste. Their preparation, bonding processes, and joint properties are compared in this paper.

This paper investigates the suppression of the cohesive cracking mode (CCM) in the sintered silver (s-Ag) die layer by intentionally introducing anisotropic porosity through two press sintering methods. Full press (FP) and local press (LP) bonding represent the s-Ag formed by pressing the die-attached assemblies (DAAs) on either the entire top surface or only on the silicon carbide (SiC) top surface, respectively. The fabricated DAAs were encapsulated with epoxy molding compounds. Degradation was evaluated using a nine-point bending test (NBT) under cyclic force between 0 and 270 N with a triangle waveform for 3 min per cycle at 150 °C. Scanning tomography images after 500 NBT cycles showed that the LP reduced the inner degradation ratio by up to 21.1% compared to the FP. Cross-sectional scanning electron microscopy revealed that the FP progressed cracking in the s-Ag die layer, whereas the LP showed no evidence of cracking. A finite element analysis revealed that in the FP, the accumulated plastic strain (APS) was concentrated in the s-Ag layer within the inner SiC chip. In contrast, the APS of the LP was preferentially concentrated outside the SiC chip. This preferential localization of damage outside the chip presents a promising approach for enhancing the reliability of packaging products.

ABSTRACTResearch on eco‐friendly materials in electronic applications has gained significant interest in recent years. The present work is aimed at investigating how the structure and properties of bio‐epoxies affect the performance of epoxy molding compound (EMC) applications in integrated circuit (IC) packaging. Three bio‐epoxies with different molecular structures were characterized and compared with a commercial epoxy as a control. The results reveal that the thermal stability and CTE of the bio‐epoxies are strongly affected by their glass transition temperature (Tg). Lower molecular chain flexibility requires more energy for chain movement and breakage, while epoxies cured with a symmetrical and linear curing agent show higher thermal conductivity. The linear structure provides a greater phonon mean path, improving heat transfer. Epoxies with greater polarity and chain flexibility show a lower dielectric constant. Furthermore, the presence of a reactive diluent, which acts as a plasticizer, was identified in BE130 and BE90. It not only reduces the Tg of the cured epoxy but also improves its ductility. However, they did not contribute to the reactivity of the crosslinking reaction and the crosslinking density. These findings demonstrate that bio‐epoxies can replace commercial epoxies in the EMC matrix, offering an alternative pathway to enhance the environmental sustainability of electronic products.