Integrated Circuit Manufacturing Technology Research Articles

Advanced Integrated Circuit Manufacturing Technology Process Industry Development

Integrated circuits are circuits with specific functions that are integrated together by semiconductor processes and are a new type of semiconductor device developed in the late 1950s through the 1960s. Integrated circuits are the foundation of information development and the benchmark for high quality development of national economy. This paper introduces the concept of integrated circuits as well as the integrated circuit process, and the application areas of integrated circuits, which account for an expanding and growing share of information, communication, consumer electronics, automotive electronics, medical electronics and other consumer areas. It discusses China's future IC process development path by combining the IC production process and design process, industrial development, design process and preparation limitations, and proposes relevant suggestions and strategies by speculating on the future development of the process.

Algorithms and Systems of Machine Vision in Integrated Circuit Manufacturing Technology

Algorithms and Systems of Machine Vision in Integrated Circuit Manufacturing Technology

Study on the formation and mechanism of aluminum bulge defect in semiconductor integrated circuit manufacturing

With the development of semiconductor integrated circuit manufacturing technology, the defects that lead to yield failure are also occurring constantly. In our work, the aluminum bulge defects in the metallization process are briefly analyzed, it will lead to macroscopic chromatic aberration and yield failure. It was confirmed by analyzing the crystal structure of titanium nitride (TiN), which the (111) crystal plane of TiN film can greatly improve the surface roughness of film. On the other hand, by changing the etching conditions of tungsten film, the etching selectivity ratio of tungsten film and TiN film is increased, so as to reduce the defects. Thus, the main factors affecting the bulge defects in the metallization process include the microstructure of TiN film and the etching process of tungsten film.

Cross-compensation of FET sensor drift and matrix effects in the industrial continuous monitoring of ion concentrations

Field-effect transistor (FET) sensors are attractive potentiometric (bio)chemical measurement devices because of their fast response, low output impedance, and potential for miniaturization in standard integrated circuit manufacturing technologies. Yet the wide adoption of these sensors for real-world applications is still limited, mainly due to temporal drift and cross-sensitivities that introduce considerable error in the measurements. In this paper, we demonstrate that such non-idealities can be corrected by joint use of an array of FET sensors – selective to target and major interfering ions – with machine learning (ML) methods in order to accurately predict ion concentrations continuously and in the field. We studied the predictive performance of linear regression (LR), support vector regression (SVR), and state-of-art deep neural networks (DNNs) when monitoring pH from combinatorial H+, Na+, and K+ ion-sensitive FET (ISFET) sequences of readings collected over a period of 90 consecutive days in real water quality assessment conditions. The proposed ML algorithms were trained against reference online measurements obtained from a commercial pH sensor. Results show a greater capability of DNNs to provide precise pH monitoring for longer than a week, achieving a relative root-mean-square error reduction of 73% over standard two-point sensor calibration methods.

Exposure latitude aware source and mask optimization for extreme ultraviolet lithography.

Extreme ultraviolet (EUV) lithography is a new generation of integrated circuit manufacturing technology with great development prospects. EUV lithography has more significant demand for high exposure latitude (EL) due to greater requirements for the stability of the light source. Source and mask optimization (SMO) technology is widely used to compensate for imaging distortion. In this paper, we propose an EL-aware SMO (ELASMO) method that uses a low-resist threshold sensitivity (LRS) penalty function to improve the EL in EUV lithography. Compared to conventional SMO, the proposed ELASMO method can significantly enhance the aerial image contrast, improve the EL, and enlarge the process window while ensuring high imaging fidelity.

Research progress of preparation of large-scale two-dimensional magnetic materials and manipulation of Curie temperature

To date, despite the continuous improvement of integrated circuit manufacturing technology, it has been limited by quantum effects and the shrinking of device size has caused the industry to encounter bottlenecks such as low reliability and high power consumption. The “Moore’s Law” that has lasted for nearly 50 years in the microelectronics industry will not be sustainable. In 2004, the advent of graphene, a two-dimensional (2D) material, brought new opportunities to break through the power consumption bottleneck of integrated circuits. Due to the low dimensionality, 2D materials exhibit a variety of fasinatingly electrical, ferromagnetic, mechanical, and optical properties at an atomic level. Among them, ferromagnetism has a wide range of applications in information processing, magnetic memory and other technologies. However, only a few 2D ferromagnetic materials are successfully synthesized. Meanwhile, the magnetic long-range order will be strongly suppressed within a limited temperature range due to thermal fluctuations, and thus bringing non-ignorable limitations and challenges to subsequent work. Therefore, the realization and control of room-temperature ferromagnetism in 2D magnetic materials is the major concern at this stage. In light of the above, this review first introduces the development process, preparation methods and superior properties of 2D magnetic materials in detail, and then focuses on the methods of manipulating the Curie temperature of 2D magnetic material. Finally, we briefly give an outlook of the application prospects in the future.

Scheduling dual-arm cluster tools with multiple wafer types and residency time constraints

Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual customization, which poses a huge challenge to the scheduling of cluster tools with single-wafer-type fabrication. Concurrent processing multiple wafer types in cluster tools, as a novel production pattern, has drawn increasing attention from industry to academia, whereas the corresponding research remains insufficient. This paper investigates the scheduling problems of dual-arm cluster tools with multiple wafer types and residency time constraints. To pursue an easy-to-implement cyclic operation under diverse flow patterns, we develop a novel robot activity strategy called multiplex swap sequence. In the light of the virtual module technology, the workloads that stem from bottleneck process steps and asymmetrical process configuration are balanced satisfactorily. Moreover, several sufficient and necessary conditions with closed-form expressions are obtained for checking the system's schedulability. Finally, efficient algorithms with polynomial complexity are developed to find the periodic scheduling, and its practicability and availability are demonstrated by the offered illustrative examples.

Reconfigurable missile‐borne SAR imaging SoC design

With the rapid development of the integrated circuit manufacturing technology and the radar technology, the demand for miniaturisation, low power consumption, and real-time performance of synthetic aperture radar (SAR) imaging system is becoming higher and higher. By designing reconfigurable IP cores and configuring parameters through CPU, a reconfigurable missile-borne SAR imaging SoC chip based on IP reuse is designed to meet this urgent demand. Using 0.13μm CMOS process, the SoC chip has been taped out and verified successfully. Compared with the traditional ‘DSP + FPGA’ platform, this chip can ensure the real-time performance of the missile-borne SAR imaging system and has more advantages in scale and power consumption.

SPP waveguide of CdS nanowires and graphene nanobelts

Graphene has potential to replace germanium as compound semiconductor for high-performance devices because of its unique optoelectronic properties and availability of existing integrated circuit manufacturing technology. This study investigates surface plasmon polariton (SPP) waveguide-based interaction between CdS nanowires and graphene nanobelts to determine shortcomings of the existing technology. The structure uses MgF2 as cladding, which symmetrically covers CdS nanowires and graphene nanobelts. An air gap of same width is etched in middle of CdS nanowires and graphene nanobelts. SPP is optically excited. Gain compensation is obtained through coupling effect of nanowires, capacitance-enhanced effect of air gap and GaAs semiconductor material, and low refractive index of buffer layer to reduce transmission loss. The structure can achieve strong photon localization and easily implement low threshold for nanometer laser. Experiments on characteristics of SPP show that increasing air gap width of structure reduces transmission loss and increases limiting factors. Limiting factor of waveguide structure is less than 0.15, which indicates ultra-deep subwavelength constraints. SPP waveguide can be integrated with various nanophotonic and electronic devices and has broad application prospects in optical sensing, optical communication, and other fields.

Surface Plasmon Polariton Waveguide by Bottom and Top of Graphene

Semiconductor surface plasmon polariton (SPP) waveguide has unique optical properties and compatibility with existing integrated circuit manufacturing technology; thus, SPP devices of semiconductor materials have wide application potential. In this study, a new integrated graphene SPP waveguide is designed using the bottom and top roles of graphene. Moreover, a T waveguide structure is designed by InGaAs of semiconductor gain, with rectangular GaAs material on both sides. The structure adopts light to stimulate the SPP, where its local area is enhanced by the interaction between two interface layers and a semiconductor gain and where its frequency can be adjusted by the thickness of the graphene. Characteristic analysis reveals the coupling between the T semiconductor gain and the SPP mode. The propagation distance of the waveguide can reach 75 cm, the effective mode field is approximately 0.0951λ 2, the minimum of gain threshold is approximately 2992.7 cm−1, and the quality factor (FOM) can reach 180. The waveguide structure which provides stronger localization can be compatible with several optical and electronic nanoscale components. That means, it can provide light for surface plasmon circuit and also can provide a great development in the low-threshold nanolaser.

MICROFABRICATED ORAL DRUG DELIVERY SYSTEMS

Microfabrication is a collection of techniques developed to fabricate micron sized features, best suited to develop the novel drug delivery microdevices. microfabrication techniques were originally developed in the microelectronics industry to produce functional devices on the micron scale such as sensors, switches, filters and gears. Approaches like modification of drug itself to improve its permeability/ solubility characters, encapsulation techniques using micro/nanoparticles, use of protease inhibitors to curb proteolytic degradation, and use of intelligent polymers and hydrogels do not offer a complete solution for adequate and safe delivery of drugs, vaccines, peptides, proteins and others. This technology has been applied to the successful fabrication of a variety of implantable and oral drug delivery devices based on silicon, glass, silicone elastomer or plastic materials. These techniques that are utilized at present have developed as a result of integrated circuit manufacturing technologies, such as photolithography, thin film growth/deposition, etching and bonding. Micromachining allows for control over surface features, aspect ratio, particle size, shape and facilitating the development of an engineered particle for drug delivery that can incorporate the advantages of microparticles while avoiding their design flaws. It helps in multi-cell and multi-site attachment, multiple reservoirs of desired size to contain multiple drugs/biomolecules of interest. These fabrication techniques have led to the development of microelectromechanical systems (MEMS), bioMEMS, micro-total analysis systems (μ-TAS), lab-on-a-chip and other microdevices. Microfabricated devices are designed for uni-directional release, to prevent enzyme degradation, precise dosing and better patient compliance. Drug delivery in the form of microparticles and micropatches have been used for targeted delivery as well as in treatment of diseases like diabetes and cancer.

Flex-to-Rigid (F2R): A Generic Platform for the Fabrication and Assembly of Flexible Sensors for Minimally Invasive Instruments

The flex-to-rigid (F2R) platform allows for the fabrication of miniature and flexible sensor assemblies for minimally invasive medical instruments such as catheters and guidewires. Devices fabricated on silicon wafers are transferred onto polyimide and partially rendered flexible by means of a two-step backside silicon deep reactive ion etching. The flexibility allows for the devices to be folded into, or wrapped around the tip of the instruments. The fabrication of the whole assembly is based on standard integrated circuit manufacturing technologies so that it is possible to scale the devices down to the dimension of the smallest guidewires. Several demonstrations are presented to show the versatility of the F2R technology, and a polyimide-based flexible thermal flow sensor for application at the tip of a 360- μm diameter guidewire is introduced.

Built-In Self-Repair Schemes for Flash Memories

The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories.

Modelling the effectiveness of computer-aided development projects in the semiconductor industry

This paper presents a complete quantitative model to estimate the potential benefits of simulation-based projects over the conventional approach. In the semiconductor industry, technology computer-aided design has shown a great potential for rapid and cost-effective development of advanced integrated circuit manufacturing technologies. However, a complete quantitative model to estimate the efficiency and effectiveness of simulation-based projects has not yet been developed. This paper describes a simplified mathematical model to estimate the reduction in development cycle time and cost by computer applications in technology development to reduce the number of expensive and time-consuming experiments in the wafer fabrication facility. This model, clearly, demonstrates a reduction in technology development cycle time over 67% and multi-million dollar cost savings by computer-aided technology development in contrast to the conventional trial-and-error-experimentation. Thus, the proposed model offers project managers a valuable tool to quantitatively assess the time and cost advantage of computer-aided advanced technology development projects.

Development and application prospects of piezoelectric precision driving technology

With the rapid development of science and technology, microelectronics manufacturing, photonics technology, space technology, ultra-precision machining, micro-robotics, biomedical engineering and other fields urgently need the support of modern precision driving theory and technology. Modern precision driving technology can be generally divided into two parts: electromagnetic and non-electromagnetic driving technology. Electromagnetic driving technology is based on traditional technology, has a low thrust-weight ratio, and needs deceleration devices with a cumbrous system or a complex structure. Moreover, it is difficult to improve positioning accuracy with this technology type. Thus, electromagnetic driving technology is still unable to meet the requirements for the above applications. Non-electromagnetic driving technology is a new choice. As a category of non-electromagnetic driving technology, piezoelectric driving technology becomes an important branch of modern precision driving technology. High holding torque and acute response make it suitable as an accurate positioning actuator. This paper presents the development of piezoelectric precision driving technology at home and abroad and gives an in-depth analysis. Future perspectives on the technology’s applications in the following fields are described: 1) integrated circuit manufacturing technology; 2) fiber optic component manufacturing technology; 3) micro parts manipulation and assembly technology; 4) biomedical engineering; 5) aerospace technology; and 6) ultra-precision processing technology.

Low-cost Distributed Embedded Control Systems

This paper presents how a complex distributed control system can be inexpensively achieved using low-cost controllers. These controllers will be interconnected in a network with an open communication bus called CAN. The development of integrated circuit manufacturing technology has increased the power and performance of the microprocessors and microcontrollers as opposed to its price, and if they also have communication capabilities, they can be used to implement low-cost distributed control nodes.Nodes with different computer architectures (from 16 to 32 bits processors) could be combined as long as the complexity of a given application. This approach was tested in a simulated process, using a dsPICTM (Microchip, 2006) microcontroller control implementation, supervised by an XScale microcomputer with a GPL (General Public License) real-time operating system as RTLinux.

Horizontal buried channels in monocrystalline silicon

This paper reports horizontal buried channels in monocristalline silicon. Those channels are a few microns in width and height and several hundred microns long. The main applications for those buried channels are microfluidic networks for MEMS devices and cooling systems for integrated circuits. Their fabrication is based on integrated circuit standard processes such as selective monocristalline epitaxial growth and high temperature annealing. The major interest of the method is its compatibility with integrated circuit manufacturing technology.

Biographies

Gordon Earle Moore, a chemist with a PhD from the California Institute of Technology, was a key figure in the development of the semiconductor industry and silicon integrated circuit technology. Moore co-founded Fairchild Semiconductor, and, subsequently, the Intel Corporation. In 1965, Moore published an observation about the exponential pace of development in integrated circuit manufacturing technology that has come to be known as "Moore's law." Moore's contributions to semiconductor devices and the semiconductor industry have had a major impact on the development of Silicon Valley as a high-technology district.

Design of a tunable frequency CMOS fully differential fourth-order Chebyshev filter

A new fully differential amplifier and a fully differential R-MOSFET-C fourth-order Chebyshev active lowpass filter employing passive resistors and current-steering MOS transistors as variable resistors are proposed. The implementation relies on the tunability of current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the cutoff frequency of Chebyshev active filter can be realized accurately tunable. The amplifier is not only with voltage common-mode negative feedback (VCMFB), but also with current common-mode negative feedback (CCMFB), which will benefit for the stability of its DC operating point. A cutoff frequency of 138kHz fourth-order Chebyshev lowpass filter was designed and fabricated using 3.3V power supply and 0.35μm CMOS technology. Chip test results demonstrate better than −68dB THD with 70kHz, 2.0Vpp signal, frequency turning range of more than 14,000 from 3Hz to 420kHz, chip area of 0.36mm2 and power consumption of 16mW.

Simultaneous power supply planning and noise avoidance in floorplan design

With today's advanced integrated circuit manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single system on a chip. However, without careful power supply planning in layout, the design of chips will suffer from local hot spots, insufficient power supply, and signal integrity problems. Postfloorplanning or postroute methodologies in solving power delivery and signal integrity problems have been applied but they will cause a long turnaround time, which adds costly delays to time-to-market. In this paper, we study the problem of simultaneous power supply planning and noise avoidance as early as in the floorplanning stage. We show that the problem of simultaneous power supply planning and noise avoidance can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no static IR (voltage)-drop requirement violation in meeting the current and power demand requirement imposed by the circuit blocks compared with a traditional floorplanner and 45.7% of improvement on a /spl Delta/I noise constraint violation compared with the approach that only considers power supply planning.