Insulator Semiconductor High Electron Mobility Research Articles

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al2O3. Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator.The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.

Effect of high voltage stress on the DC performance of the Al2O3/AlN GaN metal–insulator–semiconductor high-electron mobility transistor for power applications

We demonstrate an Al2O3/AlN/AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistor (MIS-HEMT) device with stable electrical properties under high-voltage stress, by using an Al2O3/AlN stack layer as the gate dielectric layer. Excellent quality AlN/Al2O3 GaN interface was obtained by using plasma-enhanced ALD (PE-ALD), resulting in a very low interface trap density (Dit) of ∼1.8 × 1011 eV−1 cm−2, obtained by using the conductance method. The device exhibits a small threshold voltage hysteresis of ∼200 mV and a lower gate–source leakage current. No obvious changes in the drain–source current and ON-resistance were observed for the device that was subject to the drain–source voltage stress of 100 V for 15 h.

Thin-barrier enhancement-mode AlGaN/GaN MIS-HEMT using ALD Al2O3 as gate insulator**Project supported by the National Natural Science Foundation of China (Nos. 61474101, 61106130) and the Natural Science Foundation of Jiangsu Province of China (No. BK20131072).

A high-performance enhancement-mode (E-mode) gallium nitride (GaN)-based metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) that employs a 5-nm-thick aluminum gallium nitride (Al0.3Ga0.7N) as a barrier layer and relies on silicon nitride (SiN) passivation to control the 2DEG density is presented. Unlike the SiN passivation, aluminum oxide (Al2O3) by atomic layer deposition (ALD) on AlGaN surface would not increase the 2DEG density in the heterointerface. ALD Al2O3 was used as gate insulator after the depletion by etching of the SiN in the gate region. The E-mode MIS-HEMT with gate length (LG) of 1 μm showed a maximum drain current density (IDS) of 657 mA/mm, a maximum extrinsic transconductance (gm) of 187 mS/mm and a threshold voltage (Vth) of 1 V. Comparing with the corresponding E-mode HEMT, the device performances had been greatly improved due to the insertion of Al2O3 gate insulator. This provided an excellent way to realize E-mode AlGaN/GaN MIS-HEMTs with both high Vth and IDS.

Impact of gate insulator on the dc and dynamic performance of AlGaN/GaN MIS-HEMTs

This paper studies the impact of the properties of the SiN gate insulator on the dc and dynamic performance of AlGaN/GaN Metal Insulator Semiconductor High Electron Mobility Transistors (MIS-HEMTs). We compare the dynamic and transient behaviour of devices with identical epitaxial structure and different gate insulators: RTCVD-SiN (rapid-thermal-chemical-vapour-deposition) and PEALD-SiN (plasma-enhanced-atomic-layer-deposition).We demonstrate the following important results: (i) the gate leakage of devices with PEALD-SiN insulator is three orders of magnitude lower than that of samples with RTCVD-SiN; (ii) the use of PEALD-SiN reduces significantly the transistor threshold voltage hysteresis; (iii) both sets of samples show measurable threshold voltage shift when submitted to forward gate bias. In addition we demonstrate (iv) that the VTH shift is well correlated with the gate forward leakage and bias, for both sets of samples. This result indicates that trapping is induced by the injection of electrons in the gate insulator when a positive bias is applied to the gate; in PEALD SiN devices, the reduction of the gate (forward) leakage results in a significant decrease in VTH shift.

Dynamic Performance of AlN-Passivated AlGaN/GaN MIS-High Electron Mobility Transistors Under Hard Switching Operation

High-frequency and high-temperature dynamic performance of plasma-enhanced atomic layer deposition AlN-passivated enhancement-mode GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) has been investigated under hard switching conditions. Low dynamic ON-resistance ( $R_{{\mathrm{{\scriptscriptstyle ON}}}})$ degradation with small frequency dispersion and weak temperature dependence is obtained. The effectiveness of AlN passivation in suppressing current collapse is proved even under hard switching operations, which, according to other reports of SiN x -passivated devices, could worsen the dynamic $R_{{\mathrm{{\scriptscriptstyle ON}}}}$ degradation due to the trapping of additional hot electrons.

Effect of surface pretreatment on interfacial chemical bonding states of atomic layer deposited ZrO2 on AlGaN

Atomic layer deposition (ALD) of ZrO2 on native oxide covered (untreated) and buffered oxide etchant (BOE) treated AlGaN surface was analyzed by utilizing x-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy. Evidenced by Ga–O and Al–O chemical bonds by XPS, parasitic oxidation during deposition is largely enhanced on BOE treated AlGaN surface. Due to the high reactivity of Al atoms, more prominent oxidation of Al atoms is observed, which leads to thicker interfacial layer formed on BOE treated surface. The results suggest that native oxide on AlGaN surface may serve as a protecting layer to inhibit the surface from further parasitic oxidation during ALD. The findings provide important process guidelines for the use of ALD ZrO2 and its pre-ALD surface treatments for high-k AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors and other related device applications.

Impact of residual carbon impurities and gallium vacancies on trapping effects in AlGaN/GaN metal insulator semiconductor high electron mobility transistors

Effects of residual C impurities and Ga vacancies on the dynamic instabilities of AlN/AlGaN/GaN metal insulator semiconductor high electron mobility transistors are investigated. Secondary ion mass spectroscopy, positron annihilation spectroscopy, and steady state and time-resolved photoluminescence (PL) measurements have been performed in conjunction with electrical characterization and current transient analyses. The correlation between yellow luminescence (YL), C- and Ga vacancy concentrations is investigated. Time-resolved PL indicating the CN ON complex as the main source of the YL, while Ga vacancies or related complexes with C seem not to play a major role. The device dynamic performance is found to be significantly dependent on the C concentration close to the channel of the transistor. Additionally, the magnitude of the YL is found to be in agreement with the threshold voltage shift and with the on-resistance degradation. Trap analysis of the GaN buffer shows an apparent activation energy of ∼0.8 eV for all samples, pointing to a common dominating trapping process and that the growth parameters affect solely the density of trap centres. It is inferred that the trapping process is likely to be directly related to C based defects.

Improved Interface and Transport Properties of AlGaN/GaN MIS-HEMTs With PEALD-Grown AlN Gate Dielectric

In this paper, we demonstrated AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with AlN gate dielectric grown by plasmaenhanced atomic layer deposition (PEALD). The high-quality interface of AlN/AlGaN/GaN MIS-HEMTs resulted in a very small threshold voltage (Vth) hysteresis and dispersion. Simultaneously, the MIS-HEMTs exhibited a high-peak transconductance of 289 mS/mm and a small Vth shift of 0.8 V, while those for Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /AlGaN/GaN metal-oxide-semiconductor HEMTs were 203 mS/mm and 5.2 V, respectively. Furthermore, analysis indicated that PEALD-grown AlN significantly reduced the interface charges at dielectric/III-N interface (from 1.2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> to 8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for interface traps, and from 1.01 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> to 3.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> for fixed charges) and improved channel transport properties (the full-width at half-maximum of channel transconductance increased from 0.9 to 2.7 V), compared with ALD-grown Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , which could explain the differences of device characteristics.

Positive Shift in Threshold Voltage for Reactive-Ion- Sputtered Al2O3/AlInN/GaN MIS-HEMT

AlInN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) have been fabricated with reactive-ion-sputtered (RIS) Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as a gate dielectric. Significant reduction in the gate leakage current is achieved upon insertion of RIS-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> . MIS-HEMTs also show better transconductance, drain characteristics, and ION/IOFF ratio. Most interestingly, a positive shift in threshold voltage is observed for MIS-HEMTs indicating the presence of net negative charge at oxide-semiconductor interface. The origin and stability of the negative charge at the interface is discussed in this letter.

Fixed interface charges between AlGaN barrier and gate stack composed of in situ grown SiN and Al2O3 in AlGaN/GaN high electron mobility transistors with normally off capability

Using a generalized extraction method, the fixed charge density Nint at the interface between in situ deposited SiN and 5 nm thick AlGaN barrier is evaluated by measurements of threshold voltage Vth of an AlGaN/GaN metal insulator semiconductor high electron mobility transistor as a function of SiN thickness. The thickness of the originally deposited 50 nm thick SiN layer is reduced by dry etching. The extracted Nint is in the order of the AlGaN polarization charge density. The total removal of the in situ SiN cap leads to a complete depletion of the channel region resulting in Vth = +1 V. Fabrication of a gate stack with Al2O3 as a second cap layer, deposited on top of the in situ SiN, is not introducing additional fixed charges at the SiN/Al2O3 interface.

Improvement of $V_{\rm th}$ Instability in Normally-Off GaN MIS-HEMTs Employing ${\rm PEALD}\hbox{-}{\rm SiN}_{\rm x}$ as an Interfacial Layer

In this letter, reduction of threshold voltage instability in gate recessed normally-off GaN metal insulator semiconductor high electron mobility transistors with SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> gate insulator was investigated. A plasma enhanced atomic layer deposition technique was successfully employed for very thin SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (5 nm) as an interfacial layer. The hysteresis and drift of threshold voltage in transfer curve and the forward biased gate leakage current were effectively reduced.

Effect of Atomic-Layer-Deposition Method on Threshold Voltage Shift in AlGaN/GaN Metal–Insulator–Semiconductor High Electron Mobility Transistors

We have investigated the mechanism for threshold voltage (Vth) shift of AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) for power applications. In this study, atomic layer deposited (ALD)-Al2O3 was used in AlGaN/GaN MIS-HEMTs as gate insulator films, and we focused on plasma-induced damages at the GaN/Al2O3 interface, when O2 plasma was used as the oxidant source for the ALD method. We clarified that the deep trap sites which were located around 2.58–3.26 eV from the conduction band edge were generated in the oxidized-GaN layer at the GaN/Al2O3 interface due to plasma-induced damages, and this caused the Vth shift when using O2 plasma. Therefore, we controlled the initial oxidant source, and demonstrated the reductions in the Vth shift and the gate leakage current by applying hybrid–Al2O3 structure (lower H2O vapor–Al2O3/upper O2 plasma–Al2O3) for AlGaN/GaN MIS-HEMTs.

High permittivity cerium oxide thin films on AlGaN/GaN heterostructures

Cerium oxide (CeO2) thin films have been grown by metal-organic chemical vapor deposition on AlGaN/GaN heterostructures and their insulating properties as gate dielectric layer have been explored. The deposited thin films have been found to be textured on the GaN based heterostructures and exhibited a permittivity of 26. This high permittivity value and large band gap are certainly advantageous with respect to other reported materials for the metal insulator semiconductor high electron mobility transistor application. The reduced leakage current density clearly suggests that these CeO2 films are very promising as gate dielectric for AlGaN/GaN transistors low power consumption technology.

Low gate interface traps AlGaN/GaN HEMTs using a lattice matched ZrZnO transparent gate design

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) using a radio-frequency magnetron sputtered ZrZnO transparent oxide layer as a gate insulator are investigated and compared with traditional GaN HEMTs. A negligible hysteresis voltage shift in the C–V curves is seen, from 0.09V to 0.36V, as the thickness of ZrZnO films increases. The composition of ZrZnO at different annealing temperatures is observed using X-ray photoelectron spectroscopy (XPS). The ZrZnO thin film achieves good thermal stability after 600°C, 700°C and 800°C post-deposition annealing (PDA) because of its high binding energy. Based on the interface trap density analysis, Dit has a value of 2.663×1012cm−2/eV for 10-nm-thick ZrZnO-gate HEMTs and demonstrates better interlayer characteristics, which results in a better slopes for the Ids degradation (5.75×10−1mA/mmK−1) for operation from 77K to 300K. The 10-nm-thick ZrZnO-gate device also exhibits a flat and a stable 1/f noise, as VGS–Vth, and at various operating temperatures. Therefore, ZrZnO has good potential for use as the transparent film for a gate insulator that improves the GaN-based FET threshold voltage and improves the number of surface defects at various operating temperatures.

Threshold Voltage Instability in Al2O3/GaN/AlGaN/GaN Metal–Insulator–Semiconductor High-Electron Mobility Transistors

The threshold voltage (Vth) instability in GaN-based metal–insulator–semiconductor high-electron mobility transistors (MIS-HEMTs) with 15-nm atomic-layer-deposited (ALD) Al2O3 as gate dielectrics is systematically investigated by dc current–voltage (I–V), high-frequency capacitance–voltage (C–V) (HFCV), and quasi-static C–V (QSCV) characterizations. Both Al2O3/GaN/AlGaN/GaN MIS diode and GaN/AlGaN/GaN Schottky diode only exhibit tiny threshold-voltage hysteresis (ΔVth) (<10 mV) in double-mode (up and down sweep) HFCV characteristics as the maximum forward bias (VFmax) during the sweep is set to 0 V, while an apparent ΔVth (as large as 0.9 V) emerges as VFmax is increased to +5 V for the MIS diode. The stability of Vth in the corresponding MIS-HEMTs is thus studied by increasing the maximum VGS (VGSmax) in the measurement of transfer characteristics. Significant positive Vth shift occurred once the VGSmax exceeds +1 V, while such Vth-instability is still absent in Schottky-gate AlGaN/GaN HEMTs. It is suggested that the acceptor-like deep states at Al2O3/GaN interface account for the Vth-instability in Al2O3/GaN/AlGaN/GaN MIS-HEMTs. As the filling and emission processes of these interface states are slow, they are successfully captured by low-frequency QSCV techniques.

Threshold Voltage Instability in Al2O3/GaN/AlGaN/GaN Metal–Insulator–Semiconductor High-Electron Mobility Transistors

The threshold voltage (Vth) instability in GaN-based metal–insulator–semiconductor high-electron mobility transistors (MIS-HEMTs) with 15-nm atomic-layer-deposited (ALD) Al2O3 as gate dielectrics is systematically investigated by dc current–voltage (I–V), high-frequency capacitance–voltage (C–V) (HFCV), and quasi-static C–V (QSCV) characterizations. Both Al2O3/GaN/AlGaN/GaN MIS diode and GaN/AlGaN/GaN Schottky diode only exhibit tiny threshold-voltage hysteresis (ΔVth) (<10 mV) in double-mode (up and down sweep) HFCV characteristics as the maximum forward bias (VFmax) during the sweep is set to 0 V, while an apparent ΔVth (as large as 0.9 V) emerges as VFmax is increased to +5 V for the MIS diode. The stability of Vth in the corresponding MIS-HEMTs is thus studied by increasing the maximum VGS (VGSmax) in the measurement of transfer characteristics. Significant positive Vth shift occurred once the VGSmax exceeds +1 V, while such Vth-instability is still absent in Schottky-gate AlGaN/GaN HEMTs. It is suggested that the acceptor-like deep states at Al2O3/GaN interface account for the Vth-instability in Al2O3/GaN/AlGaN/GaN MIS-HEMTs. As the filling and emission processes of these interface states are slow, they are successfully captured by low-frequency QSCV techniques.

Characterization of Al2O3/GaN/AlGaN/GaN metal—insulator—semiconductor high electron mobility transistors with different gate recess depths

In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal—insulator—semiconductor (MIS) high electron mobility transistors (HEMTs), we demonstrate better performances of recessed-gate Al2O3 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine-based AlGaN etching with three etching times (15 s, 17 s and 19 s). The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of AlGaN/GaN HEMT. Through the recessed-gate etching, the transconductance increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with τit = (0.20−1.59) μs and Dit = (0.55−1.08) × 1012 cm−2 · eV−1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AlGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time (15 s in this paper) can enhance the performances of MIS-HEMTs effectively.

AlGaN/GaN MIS-HEMT using NbAlO dielectric layer grown by atomic layer deposition

We present an AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) with an NbAlO high-k dielectric deposited by atomic layer deposition (ALD). Surface morphology of samples are observed by atomic force microscopy (AFM), indicating that the ALD NbAlO has an excellent-property surface. Moreover, the sharp transition from depletion to accumulation in capacitance–voltage (C–V)curse of MIS-HEMT demonstrates the high quality bulk and interface properties of NbAlO on AlGaN. The fabricated MIS-HEMT with a gate length of 0.5 μm exhibits a maximum drain current of 960 mA/mm, and the reverse gate leakage current is almost 3 orders of magnitude lower than that of reference HEMT. Based on the improved direct-current operation, the NbAlO can be considered to be a potential gate oxide comparable to other dielectric insulators.

The reduction of gate leakage of AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors by N2 plasma pretreatment

Electrical performance of an AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MISHEMT) with Al2O3 as the gate insulator layers indicated that the gate leakage was decreased by two orders of magnitude after the Al2O3/AlGaN interface was pretreated by N2 plasma. The Al2O3 thin film was deposited by atomic layer deposition (ALD). Effects of N2 plasma pretreatment on the electrical and structural properties of the Al2O3/AlGaN interface were investigated by C–V measurements, high-resolution transmission electron microscopy (HRTEM) and x-ray photoelectron spectroscopy (XPS). The C–V measurements showed that the electrical property was improved after N2 plasma pretreatment, HRTEM measurements indicated that the thickness of an interfacial layer was reduced. XPS analysis confirmed that AlGaN oxides are greatly decreased during N2 plasma pretreatment.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end ( Γ -gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.