Input Data Rate Research Articles

0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking

A near-threshold forwarded-clock I/O receiver architecture is presented. In the proposed receiver, the majority of the circuitry is designed to operate in the near-threshold region at 0.6 V supply to save power, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at the nominal 1 V supply. To ensure the quantizers are working properly with this low supply, a 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism. A novel low-power super-harmonic injection-locked ring oscillator is proposed to generate deskewable symmetric multi-phase local clock phases. The relative performance impact of including a per-data lane sample-and-hold (S/H) to improve quantizer aperture time at low voltage is demonstrated with two receiver prototypes fabricated in a 65 nm CMOS technology. Including the amortized power of global clock distribution, the receiver without S/H consumes 1.3 mW and the one with S/H consumes 2 mW at an 8 Gb/s input data rate, which converts to 0.163 pJ/bit and 0.25 pJ/bit, respectively. Measurement results show both receivers get BER <; 10-12 across a 20-cm FR4 PCB channel.

5 Gb/s 2:1 fully-integrated full-rate multiplexer with on-chip clock generation circuit in 0.18-μm CMOS

A 5 Gb/s 2:1 full-rate multiplexer (MUX) has been designed and fabricated in SMIC 0.18-μm CMOS process. A clock generation circuit (CGC) is also integrated to provide the MUX with both 2.5 and 5-GHz clock signals. The CGC is realized by a clock and data recovery (CDR) loop with a divide-by-2 frequency divider embedded in, where the two required clocks are obtained after and before the divider, respectively. In addition, the phase relation between data and clock is assured automatically by CDR feedback loop and the precise layout. The whole chip area is 812 × 675 μm, including pads. At a single supply voltage of 1.8 V, the total power consumption is 162 mW with an input sensitivity of <25 mV and a single-ended output swing of above 300 mV. And due to the full-rate architecture, the pulse width distortion (PWD) with multiplexed data is removed. The measured results also show that the circuit can work reliably at any input data rate between 2.46 and 2.9 Gb/s without need for external components, reference clock, or manual phase alignment between data and clock.

Low-complexity high-throughput decoding architecture for convolutional codes

Sequential decoding can achieve a very low computational complexity and short decoding delay when the signal-to-noise ratio (SNR) is relatively high. In this article, a low-complexity high-throughput decoding architecture based on a sequential decoding algorithm is proposed for convolutional codes. Parallel Fano decoders are scheduled to the codewords in parallel input buffers according to buffer occupancy, so that the processing capabilities of the Fano decoders can be fully utilized, resulting in high decoding throughput. A discrete time Markov chain (DTMC) model is proposed to analyze the decoding architecture. The relationship between the input data rate, the clock speed of the decoder and the input buffer size can be easily established via the DTMC model. Different scheduling schemes and decoding modes are proposed and compared. The novel high-throughput decoding architecture is shown to incur 3-10% of the computational complexity of Viterbi decoding at a relatively high SNR.

Optimised non-uniform biasing technique for a high-speed optical router to achieve uniform semiconductor optical amplifier gain

In this study, we propose applying non-uniform biasing current technique to improve the gain uniformity of the semiconductor optical amplifier (SOA) for high-speed optical routers. The output pulses will have high-gain deviation because of the high-speed input pulses and the slow SOA gain recovery, thus resulting in a high system power penalty. The theoretical SOA operation principle is demonstrated using a segmentation model that employs the rate and propagation equations with third-order gain coefficients. The impact of the bias current on the SOA gain responses owing to the input packet of 1 mW input Gaussian pulses at a wavelength of 1550 nm is analysed in order to optimise the proposed non-uniform bias current shape. The uniform and the optimised non-uniform bias current techniques are investigated in terms of the SOA gain uniformity and the average output power for high-speed data rates from 10 to 160 Gb/s. The impact of the average bias current applied to the SOA on the non-uniform shape is also investigated at all input data rates. Results obtained show a significant improvement in the gain standard deviation of 4.6, 6.3, 8.7, 10.1 and 10.2 dB for the data rates of 10, 20, 40, 80 and 160 Gb/s, respectively, when applying 150 mA average non-uniform biasing and these values reaches 15.2, 16.3, 17.7, 18 and 17.4 dB at 200 mA. The proposed technique also offers an increase in the average output power for the input pulses compared with uniform biasing.

Shared execution strategy for neighbor-based pattern mining requests over streaming windows

In diverse applications ranging from stock trading to traffic monitoring, data streams are continuously monitored by multiple analysts for extracting patterns of interest in real time. These analysts often submit similar pattern mining requests yet customized with different parameter settings. In this work, we present shared execution strategies for processing a large number of neighbor-based pattern mining requests of the same type yet with arbitrary parameter settings. Such neighbor-based pattern mining requests cover a broad range of popular mining query types, including detection of clusters, outliers, and nearest neighbors. Given the high algorithmic complexity of the mining process, serving multiple such queries in a single system is extremely resource intensive. The naive method of detecting and maintaining patterns for different queries independently is often infeasible in practice, as its demands on system resources increase dramatically with the cardinality of the query workload. In order to maximize the efficiency of the system resource utilization for executing multiple queries simultaneously, we analyze the commonalities of the neighbor-based pattern mining queries, and identify several general optimization principles which lead to significant system resource sharing among multiple queries. In particular, as a preliminary sharing effort, we observe that the computation needed for the range query searches (the process of searching the neighbors for each object) can be shared among multiple queries and thus saves the CPU consumption. Then we analyze the interrelations between the patterns identified by queries with different parameters settings, including both pattern-specific and window-specific parameters. For that, we first introduce an incremental pattern representation, which represents the patterns identified by queries with different pattern-specific parameters within a single compact structure. This enables integrated pattern maintenance for multiple queries. Second, by leveraging the potential overlaps among sliding windows, we propose a metaquery strategy which utilizes a single query to answer multiple queries with different window-specific parameters. By combining these three techniques, namely the range query search sharing, integrated pattern maintenance, and metaquery strategy, our framework realizes fully shared execution of multiple queries with arbitrary parameter settings. It achieves significant savings of computational and memory resources due to shared execution. Our comprehensive experimental study, using real data streams from domains of stock trades and moving object monitoring, demonstrates that our solution is significantly faster than the independent execution strategy, while using only a small portion of memory space compared to the independent execution. We also show that our solution scales in handling large numbers of queries in the order of hundreds or even thousands under high input data rates.

Realization of All-Optical Digital Comparator Using Single Mode Fabry–Pérot Laser Diodes

A two-bit all-optical digital comparator using single mode Fabry-Pérot laser diodes (SMFP-LDs) at an input data rate of 10 Gbps is proposed and demonstrated. All-optical comparator is demonstrated using cascaded logic units which are based on injection locking, multi-input injection locking and supporting beam principles for suppressing the dominant mode of SMFP-LDs. Digital comparators are the key components for the decision making circuits, the integral part of the arithmetic and logical units of optical data processors. The output performance of the proposed all-optical comparator is verified with output waveform, rising-falling time, output eye diagram, and bit error rate (BER) at 10 Gbps input Non Return to Zero (NRZ) PRBS of 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 signal. The rising/falling time of about 47 ps, clear output waveforms, and clear output eye diagram with an extinction ratio of about 12 dB are obtained. A maximum power penalty of 1.3 dB is measured at a BER of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> .

Realization of all-optical multi-logic functions and a digital adder with input beam power management for multi-input injection locking in a single-mode Fabry-Pérot laser diode

We propose a novel idea for the suppression of the dominant mode of the single-mode Fabry-Pérot laser diode (SMFP-LD) to realize all-optical multi-logic functions and a digital adder. The basic principle of the proposed scheme is the power management of input beams to suppress the dominant mode of the SMFP-LD for multi-input injection locking. The proposed principle is explained and implemented to realize all-optical multi-logic functions and a digital adder at an input data rate of 10 Gbps. A clear eye opening with an extinction ratio of about 12 dB and a rising-falling time of less than 40 ps are observed at the outputs. The bit error rate (BER) performance is measured for all logic gates and half adder operation. We found there is no BER floor up to BER of 10(-12) and the maximum power penalty of about 1.2 dB at a BER of 10(-9).

The study of enhanced earth observations on a satellite image chain

The Multi-Spectral Camera (MSC) on the KOrea Multi-Propose SATellite (KOMPSAT)-2 was developed and launched as a main payload to provide a One(1) m panchromatic image and four(4) band four(4) m multi-spectral images at an altitude of 685 km covering a swath width of 15 km. These images, archived around the world, are a useful resource for space applications in agriculture, cartography, geology, forestry, regional planning, surveillance, and national security. The image quality of KOMPSAT-2 depends upon its image chain, which is comprised of an on-board system in the satellite and a processing system at the ground station. Therefore, in this study we determine the factors that have a major impact on the image quality through an investigation of the entire image chain. Consequently, two methods, involving a compression algorithm and a deconvolution technique, were determined as having a significant influence on the KOMPSAT-2 image quality. The compression algorithm of KOMPSAT-2 is rate-controlled JPEG-like algorithm that controls the mismatch between the input and output data rate. The ability to control the input/output data rate may be useful during the operation of the satellite but can also lower the overall image quality. The deconvolution technique may increase the sharpness of images, but it can also amplify the image noise level. Therefore, we propose methods of wavelet-based compression and denoising as an alternative to currently existing algorithms. Satisfactory results were obtained through experimentation with these two algorithms, and they are expected to be successfully implemented into the future KOMPSAT series to yield high-quality images for enhanced earth observation.

A study on metadata elements for web‐based reference resources system developed through usability testing

PurposeTo propose correct metadata elements, it was deemed necessary to close the gap between the perception of metadata creators and data creators through a user behavior analysis. This study aims to improve metadata elements of web‐based reference resources.Design/methodology/approachThe study employed three types of surveys: behavior analysis of metadata creators, perception analysis of users, and system satisfaction. For analysis of metadata creators, the study examined data fields where metadata were recorded among metadata elements of reference resources. For user awareness analysis, respondents were asked to answer the necessity of 17 elements after they actually had entered data and to recommend other necessary elements. Finally, system satisfaction survey was followed.FindingsAs a result, first, it was found that the respondents recognized five elements: contributor, source, data, format, and relation as necessary input elements, which in practice had not been well recorded in real operating systems. The usability test also found that users entered the five elements more than other elements. Second, the first survey experience did not impact the second survey response. It was found that previous experience of system use had significantly impacted respondents' recognition of necessary metadata elements. It was also found that data input rate in the data input test had a significant influence on the change in the perception regarding necessary metadata. Third, the most chosen elements when searching for reference resources were found to be title, subject, description, and creator, in order of frequency. Fourth, respondents were surveyed on their satisfaction regarding nine questions after they had used a system (factor analysis). In this analysis, it was found that the users' satisfaction was relatively high in system usefulness, ease of system use, ease of understanding information, and sufficiency of metadata elements.Originality/valueSince the 1990s, studies on the development of metadata elements for web‐based reference resources have been made and applied to the real world. Ever since, many reference resources web sites have been developed. However, it was found that no standard metadata format was built for web‐based reference resources and each website provided its own item to the minimal degree. The result of this study can provide a standardized and more consistent service for web‐based resource.

A Dynamic Self-Adjusted Buffering Mechanism for Peer-to-Peer Real-Time Streaming

Multimedia live stream multicasting and on-line real-time applications are popular recently. Real-time multicast system can use peer-to-peer technology to keep stability and scalability without any additional support from the underneath network or a server. Our proposed scheme focuses on the mesh architecture of peer-to-peer live streaming system and experiments with the buffering mechanisms. We design the dynamic buffer to substitute the traditional fixed buffer. According to the existing measurements and our simulation results, using the traditional static buffer in a dynamic peer-to-peer environment has a limit of improving quality of service. In our proposed method, the buffering mechanism can adjust buffer to avoid the frozen or reboot of streaming based on the input data rate. A self-adjusted buffer control can be suitable for the violently dynamic peer-to-peer environment. Without any support of infrastructure and modification of peer-to-peer protocols, our proposed scheme can be workable in any chunk-based peer-to-peer streaming delivery. Hence, our proposed dynamic buffering mechanism varies the existing peer-to- peer live streaming system less to improve quality of experience more.

5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump

A 5-Gb/s current-mode peak detector is proposed using a V-I converter, a current comparator, and a charge pump with three states (i.e., UP, DN, and HOLD). It eliminates the problem that a voltage error increases with an input data rate in a conventional peak detector circuit. In this brief, the voltage error between the measured input and output peak voltages is smaller than 5% for a pseudo-random binary sequence signal at a data rate up to 5 Gb/s, with an input voltage swing up to ±500 mV and an input common-mode voltage of 0.9 V. A chip fabricated in a 0.18-μm process gives the power consumption of 2.7 mW at a voltage supply of 1.8 V and a chip area of 150 μm × 120 μm.

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

A high-throughput low-latency digital finite impulse response (FIR) filter has been designed for use in partial-response maximum-likelihood (PRML) read channels of modern disk drives. The filter is a hybrid synchronous-asynchronous design. The speed-critical portion of the filter is designed as a high-performance asynchronous pipeline sandwiched between synchronous input and output portions, making it possible for the entire filter to be embedded within a clocked system. A novel feature of the filter is that the degree of pipelining is dynamically variable, depending upon the input data rate. This feature is critical in obtaining a very low filter latency throughout the range of operating frequencies. The filter is a ten-tap six-bit FIR filter, fabricated in a 0.18-μm CMOS process. Resulting chips were fully functional over a wide range of supply voltages, and exhibited throughputs of over 1.3 giga-items/s, and latencies of 2-5 clock cycles. Interestingly, the filter throughput was limited by the synchronous portion of the chip; the internal asynchronous pipeline was estimated to be capable of significantly higher throughputs, around 1.8 giga-items/s. More importantly though, the adaptively pipelined nature of the filter allows it to offer a worst-case latency of only 10 ns, which is half the worst-case latency of the best previously reported comparable fully-synchronous implementation by Rylov et al.

LHCb Silicon Tracker DAQ and ECS Online Systems

The LHCb experiment at CERN is designed to perform precision measurements of b quark decays. The Silicon Tracker plays a crucial role in reconstructing particle trajectories and consists of two silicon micro-strip detectors, the Tracker Turicensis and the Inner Tracker. The radiation environment and the magnetic field represent new challenges for the implementation of the Experiment Control System (ECS) and the data acquisition (DAQ). The DAQ has to deal with ~272 000 analog read-out channels and real-time DAQ at a rate of ~ 1.1 MHz with data processing at the Trigger Electronics and L1 (TELL1) board level. The TELL1 real-time algorithms for clustering thresholds and other computations run on dedicated FPGAs. After data processing the total throughput amounts to about 6.4 GB from an input data rate of ~ 337 GB per second. The ECS is based on the hierarchical finite state machine paradigm and allows distributed control access and multi-platform use. The ECS is able to control and monitor the detector hardware infrastructure (power supplies, DAQ electronics ...) as well as monitor the environmental parameters. It can also take automated actions on warnings or alarms. Finally a completely independent, hardware based safety system ensures the detector safe operation.

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology. The Pottbäcker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440 μm2, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of −111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

A 5-Gb/s 2:1 MUX (multiplexer) with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment (APA), has been designed and fabricated in SMIC's 0.18 μm CMOS technology. The chip area is 670 × 780 μm2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

A shared execution strategy for multiple pattern mining requests over streaming data

In diverse applications ranging from stock trading to traffic monitoring, popular data streams are typically monitored by multiple analysts for patterns of interest. These analysts may submit similar pattern mining requests, such as cluster detection queries, yet customized with different parameter settings. In this work, we present an efficient shared execution strategy for processing a large number of density-based cluster detection queries with arbitrary parameter settings. Given the high algorithmic complexity of the clustering process and the real-time responsiveness required by streaming applications, serving multiple such queries in a single system is extremely resource intensive. The naive method of detecting and maintaining clusters for different queries independently is often in-feasible in practice, as its demands on system resources increase dramatically with the cardinality of the query workload. To overcome this, we analyze the interrelations between the cluster sets identified by queries with different parameters settings, including both pattern-specific and window-specific parameters. We introduce the notion of the growth property among the cluster sets identified by different queries, and characterize the conditions under which it holds. By exploiting this growth property we propose a uniform solution, called Chandi , which represents identified cluster sets as one single compact structure and performs integrated maintenance on them -- resulting in significant sharing of computational and memory resources. Our comprehensive experimental study, using real data streams from domains of stock trades and moving object monitoring, demonstrates that Chandi is on average four times faster than the best alternative methods, while using 85% less memory space in our test cases. It also shows that Chandi scales in handling large numbers of queries on the order of hundreds or even thousands under high input data rates.

Embedded fuzzy expert system for Adaptive Weighted Fair Queueing

This paper introduces an embedded fuzzy expert system for Adaptive Weighted Fair Queueing (AWFQ) located in the network traffic router to update weights for output queues. WFQ algorithm allows differentiated service for traffic classes according to Quality of Service (QoS) requirements. Link sharing and packet scheduling methods are the most critical factors when guaranteeing QoS. There are many different scheduling mechanisms but adequate and adaptive QoS aware scheduling solutions are still in a phase of development due to the rapid growth of multimedia in the Internet. The proposed AWFQ model in this work simplifies the link sharing to two service classes: one for UDP and another for TCP. The implementation of the model is based on adaptive change of weight coefficients that determine the amount of allowed bandwidth for the service class. New weight coefficients are calculated periodically on routers according to developed embedded fuzzy expert system. It is shown through simulations that the AWFQ model is more stable and reacts faster to different traffic states than the traditional WFQ scheduler. The embedded expert system adjusts the weights of AWFQ with two parameters that are based on the share of the UDP and TCP input traffic data rate and the change of the share of the UDP and TCP input data rate.

A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications

In this paper, a highly parallel deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD@60fps sequences at less than 100MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24×64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130nm process, the architecture costs a gate count of 30.2k, which is competitive considering its high performance.

Injection-Locked Clock Recovery Using a Multiplexed Oscillator for Half-Rate Data-Recovered Applications

An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-μm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55 dBc/Hz at 100-kHz offset and -129.58 dBc/Hz at 1-MMz offset with ±25 MHz lock range, while operating at the input data rate of 1.55 Gb/s.

Congestion Detection in the European Internet

In this paper we present a study about the utilization of one-way delay measurements to detect and characterize network congestion in the european Internet. The experiments have been made using the ETOMIC platform that allows one-way delay measurement with high precision timestamps. We have found a peculiar router behaviour in which the bottleneck is not the available bandwidth but it is the packet processing power of the router (backplane and CPU constraints). This router has been characterized with several network parameters. Some of them are the dependency of this limitation with the input data rate in packets per second, the size of burst packet losses measured in packets or time and the absence of specific scheduling algorithms in the router that could affect to larger flows.