Initial Frequency Error Research Articles

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

2.45 GHz PLL 설계 및 주파수와 위상 오차 분석

This paper concerns a PLL design operating at 2.45 GHz and a method for checking frequency and phase errors over time. During the design process, the design method had a natural frequency (ωn) of 33,800 rad/s and a damping ratio (ζ) of 0.53 according to a generally known method of designing a Type-II PLL. Owing to production, when the PLL of VCO(voltage controlled oscillator) was added, phase noise decreased by 22 dB and 58 dB at 10 kHz and 150 kHz offset, respectively. In the experimental stage of the characteristics, the result of calculating the interval between the peak points of the initial frequency error in the circuit designed using MATLAB program was 100 μs, and a similar result was obtained when the measurement was taken using an oscilloscope. It was assumed that the highest point of the output frequency was 2.5 GHz through the change of the tuning voltage measured using the oscilloscope, and it was verified by using mixer that a maximum output frequency was 2.504 GHz. Additionally, for the compensation of the phase error at the comparison frequency, we obtained values of 12.7° and 8.93° using an oscilloscope and a PSpice, respectively, after fixing the frequency. The error between the two measurements was 29.7 %, and it was determined to be due to approximation in the integration process and the fluctuation of the tuning voltage.

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-$\mu$ s Settling Time for Multi-ISM-Band ULP Radios

This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively shorten the calibration time, while the split coarse-fine PLL loops with different loop bandwidths accelerate the loop settling speed. The employed ring VCO (RVCO) aids to extend the frequency tuning range and generate multi-phase outputs. Prototyped in 65-nm CMOS, the DPLL consumes 1.2–2.4 mW over a wide frequency locking range of 68.3% (1.3–2.65 GHz) and occupies a die area of 0.12 mm2. The settling time measures $8~\mu \text{s}$ at an 82-MHz initial frequency error.

Initial frequency refining algorithm for pull‐in process with an auxiliary DLL in pseudolite receiver

Pulsed time division multiple access is recommended for psedudolite satellite signal to eliminate the near-far effect, which is different from global navigation satellite system signal design. However, in this case, the initial frequency bias obtained from acquisition is not precise enough for the carrier tracking loop to converge due to the signal's pulse modulation, as the rolling-off of auto-correlation function is insensitive to slight frequency changes. This Letter proposes an approach to narrowing the initial frequency error by mapping from code Doppler to carrier Doppler, in which the former one can be obtained from a delay lock loop (DLL). Simulation results demonstrate the validity of the proposed method in the initialisation of frequency pull-in process owing to the fixed proportion existed in the code and carrier Doppler.

Doppler Frequency Estimation in GNSS Receivers Based on Double FFT

This paper presents an innovative Doppler frequency estimation technique, which is particularly suited for global navigation satellite system (GNSS) receivers operating in vehicular scenarios. Mass-market and commercial navigation devices are being increasingly exploited for in-car navigation and for vehicular applications based on positioning. However, the low computational burden that can be afforded by such devices requires the implementation of low-complexity algorithms, allowing real-time and on-demand processing. This is the case, for instance, for open-loop architectures and of maximum likelihood estimation (MLE)-based techniques, which estimate the frequency component of the GNSS signal through a discrete Fourier transform. A state of the art of such methods is first carried out, outlining their benefits, regarding robustness and stability, and their limitations, mainly concerning the accuracy. Successively, an innovative refinement technique is introduced, based on the computation of a frequency correction term. Further enhancements are then proposed to solve particular issues, such as the estimation of the sign of the correction term and the impact of the initial frequency error. In particular, zero forcing and a double fast Fourier transform (FFT), which represent the main contribution of this paper, are proposed to increase the accuracy without increasing the computational load. A complete analytical derivation and theoretical description is provided, along with a detailed performance assessment. Finally, a performance comparison with existing techniques and with the Cramer–Rao lower bound (CRLB) for frequency estimation is given, confirming the excellent behavior of the proposed algorithm for the signal conditions and strengths that are typical of a vehicular scenario and in the presence of frequent interruptions.

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35μm CMOS process, with a supply voltage of 3.3V.

Robust Read Channel System Directly Processing Asynchronous Sampling Data

In this study, we describe a robust read channel employing a novel timing recovery system and a unique Viterbi detector which extracts channel timing and channel data directly from asynchronous sampling data. The timing recovery system in the proposed read channel has feed-forward architecture and consists entirely of digital circuits. Thus, it enables robust timing recovery at high-speed and has no performance deterioration caused by variations in analog circuits. The Viterbi detector not only detects maximum-likelihood data using a reference level generator, but also transforms asynchronous data into pseudosynchronous data using two clocks, such as an asynchronous clock generated by a frequency synthesizer and a pseudosynchronous clock generated by a timing detector. The proposed read channel has achieved a constant and fast frequency acquisition time against initial frequency error and has improved its bit error rate performance. This robust read channel system can be used for high-speed signal processing and LSIs using nanometer-scale semiconductor processes.

Frequency synchronization for digital audio broadcasting

In DAB, a coarse frequency offset estimation algorithm has to provide an initial frequency error estimate, which is sufficiently accurate for the subsequent fine frequency synchronization algorithm to operate reliably. We present a coarse frequency offset estimation technique using the minimum energy detection scheme for an OFDM-based transmission system. It has been shown that the proposed algorithm has high robustness against a large range of symbol timing offsets with a low complexity.

Simple switching technique for fast PLL frequency synthesisers

For PLL frequency synthesisers a simple circuit for a deadbeat control strategy is given; with the loop damping removed the initial frequency error is measured over half a cycle of loop oscillation, and then a corrective step of half this is made and the damping replaced.

Improving Frequency Acquisition of a Costas Loop

A Costas loop for tracking a BPSK signal does not acquire when the initial frequency error is comparable to the loop bandwidth. This paper describes methods for deriving control proportional to frequency error so as to improve the frequency acquisition capability by an AFC augmentation. A composite AFC/Costas loop is realized by combining the individual loops. Pull-in from a frequency error much greater than the Costas loop bandwidth is now feasible. The increase in phase error due to the AFC capability is evaluated by a linearized analysis. If the bandwidth of the AFC portion is sufficiently narrow, the degradation is negligible. Improved frequency acquisition can also be realized by a simple modification of the Costas loop to remove the low-pass filter on the quadrature phase detector channel, with negligible degradation to phase tracking.

Second-Order Phase-Lock-Loop Acquisition Time in the Presence of Narrow-Band Gaussian Noise

Phase-lock acquisition time of a perfect (proportional plus integral control) second-order phase-lock loop (PLL) in the presence of narrow-band Gaussian noise is studied by means of computer simulation. 100 nonoverlapping sequences of pseudorandom noise are generated. In the presence of each noise sequence, phase-lock acquisition is simulated at each of five pairs of initial phase error φ 0 and initial frequency error φ 0 . For each (\phi_{0},\phi_{0}) with each noise sequence, phase-lock acquisition is simulated at nine different ratios of signal-to-noise energy at the PLL input. If the PLL phase detectors were linear rather than sinusoidal, the range of PLL output signal-to-noise ratios simulated would extend from 4 to 50 dB. The 4500 acquisitions of phase lock simulated are represented by 45 distribution functions that explicitly indicate the effect of PLL output signal-to-noise ratio on PLL phase-lock acquisition time.

A Simple Technique for Improving the Pull-in Capability of Phase-Lock Loops

This paper presents a simple technique for improving the pull-in capability of phase-lock loops. This technique, called derived rate rejection or DRR, differs from those which use an external AFC loop in simplicity of implementation and design rationale, although the end result is the same. If, as is usually the case, a coherent detector accompanies the phase-lock loop, the implementation of the DRR technique requires only the addition of a switch. The switching logic results from a superficial consideration of the nonlinear equation for the phase-lock loop and its solution in the phase plane. The switch does not affect the normal behavior of the loop after lock has been attained. Results of computer studies show the improvement realizable for the following configurations: 1) Proportional-plus-integral control. 2) Proportional-plus-imperfect integral control. For an initial frequency error of five times the linearized phase lock-loop natural frequency, the improvement in pull-in time is a factor of two. For an initial frequency error of ten times the phase-lock loop natural frequency, the improvement in pull-in time is a factor of ten.

Unlock Characteristics of the Optimum Type II Phase-Locked Loop

This paper describes a study of the statistical unlock characteristics of the commonly used optimum type II phase-locked loop taking into account the nonlinearity of the phase detector. The unlock behavior is investigated by simulating the loop with random noise inputs on a digital computer. A criterion of loop unlock is evolved using the phase portrait of the loop and consists of crossing of separatrices by loop error and a measure of loop error rate. Approximately 100 statistically independent trials were made for each of a number of combinations of initial phase error, initial frequency error, and input noise amplitude. From these computer runs, cumulative frequency distributions of unlock time and curves of mean time to unlock were obtained and are presented. The phase portrait of the loop containing time information also is included in the paper, along with a plot of capture characteristics for large initial frequency offsets.

The Lock-in Performance of an AEC Circuit

The lock-in condition of the phase-detector reactance tube-controlled oscillator afc system has been investigated. For the case of RC coupling between phase detector and the reactance tube, an explicit relation is obtained for the lock-in condition which involves the filter time constant, the initial frequency error, the phase detector constant and the reactance tube controlled oscillator sensitivity constant.