InGaAs MOSFETs Research Articles

Geometrical Magnetoresistance as a Tool for Carrier Mobility Extraction in InGaAs MOSFETs

Geometrical Magnetoresistance as a Tool for Carrier Mobility Extraction in InGaAs MOSFETs

Inversion-Mode In0.53Ga0.47 As MOSFET with f T = 275 GHz and high V eff

In this work, we present an inversion-mode In0.53Ga0.47As planar MOSFETs with current gain cutoff frequency (f T) = 275 GHz and maximum oscillation frequency (f max) = 75 GHz. To the best of our knowledge, this is the highest f T value among all the reported inversion-mode InGaAs MOSFETs. Meanwhile, peak transconductance (g m) shows 1035 (μS/μm). These extraordinary properties are attributed to the N2 remote plasma treatment which results in excellent high-k/III-V interface quality. With the assistance of delay-time analysis, effective electron velocity (V eff) of 2.88 × 107(cm s–1) is extracted for a possible explanation of the observed record f T performance.

Cryogenic Characteristics of InGaAs MOSFET

We present an investigation of the temperature dependence of the current characteristic of a long-channel InGaAs quantum well MOSFET. A model is developed, which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density to accurately explain the measured data over all modes of operation. The increased effect of remote impurity scattering is associated with mobility degradation in the subthreshold region. The device has been characterized down to 13 K, with a minimum inverse subthreshold slope of 8 mV/dec and a maximum ON-state mobility of 6700 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> and with values of 75 mV/dec and 3000 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> at room temperature.

Study of scaling effect of ferroelectric gate stack in planar InGaAs MOSFET

AbstractNegative capacitance field effect transistors is found to be a promising option for low power VLSI devices in the advanced technology node. In this article, through extensive numerical simulation, we report the scaling effect of ferroelectric gate stack, channel thickness and gate length on electrostatic integrity, DC, analog and RF performance of InGaAs quantum well MOS transistor. The different DC and analog figure of merits such as on current (), switching ratio (), threshold voltage roll‐off, sub‐threshold swing (SS), trans‐conductance (), transconductance efficiency () of the test device has been analyzed for different ferroelectric layer thicknesses and compared with the baseline device. We have investigated RF performance such as gate capacitance, unity‐gain cut‐off frequency and small signal voltage gain of the device. Improvement in DC and analog figure of merits is proportional to the ferroelectric layer thickness. However, for higher values of ferroelectric thickness, the hysteresis effect gradually became prominent. MOS transistor with optimum ferroelectric layer thickness shows the negligible amount of threshold voltage roll‐off and improved transconductance‐frequency product compared to the baseline device. In presence of ferroelectric layer, the effect of channel thickness variation on device performance is reduced. The role of ferroelectric gate stack is found to be more prominent at shorter gate length.

Transparent Conductive Oxide (TCO) Gated Ingaas Mosfets for Front-Side Illuminated Short-Wave Infrared Detection

TCO gated InGaAs MOSFETs are demonstrated as a high responsivity and broadband short-wave infrared (SWIR) photodetector under front-side illumination (FSI). InGaAs MOSFET structures have many advantages for monolithic integration with optical communication devices with O, C, and L bands and Si-LSI.The TCO gated InGaAs MOSFETs were fabricated through the gate-last method as shown in Fig. (a) [1]. A 300-nm-thick p-type In0.53Ga0.47As layer was grown on an InP (001) wafer using MOCVD. After the deposition of a 10-nm-thick Al2O3 protection layer by ALD, the InGaAs active region was defined by chemical wet etching for mesa isolation. For the formation of the source/drain region, Si ions were implanted with 2×1014 cm-2 at 15 keV, followed by RTA at 450 °C for 10 min to achieve dopant activation. After splitting the Al2O3 protection layer, a 10-nm-thick Al2O3 gate oxide layer was deposited again. As TCO gate, Ce and H co-doped In2O3 (In2O3: Ce, H) with an electron mobility of ~160 cm2/V·s and a carrier density of ~ 2×1020 cm-3 were used [2, 3]. The amorphous TCO gate, which were deposited onto the Al2O3 layer using the ion plating method, were lifted off and crystallized by annealing at 250 °C for 30 min. Finally, Ti/Au formed for the S/D and gate contact after post-metallization annealing (PMA) at 250 °C for 30 min.The thin TCO films exhibited a very low specific contact resistance of 9.01 × 10-8 W·cm2 and a sheet resistance of 18.7W/sq. We confirmed the normal n-channel MOSFET operation with an I on/I off ratio of > 1×104. S.S. and D it values were 134 mV/dec. and 5.2 × 1012 eV-1cm-2, respectively. The peak G m was observed at V G= 0.5 V, and the extracted peak field-effect mobility was 620 cm2/V·s. The threshold voltage negatively shifted to -0.38 V, operating in enhancement mode owing to the work function of the TCO (4.2 eV), which is smaller than the Fermi level energy of p-type InGaAs (5.09 eV).Figure (b) shows the I D - V G characteristics of InGaAs MOSFETs at V G = 1 V in the dark and under illumination at the excitation wavelength of 1550 nm with an incident optical power of 5213 nW. SWIR light was illuminated in the channel area (L/W = 10 μm/10 μm) of TCO gated InGaAs MOSFET with a spot size of 10 μm. Under SWIR illumination, an increase in can be observed in the entire gate bias. Owing to the normally-on operation of the TCO gated InGaAs MOSFET, a photocurrent is detected even if the gate bias is 0 V. The photocurrent increased with the gate bias and reached the maximum in the vicinity of V G = 0.5 V, which corresponds to that of the maximum transconductance. The primary photo-response when the device is under illumination is known as the photovoltaic effect [4, 5]. The photo-generated holes move to the source region and accumulate at the potential barrier between the source and the channel. This results in the effective reduction of a potential barrier for electrons at the source edge. These phenomena lead to a decline in the threshold voltage of the MOSFET, which leads to the increase of the drain current. The threshold voltage of the TCO gated InGaAs MOSFETs in the dark was -0.35 V, and this value shifted to -0.45 V under illumination. Because is proportional to the mobility at the MOS interface, the improvement of the interface quality of the TCO/Al2O3/InGaAs MOS structures can enhance the sensitivity.Owing to the SWIR transparent TCO, we observed a responsivity of more than 1 A/W in the range of 1000 nm to 1800 nm, which includes the entire optical communication wavelength bands (1260–1625 nm). Because the maximum sensitivity of InGaAs photodiode was approximately 1 A/W at approximately 1550 nm [6], it is demonstrated that TCO gated InGaAs MOSFETs is a highly sensitive device in the SWIR region owing to the gain mechanism in the photoFETs.[1] T. Maeda, et al., Appl. Phys. Lett., 119, 192101 (2021).[2] T. Koida, et al., Status Solidi A, 215, 1700506 (2018).[3] T. Koida, et al., Status Solidi A, 218, 2000487 (2021).[5] Y. Takanashi, et al., IEEE Electro. Dev. Lett., 19, 472 (1998).[6] http://www.thorlabs.com. Figure 1

Design of Hafnium Oxide (HfO&lt;sub&gt;2&lt;/sub&gt;) Sidewall in InGaAs/InP for High-Speed Electronic Devices

The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO2 which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

A Comparison of Analog Performance, Linearity, and Distortion Characteristics Between Symmetric InGaAs and Asymmetric InGaAs/InP MOSFETs

In this article, we report an investigation of analog performance, linearity, and harmonic distortion (HD) characteristics for both symmetric and asymmetric InGaAs n-channel MOSFETs at elevated temperatures. Analog performance parameters such as transconductance and voltage gain are found to be better for the asymmetric InGaAs MOSFETs than their symmetric counterparts. The linearity metrics such as g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m2</sub> , g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m3</sub> , voltage intercept points 2 (VIP2), VIP3, IIP3, and third-order intermodulation distortion (IMD3) have been analyzed. Asymmetric devices are found to perform better in terms of linearity. Moreover, distortion is also found to be less for the asymmetric devices than the symmetric ones. A comparison of the linearity and distortion characteristics of InGaAs devices with a similarly sized Si device reveals that, although the Si device performs better in terms of linearity, particularly at elevated temperatures, InGaAs devices have an edge in terms of distortion over the Si device.

Analysis of Potential and Electron Density Behaviour in Extremely Scaled Si and InGaAs MOSFETs Applying Monte Carlo Simulations

Scaling of Silicon and InGaAs MOSFETs of a 25 nm gate length till shortest gate length of 5 nm, simulated this nano-device by Monte Carlo (MC) with quantum corrections. The transistors are scaled-down only in lateral dimensions in order to study electron transport approaching a ballistic limit along the scaled channel following experimental works. These MC simulations are able to give detailed insight into physical behaviour of electron velocity, electron density, and potential in relation to the drive current. We found that electron peak velocity increases during the scaling in Si MOSFETs till the 10 nm gate length and then dramatically declines due to a strong long-range Coulomb interaction among the source and the drain [16]. This effect is not observed in the equivalent InGaAs MOSFETs in which electron peak velocity exhibits double peak which steadily increases during the scaling [16]. However, the increasing of current in the equivalent InGaAs MOSFETs is moderate, by about 24 %, by comparing of current in the Si MOSFETs of 74 % delivered by 5 nm channel transistor.

A New Technique for Mobility Extraction in MOSFETs in the Presence of Prominent Gate Oxide Trapping: Application to InGaAs MOSFETs

In the presence of prominent gate oxide trapping, the conventional technique for channel mobility extraction in MOSFETs based on ${I}$ – ${V}/{C}$ – ${V}$ measurements becomes inadequate. This is the consequence of two different effects associated with oxide traps: gate voltage stretch-out and electron trapping and detrapping in the oxide at the megahertz (MHz)-range frequencies that are commonly utilized. In thin-channel planar InGaAs MOSFETs, both effects are observed and found to result in a severe overestimation of mobile charge and subsequently an underestimation of mobility using ${I}$ – ${V}/{C}$ – ${V}$ . To address this issue, we demonstrate a new mobility extraction technique (RF- ${I}_{D}$ ) based on concurrent ${I}$ – ${V}$ and ${S}$ -parameter measurement in the gigahertz (GHz) regime that is largely immune to oxide trapping. Excellent agreement with Hall measurements as well as with theoretical predictions from Poisson–Schrodinger simulations gives confidence to the new technique. Importantly, the new technique is not limited to InGaAs planar MOSFETs, but applies to any device geometry and any material system. Promising mobility ~1100 cm2/ $\text{V}\cdot \text{s}$ is found in quantum-well planar InGaAs MOSFETs with a 4-nm-thick channel.

Total-Ionizing-Dose Effects in InGaAs MOSFETs With High-k Gate Dielectrics and InP Substrates

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage $V_{\text {th}}$ shifts and subthreshold stretchout ( SS ), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and $I_{d}$ – $V_{\text {gs}}$ measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of $V_{\text {th}}$ and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep.

Interface and electrical properties of buried InGaAs channel MOSFET with an InP barrier layer and Al2O3/HfO2/Al2O3 gate dielectrics

The effects of HfO2-Al2O3 laminate structures on the equivalent oxide thickness (EOT), interface characteristics and leakage current properties are investigated on InP substrates. Ti and HfO2-Al2O3 laminate structures are introduced in the MOS capacitors, which present an approximately 1 nm EOT. Compared with the Al2O3/HfO2 laminate structure, the Al2O3/HfO2/Al2O3 laminate structure exhibits many advantages in border trap density, interface trap density and gate leakage current on InP substrate. The peak transconductance and drive current of buried InGaAs MOSFETs with a 0.8 nm Al2O3/3 nm HfO2/0.5 nm Al2O3 gate dielectric layer are increased by 41% and 38%, respectively, compared to that of the 3 nm Al2O3 layered one.

Hot carrier instability associated with hot carrier injection and charge injection in In0.7Ga0.3As MOSFETs with high-κ stacks

Channel hot carrier (CHC) reliability in In0.7Ga0.3As nMOSFETs with Al2O3/HfO2 (EOT = 0.8 nm) during CHC stress has been studied in scaled-down gate devices. The threshold voltage degradation (ΔVT) during CHC stress was attributed to the hot carrier injection into Al2O3 or/and HfO2 defect sites, rather than charge trapping into high-κ bulk defects. Additionally, with an increase of gate voltage at a fixed drain voltage (VDS), there was an increase in probability that the InGaAs channel carriers are easily injected into Al2O3 or/and HfO2 defect sites, causing the worst ΔVT degradation at the same VGS = VDS stress condition. Hence, hot carrier injection during CHC stress was divided into two components: charge injection by the vertical field near the source region and injection of hot carriers into the oxide bulk defects at the drain corner. To decouple the charge trapping and hot carrier injection into the gate oxide defect sites during CHC stress, an unrecovered (hot carrier damage) and recovery ratio (charge injection) of the ΔVT degradation after relaxation and opposite polarity voltage were calculated to be about ∼70% and ∼30%, respectively. Therefore, hot carrier injection has emerged as a dominant degradation factor in InGaAs MOSFETs with high-κ dielectrics.

(Invited) Negative Capacitance III-V FinFETs for Ultra-Low-Power Applications

Owing to its superior carrier transport, InxGa1-xAs materials are considered as the potential n-channels to replace Si for future CMOS technologies beyond the 7-nm technology node. Negative capacitance (NC) FETs with steep SS characteristics are extensively studied to lower the supply voltage (Vdd) for ultra-low-power applications. NC effects can be realized by using ferroelectric (FE) materials in the dielectric gate stack. Among the variety of FE materials, hafnium zirconium oxide (HfZrOx-HZO), which can be employed by atomic layer deposition (ALD) technique, is well-known as the most CMOS-compatible material. There have been various reports that show steep switching behaviors by applying HZO materials on both Si and Ge channels. Recently, NC InGaAs MOSFETs with FE HZO have been presented for steep subthreshold slope (SS) behaviors. However, NC effects have not been presented for nonplanar InGaAs FinFETs yet. In this work, we demonstrate NC In0.53Ga0.47As FinFETs with ferroelectric FE HZO as gate dielectric, exhibiting bi-directional sub-60 mV/dec (SS) at room temperature, for the first time. We show minimum SSrev of 23 and SSfor of 34 mV/dec on InGaAs NC FinFETs with 5 nm HZO thin film. III-V NC FinFETs with HZO FE materials can be very promising for extremely high performance and ultra-low-power CMOS applications.

Regrown source/drain in InGaAs multi-gate MOSFETs

To realize further progress in the field of integrated circuits, a high mobility channel material, such as InGaAs for n-MOSFETs, with a multi-gate structure is desired. To realize high current densities in InGaAs MOSFETs, heavily doped sources/drains obtained using epitaxial growth are required. Here, we report the regrowth of source/drain using MOVPE for fin FET and nanosheet FET structures. A thinner flow liner for higher flow rate of 1.5 m/s was selected as a growth condition to improve the selective growth property and contact characteristics. As a result, a carrier concentration of 2 × 1019 cm−3 and contact resistivity of 8.0 × 10−8 Ωcm2 were obtained simultaneously.We fabricated fin FET and nanosheet structures as multi-gate MOSFETs. In the case of fin FETs, the surrounded growth of the channel and operation of a 16-nm-gate device were confirmed. In the case of nanosheet FETs, we used butt-jointed structures, i.e., we performed regrowth after the channel portion was formed into a mesa shape by etching, and the regrowth interface was a boundary between the channel and source/drain. After the regrowth and removal of the InP layer between the sheets, it was confirmed that the two layers of the nanosheets were supported by the regrown source/drain layers on both sides. In this structure, the operation of the 40-nm-gate device was also confirmed.

Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, VT,lin, VT,sat, on-current, ION, leakage current, IOFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced VT variability, it increases the total VT,lin variability as well as that for ION and IOFF.

Systematic calibration of drift diffusion model for InGaAs MOSFETs in quasi-ballistic regime

This paper proposes a systematic procedure to calibrate the parameters of the drift-diffusion (DD) model for a performance evaluation of InGaAs MOSFETs in the quasi-ballistic regime. The simulation results of a deterministic multi-subband Boltzmann transport equation (BTE) solver serve as the standard. The DD model is calibrated both under low and high electric fields. The electrostatic characteristics, low field mobility model, and high field saturation model are calibrated in proper sequence, and a good agreement among the drive current, carrier distribution, and velocity distribution are achieved between the results of the calibrated DD model and the BTE solver. The proposed calibration procedure can also be employed in devices made of other materials.

Effect of Low Temperature RF Plasma Treatment on Electrical Properties of Junctionless InGaAs MOSFETs

In this paper, we study the effect of low-temperature RF plasma treatment in forming gas (10%H2+90%N2) on the electrical characteristics of junctionless MOSFETs with n-In0.53Ga0.47As channel and an Al2O3 gate dielectric. The impact of plasma power density on the device parameters is investigated. It is found that RF plasma annealing with a low power density (0.5 W/cm2) at 150°C for 10 min provides substantial improvement of source/drain contacts resistance and the carrier mobility resulting in a considerable increase of the on-state current and transconductance. It also improves the subthreshold slope and reduces the fixed positive charge in Al2O3 under the gate, shifting the threshold voltage toward positive values. It is demonstrated that non-thermal factors play a principle role in modification of electrical properties of the JL MOSFETs under RF plasma treatment. Such treatment may be an efficient tool for the improvement of the performance of the advanced MOSFETs with III-V channel materials.

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled transistors. In this paper, we demonstrate an innovative use of a heat-dissipating shunt of Ni-InGaAs on InGaAs(111) in the S/D extension region, as well as the use of high-conductivity Mo contact to simultaneously improve electrical and thermal stability and heat dissipation in III-V transistors, such that the peak channel temperature is reduced by as much as 25%–30%. Given the exponential temperature sensitivity of transistor reliability, heat shunts will improve transistor lifetime significantly.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an ION/IOFF ratio of more than 106 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

TCAD Mobility Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections

A TCAD-oriented mobility model, whose main features are: 1) inclusion of ballistic effects in the linear region and 2) smooth transition between the linear and saturation regions, is presented. It is applied to short-channel double-gate thin-body InGaAs MOSFETs. The bases of the model are the concept of ballistic mobility and Matthiessen’s rule in the linear regime, and the saturation velocity within a modified Canali model at high-longitudinal fields. Comparisons with accurate semiclassical multivalley multisubband Monte Carlo transport simulations indicate that TCAD simulations making use of the proposed model are able to correctly predict the terminal currents and the internal device quantities in the linear regime in a 15-nm device with no need of fitting parameters. In the saturation region, an empirical adjustment of the saturation velocity is needed, after which currents are accurately predicted for a wide range of gate lengths and bias conditions.