Incremental Delta-sigma Modulator Research Articles

A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

Low power capacitive-to-digital converter based on incremental delta-sigma modulator

This paper presents a low-power capacitive-to-digital converter (CDC) based on incremental delta-sigma modulator. It utilizes a zoom-in sensing capacitor that is insensitive to parasitic capacitance, improving the capacitance resolution. The use of a high-gain, PVT-robust current-starved OTA and a dynamic bias comparator enhances the efficiency of the system. An ultra-low-power bias circuit is integrated into the system, further improving integration and efficiency. The proposed CDC is fabricated using a 180 nm CMOS process. Operating at a 1.2 V supply voltage and a 250 kHz sampling frequency. With a measurement time of 0.8 ms, the capacitance resolution is 107.6 aF, and the power consumption is 10.27 μW. The figure-of-merits (FoM) is 2.06 pJ/step.

A 280 μW, 108 dB DR PPG-Readout IC With Reconfigurable, 2nd-Order, Incremental ΔΣM Front-End for Direct Light-to-Digital Conversion.

This paper reports on a low-power readout IC (ROIC) for high-fidelity recording of the photoplethysmogram (PPG) signal. The system comprises a highly reconfigurable, continuous-time, second-order, incremental delta-sigma modulator (I-ΔΣM) as a light-to-digital converter (LDC), a 2-channel 10b light-emitting diode (LED) driver, and an integrated digital signal processing (DSP) unit. The LDC operation in intermittent conversion phases coupled with digital assistance by the DSP unit allow signal-aware, on-the-fly cancellation of the dc and ambient light-induced components of the photodiode current for more efficient use of the full-scale input range for recording of the small-amplitude, ac, PPG signal. Fabricated in TSMC 0.18μm 1P/6M CMOS, the PPG ROIC exhibits a high dynamic range of 108.2dB and dissipates on average 15.7μW from 1.5V in the LDC and 264μW from 2.5V in one LED (and its driver), while operating at a pulse repetition frequency of 250Hz and 3.2% duty cycling. The overall functionality of the ROIC is also demonstrated by high-fidelity recording of the PPG signal from a human subject fingertip in the presence of both natural light and indoor light sources of 60Hz.

DC-100 kHz Tunable Readout IC for Impedance Spectroscopy and Amperometric Measurement of Electrochemical Sensors.

This paper presents a low-noise, front-end sensor IC that includes both AC impedance spectroscopy and DC amperometric measurement capabilities for electrochemical and biosensor applications. A common-gate current buffer topology is proposed that supports both current-mode and voltage-mode sensor signals to allow an input frequency range from DC to 100 kHz. Low-noise operation is achieved across a wide input frequency range using tunable high-pass and low-pass frequency response. In addition, an incremental delta-sigma modulator with embedded frequency response analysis serves as both on-chip impedance analyzer and current-driven analog-to-digital converter. Implemented using a 0.18 μm CMOS process, this work achieves 45 fA/√Hz input current noise density at 1 kHz. Input dynamic range exceeding 80 dB is achieved up to 10 kHz bandwidth, with a maximum of 104 dB dynamic range at 10 Hz.

Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

A 1-V 8.1-$\mu$ W PPG-Recording Front-End With > 92-dB DR Using Light-to-Digital Conversion With Signal-Aware DC Subtraction and Ambient Light Removal

This letter reports on a photoplethysmogram (PPG) readout IC (ROIC), comprising an ultralow-power recording front-end and a 2-channel light-emitting diode (LED) driver. The front-end uniquely employs a continuous-time, first-order, incremental delta–sigma modulator (I– $\Delta \Sigma \text{M}$ ) for direct light-to-digital conversion in a single stage with duty-cycled operation for power savings. Moreover, the I– $\Delta \Sigma \text{M}$ enables reconfigurable operation in intermittent conversion phases that allows the direct measurement of dc and ambient light-induced components of the photodiode current for signal-aware on-the-fly cancellation to recover the small ac PPG signal. Fabricated in 0.18- $\mu \text{m}$ 1P/6M CMOS, the PPG ROIC features a high dynamic range of 92.7 dB, dissipates 8.1 $\mu \text{W}$ and 1.95 mW in the recording front-end and the LED (with its driver), respectively, with ~10% duty cycling, and is validated by high-fidelity PPG recording from a human subject fingertip using an infrared LED.

A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback

This letter presents a high-resolution continuous-time incremental delta-sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.

A Large Measurable Range Capacitance-to-Digital Converter for Smart Humidity Sensors.

This study aims to propose a capacitance-to-digital converter (CDC) based on a third-order cascade of integrators with a feed-forward (CIFF) incremental sigma-delta modulator for smart humidity sensor application. Disguised zoom-in technology was proposed to enlarge the measurable range of the CDC. The input range of the CDC was 0–388 pF. The proposed CDC was realized using 0.18 μm complementary metal-oxide-semiconductor technology. Results show that the CDC performs a 13-bit capacitance-to-digital conversion in 0.8 ms. The analog system consumes 169.7 μA from a 1.8 V supply, which corresponds to a figure of merit (FOM) of 3.0 nJ/step. The proposed CDC was combined with a HS1101 humidity sensor to demonstrate its incorporation in an overall system design. The resolution was 0.7% relative humidity (RH) over a range of 30%–90% RH.

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

This paper presents a 13-bit high-resolution two-step analog-to-digital converter (ADC). Successive approximation register (SAR)-ADCs and an incremental sigma-delta modulator (ISDM) act as the coarse and fine ADCs, respectively. By using the proposed time-domain ISDM, the integrator is relaxed from the finite gain error and static current consumption. For the matching of the capacitive digital-to-analog converter(CDAC), the integral non-linearity (INL) splitting (INLS) switching procedure is developed to reduce the INL and switching energy to 25% and 9% of the reference common-mode voltage (VCM)-based scheme, respectively. With a reduced capacitance of the capacitor array, the requirements of the input driver and reference buffer are effectively relaxed. A prototype was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm CMOS technology, which occupies an area of 0.059 mm2. The achieved spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) at Nyquist rate are 90.38 and 73.57 dB, respectively. The maximum differential non-linearity (DNL) and INL are 0.45 and 0.75 LSB, respectively. The prototype consumes 638 nW at 0.4-V supply and 270-kHz sampling rate. The resultant Schreier figure of merit (FoM) is 186.8 dB, and the Walden FoM is 0.61 fJ/conversion step.

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta–sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and low-power is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively.