Improvement In Power Consumption Research Articles

Energy-Efficient Handover Algorithm for Sustainable Mobile Networks: Balancing Connectivity and Power Consumption

In the era of pervasive mobile and heterogeneous networks, maintaining seamless connectivity during handover events while minimizing energy consumption is paramount. Traditional handover mechanisms prioritize metrics such as signal strength, user mobility, and network load, often neglecting the critical aspect of energy consumption. This study presents a novel approach to handover decision-making in mobile networks by incorporating energy-related metrics, such as battery level, energy consumption rate, and environmental context, to make informed handover decisions that balance connectivity quality and energy efficiency. Unlike traditional methods that primarily focus on signal strength and network load, our approach addresses the critical need for energy efficiency, particularly in high-mobility scenarios. This innovative framework not only enhances connectivity but also significantly improves power consumption management, offering a more sustainable solution for modern mobile networks. Through extensive simulations, we demonstrate the effectiveness of our proposed solution in reducing energy usage without compromising network performance. The results reveal significant improvements in energy savings for mobile devices, especially under high-mobility scenarios and varying network conditions. By prioritizing energy-efficient handovers, our approach not only extends the battery life of mobile devices but also contributes to the overall sustainability of mobile networks. This paper underscores the importance of incorporating energy metrics into handover decisions and sets the stage for future research in energy-aware network management.

Inverter Packaging Technology That Improves Power Consumption and Convenience of Electric Vehicles

Inverter Packaging Technology That Improves Power Consumption and Convenience of Electric Vehicles

Energy-efficient Vienna rectifier for electric vehicle battery charging stations

Global DC fast-charging infrastructure is being rapidly developed to accommodate the ever-increasing demand from the electric vehicle market. A major complication in the electric power system's process is the proliferation of ultra-fast charging (UFC) stations, which are known for their enormous power consumption and unpredictable, intermittent performance. By implementing grid-supportive features and ensuring an improved power consumption profile for the grid, installing regional energy storage can solve these challenges. This study presents a control approach for managing the grid-side AC/DC converters of rapid charging stations focused on future-oriented regulation. The paper primarily concentrates on various Vienna rectifier topologies. The technology, characteristics, benefits, and operational aspects of Vienna rectifier topologies are vital to improving the performance, efficiency, and grid integration of electric vehicle charging systems. Fast charging, grid stability, energy economy, and the smooth integration of electric vehicles into the electrical grid are all made possible by Vienna rectifiers. When used in battery energy storage systems (BESS) for electric vehicle charging infrastructure, Vienna rectifiers allow for effective discharge and charging of the batteries. The configurations and assessments of these converters are examined, assessed, and compared based on power output parameters, element count, power factor, THD, and efficiency. The Vienna rectifier has been identified as the best suitable DC fast-charging converter architecture for power levels exceeding 15 kW due to its exceptional efficiency, limited output voltage ripples, high power density, reduced current ripples, and reliable performance. Research on ways to improve electric vehicle charging infrastructure can be spurred by a better grasp of the Vienna rectifier's technological complexities and performance benefits, leading to greener and more efficient transportation options. As a result, the system's power density will eventually rise and elemental stress will decrease.

Research on coordinated control strategy for braking energy recovery of pure electric vehicles based on ESC

AbstractTaking a rear‐wheel drive pure electric vehicle as the research object, considering the safety during braking and improving energy recovery rate, a study was conducted on the distribution strategy of front and rear axle braking force. During the braking process, the feedback braking force of the motor and the hydraulic braking force with an electronic stability controller (ESC) were coordinated and controlled, to ensure that the total required braking force was met. A fuzzy logic controller has been designed, with three variables of battery state of charge, vehicle speed, and braking intensity as inputs, and a modified motor braking ratio as output variable to prevent wheel lockup. Using Cruise software, a co‐simulation model was established with Amesim and Simulink, and simulation validation was conducted on the braking process and cycling conditions. The simulation results showed that the brake recovery strategy based on fuzzy control can effectively improve the vehicle's control performance and energy recovery rate compared to the Economic Commission of Europe regulation. The NEDC (New European Driving Cycle) working condition improved by 10.41% and the CLTC‐P (China Light‐duty Vehicle Test Cycle‐passenger) working condition improved by 10.57%. Effectively improving power consumption per 100 km, NEDC decreased by 1.81% and CLTC‐P decreased by 2.62%.

Federated learning inspired Antlion based orchestration for Edge computing environment.

Edge computing is a scalable, modern, and distributed computing architecture that brings computational workloads closer to smart gateways or Edge devices. This computing model delivers IoT (Internet of Things) computations and processes the IoT requests from the Edge of the network. In a diverse and independent environment like Fog-Edge, resource management is a critical issue. Hence, scheduling is a vital process to enhance efficiency and allocation of resources properly to the tasks. The manuscript proposes an Artificial Neural Network (ANN) inspired Antlion algorithm for task orchestration Edge environments. Its aim is to enhance resource utilization and reduce energy consumption. Comparative analysis with different algorithms shows that the proposed algorithm balances the load on the Edge layer, which results in lower load on the cloud, improves power consumption, CPU utilization, network utilization, and reduces average waiting time for requests. The proposed model is tested for healthcare application in Edge computing environment. The evaluation shows that the proposed algorithm outperforms existing fuzzy logic algorithms. The performance of the ANN inspired Antlion based orchestration approach is evaluated using performance metrics, power consumption, CPU utilization, network utilization, and average waiting time for requests respectively. It outperforms the existing fuzzy logic, round robin algorithm. The proposed technique achieves an average cloud energy consumption improvement of 95.94%, and average Edge energy consumption improvement of 16.79%, 19.85% in average CPU utilization in Edge computing environment, 10.64% in average CPU utilization in cloud environment, and 23.33% in average network utilization, and the average waiting time decreases by 96% compared to fuzzy logic and 1.4% compared to round-robin respectively.

P‐24: Ultra‐low power consumption notebook LCD with high on‐state current metal oxide device

Dual gate device with mobility of 20cm2/Vs has been applied to improve power consumption of oxide products, the devices show high on‐state current of more than 45uA, good uniformity of ΔVth 1.03V, PBTS of 2.18V. The optimized pixel design of 14inch WQXGA achieves high aperture ratio of 74% and transmittance of over 9.5%. This 120Hz demo with brightness of 150nit can significantly reduce power consumption by 65%, from 2.1W to 1.27W.

Integrating Fuzzy Logic and Brute Force Algorithm in Optimizing Energy Management Systems for Battery Electric Vehicles

The limited driving range of BEVs is the main challenge in developing zero-emission Battery Electric Vehicles (BEVs) to replace traditional fuel-based vehicles. This limitation necessitates an increase in battery energy while balancing the power supply and consumption requirements for the vehicle’s motor and auxiliaries, such as the Heating, Ventilation, and Air Conditioning (HVAC) system. This research proposes a solution to achieve more efficient control of HVAC consumption by integrating fuzzy logic techniques with brute-force algorithms to optimize the Energy Management System (EMS) in BEVs. The model was based on actual parameters, implemented using MATLAB-Simulink and ADVISOR software, and configured using a backward-facing design incorporating the technical specifications of a Malaysian electric car, the PROTON IRIZ. An optimal solution was proposed based on the Satisfaction Ratio (SR) and State of Charge (SoC) metrics to achieve the best system optimization. The results demonstrate that the optimized fuzzy EMS improved power consumption by 23.2% to 26.6% compared to a basic fuzzy EMS. The proposed solution significantly improves the driving range of BEVs.

Toward Energy‐Efficient Ferroelectric Field‐Effect Transistors and Ferroelectric Random Access Memories: Tailoring the Coercive Field of Ferroelectric HfO2 Films

Many modern applications require fast and reliable nonvolatile memory. Ferroelectric (FE) memories, such as FE field‐effect transistors and FE random access memories, show great promise in meeting these requirements. Another key factor is power efficiency. In the case of FE memories, the coercive field is a critical parameter for improving power consumption. This article introduces and reviews four promising methods to tailor the of FE films based on Zr‐doped : 1) composites with various Hf contents, 2) hybrid stacks consisting of antiferroelectric sublayers with excess Zr (x 0.5) and FE sublayers, 3) superlattice structures (also known as nanolaminates) consisting of and sublayers stacked on top of each other, and 4) films doped with an aluminum impurities. Electrical characterization of metal–FE–metal capacitor test structures confirms the suitability of all approaches. Analysis of the strengths and weaknesses is conducted, considering the tuning range, shape stability of the polarization versus electric field hysteresis loop, and the impact of these approaches on the remanent polarization .

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Development of a Performance-Based Design Technique for an Axial-Flow Fan Unit Using Airfoil Cascades Based on the Blade Strip Theory

Axial-flow fans are widely used as cooling fans in the outdoor units of split-type air conditioners. The design of an axial-flow fan blade involves stacking several airfoils that can be differently designed for each spanwise section. However, the complex flow field around the fan blade, including circumferential and axial flows, presents challenges when applying the single airfoil theory. This study proposed a systematic performance-based design method for axial-flow fans using a cascade of airfoils based on the blade strip theory. The theory characterized the complex three-dimensional flow field driven by an axial-flow fan in terms of a two-dimensional cascade of airfoil flows. Computational fluid dynamics based on finite volume methods were used to predict the flow field and aerodynamic sound sources of an existing low-pressure axial-flow fan partially covered by a fan shroud, and the results were validated against experimental measurements. Three radial locations in the spanwise region from the hub to the blade tip that have a significant impact on aerodynamic performance were selected, and the two-dimensional flow field on a cylindrical surface with a constant radius was extracted from the three-dimensional flow field to characterize the performance of an axial fan. Then, the airfoils at the targeted span locations were optimized for a higher flow rate and greater efficiency via two-dimensional simulations using the cascades of the airfoil, and the selected optimized airfoils were applied to existing fan blades. The effectiveness of the proposed performance-based design method for low-pressure axial-flow fans was validated by the results, which showed that the redesigned fan blades with cascades of airfoils performed as predicted, increasing the intended higher flow rate by about 1%, improving power consumption by 8%, and lowering the overall sound pressure level by 1.5 dBA.

A Power-Aware Method for IoT Networks with Mobile Stations and Dynamic Power Management Strategy

The Internet of Things (IoT) plays a critical role in the digitalization of numerous industries, enabling increased automation, connectivity, and data collection in areas such as manufacturing, healthcare, transportation, and smart cities. This paper introduces a power-aware method for IoT networks using mobile stations and a dynamic power management strategy. The proposed method aims to improve power consumption and total packets received compared to the static-station balanced data traffic method. The proposed method uses a mobile station to dynamically adapt its transmission power based on the network conditions and the strength of the received signal. Furthermore, a dynamic power management strategy is employed to further decrease the power usage of the network by adjusting the power state of each station and IoT node according to its level of activity, data traffic, and communication requirements. Simulation results showed that the proposed method reduced power consumption by up to 64%, increased total packets received by 72%, and, as a result, increased network coverage and lifetime compared to the balanced data traffic method with static stations. This method can be employed in various IoT applications to improve power efficiency and increase network reliability.

Energy efficient resource allocation algorithms combining PSO with FLC and Taguchi method in hybrid opportunistic networks

In order to reduce power consumption and delay time when mobile devices use wireless networks, this paper proposes dividing groups of mobile devices into clusters, and proposes two cluster architectures, which are dual-radio opportunistic networking for energy efficiency combining particle swarm optimization with fuzzy logic control and Taguchi by 2-hop of priority weighted round robin (DRONEE-PFT2-PWRR) and dual-radio opportunistic networking for energy efficiency combining particle swarm optimization with fuzzy logic control and Taguchi by multi-hop of priority weighted rate control (DRONEE-PFTM-PWRC). Furthermore, our proposed DRONEE-PFT2-PWRR algorithm increases cluster coverage using 2-hop and our proposed DRONEE-PFTM-PWRC algorithm improves power consumption of the system by multi-hop cluster architecture. Internal cluster communication uses Wi-Fi transmission packets, which can reduce energy consumption when a mobile device communicates with a long term evolution advanced (LTE-A) base station, and reduce interference on signals between mobile devices. In the selection of cluster heads, this paper uses particle swarm optimization (PSO) to find the best cluster head position, and the PSO fitness parameter value is adjusted using fuzzy logic control (FLC) combined with the Taguchi method. Priority weighted round robin (PWRR) architecture is proposed for LTE-A base station and cluster network resource allocation, and quality of service is introduced to give priority weight to packets according to data type. Furthermore, priority weighted rate control (PWRC) is proposed. This method determines whether the network resources of the base station meet the demands of the cluster, and then assigns weights according to the requirements of the cluster and its priorities, and finally allocates network resources according to those weights. This increases the uplink throughput of network resource allocation. Simulation results show that our proposed methods significantly outperform the DRONEE-weighted (DRONEE-W) algorithm method in terms of power consumption, network throughput, and transmission delay time.

An Energy and Quality Efficient MTJ/FinFET Approximate 5:2 Compressor for Image Processing Applications

Shrinking the transistor dimensions in complementary metal-oxide-semiconductor (CMOS) technology has led to many huge problems, like high power density. Various methods at different design levels of abstraction, such as approximate computing and spintronic devices based on magnetic tunnel junction (MTJ), have been studied to solve these problems. In this paper, we propose a novel hybrid MTJ/FinFET-based approximate 5:2 compressor. The proposed design employs the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE) to store inputs in MTJs. Due to the SHE assistance, the energy efficiency of the MTJ switching is improved considerably over the conventional STT method. Our design significantly improves the energy consumption compared to the previous compressors, thanks to the decrease in MTJ and transistor counts. The proposed circuit and previous designs are simulated using HSPICE with 7-nm FinFET and SHE perpendicular-anisotropy MTJ model. From the simulation results, we can see that the proposed design improves power consumption, write energy, read energy, number of transistors and MTJ count on average by 49%, 50%, 63%, 20% and 50%, respectively, in comparison with the existing counterparts. Furthermore, the accuracy of the approximate designs is evaluated through comprehensive MATLAB simulations. The results indicate that the proposed circuit outperforms the best previous energy-efficient designs in terms of accuracy despite having better hardware characteristic parameters.

Design and Preliminary Experiment of Room-Temperature Bitter Magnet for Compact Gyrotron

Magnetic field system is one of the most crucial components for gyrotron operation. A compact gyrotron with a custom-designed magnet would be a promising continuous radiation source for millimeter-wave power applications. In this article, a design and preliminary experiment of a room-temperature Bitter magnet for developing compact gyrotron are presented. To lengthen the magnetic field homogeneity region without dramatically improving power consumption, a special design that every Bitter segment with different outer radii is adopted. Both in simulation and experimental measurement, the length of the homogeneity region is 120 mm, and homogeneity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \textit{B}$</tex-math> </inline-formula> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{B}$</tex-math> </inline-formula> is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 0.9% is obtained. A 5 kV magnetron injection gun (MIG) was designed based on the experimental measurement of this Bitter magnet, in which a velocity ratio of 1.3 and transverse velocity spread of 12% were obtained at current 0.5 A in simulation.

New approach to improve power consumption associated with blockchain in WSNs.

Nowadays, Wireless Sensor Networks (WSNs) are widely used for collecting, communicating, and sharing information in various applications. Due to its limited resources in terms of computation, power, battery lifetime, and memory storage for sensor nodes, it is difficult to add confidentiality and integrity security features. It is worth noting that blockchain (BC) technology is one of the most promising technologies, because it provides security, avoids centralization, and a trusted third party. However, to apply BCs in WSNs is not an easy task because BC is typically resource-hungry for energy, computation, and memory. In this paper, the additional complication of adding BC in WSNs is compensated by an energy minimization strategy, which basically depends on minimizing the processing load of generating the blockchain hash value, and encrypting and compressing the data that travel from the cluster-heads to the base station to reduce the overall traffic, leading to reduced energy per node. A specific (dedicated) circuit is designed to implement the compression technique, generate the blockchain hash values and data encryption. The compression algorithm is based on chaotic theory. A comparison of the power consumed by a WSN using a blockchain implementation with and without the dedicated circuit, illustrates that the hardware design contributes considerably to reduce the consumption of power. When simulating both approaches, the energy consumed when replacing functions by hardware decreases up to 63%.

Impact of device-to-device interference in nanosheet field-effect transistors

Nanosheet field-effect transistors (NS FETs) are a promising candidate for extremely scaled logic devices beyond FinFETs. The benefits of NS FETs include superior design flexibility and gate controllability, which enable continuous scaling beyond the 3-nm process node, while improving power consumption and performance as well. Recently, many reports have covered how geometrical changes such as the number of stacked nanosheets, inner spacer thickness, and gate stack structures, impact the characteristics of NS FETs. However, few studies have documented the interference effects of multiple NS FETs, even though this is quite important to actual CMOS circuit operation. In this work, we investigated the impact of device-to-device interference on the electrical behavior of adjacent NS FETs using TCAD simulation. We demonstrate that both off-state current (IOFF), and short-channel effects (SCEs) immunity, are significantly affected by adjacent NS FET's on/off operation. Further, we also determined the optimum device structure for maintaining the desired IOFF and SCEs immunity, which can be implemented by adjusting key geometrical parameters, including inner spacer thickness (TSPACER), gate length (LG) and STI collapses (Tcollapse). The superb gate controllability with deeper STI collapses results in much better SCEs properties in terms of IOFF, threshold voltage (VT), and subthreshold swing (SS), providing a promising way of reducing the local variation in NS FETs induced by adjacent devices.

Supercontinuum in integrated photonics: generation, applications, challenges, and perspectives.

Frequency conversion in nonlinear materials is an extremely useful solution to the generation of new optical frequencies. Often, it is the only viable solution to realize light sources highly relevant for applications in science and industry. In particular, supercontinuum generation in waveguides, defined as the extreme spectral broadening of an input pulsed laser light, is a powerful technique to bridge distant spectral regions based on single-pass geometry, without requiring additional seed lasers or temporal synchronization. Owing to the influence of dispersion on the nonlinear broadening physics, supercontinuum generation had its breakthrough with the advent of photonic crystal fibers, which permitted an advanced control of light confinement, thereby greatly improving our understanding of the underlying phenomena responsible for supercontinuum generation. More recently, maturing in fabrication of photonic integrated waveguides has resulted in access to supercontinuum generation platforms benefiting from precise lithographic control of dispersion, high yield, compact footprint, and improved power consumption. This Review aims to present a comprehensive overview of supercontinuum generation in chip-based platforms, from underlying physics mechanisms up to the most recent and significant demonstrations. The diversity of integrated material platforms, as well as specific features of waveguides, is opening new opportunities, as will be discussed here.

WITHDRAWN: DESIGN OF ADIABATIC CIRCUITS WITH REVERSIBLE LOGIC BASED FULL ADDER AND MULTIPLIER IN CURRENT-MODE LOGIC CIRCUITS FOR EFFICIENT POWER DISSIPATION

The widely used reversible full adder circuits are actualized in preceding research that optimizes design as well as speed of circuits.Theselogic gates that are reversible such as Peres, TSG, Toffoli, Feynman, and Fredkin are predominantly deployed in designing the reversible circuits. Nevertheless, its results are not promising in the context of dissipating static power. Power dissipation has turned out to be crucial issue in designing VLSI circuits. To overcome this problem, the energy recovery principle is introduced, and it is known as Adiabatic Logic. The famous adiabatic, low powered circuits work on reversible logic to store power and revert the same. Multiple Adiabatic Techniques (AT)is employed for dissipating the power in efficient manner. These ATs reduce power dissipation especially in VLSI circuits by performs both charging as well as discharging. The proposed research implements the Reversible Logic (RL) in Full Adder (FA) of Adiabatic Logic Reversible MOS Current-Mode Logic (MCML) FA generally termed Adiabatic Logic Reversible MCML Full Adder (FA) as well as on the Adiabatic Logic Reversible MCML multiplier. This is aimed to produce high speed circuits at reduced power. Reliable performance augmented with speedy operation is prominently exhibited in MCML than CMOS logic family. Coverage area along with improved power consumption may help in deployment of reversible logic in FA pertaining to MCML. Minimal quantity garbage output when given constant inputs is employed in reversible FA. The detailed experimental analysis portrays that proposed circuit can attain improved performance than existing RL like Feynman gate, Peres gate, TSG, Reversible MCML with Full Adder in the context of mean power, static power and current, and coverage area.

Review and analysis of secure energy efficient resource optimization approaches for virtual machine migration in cloud computing

Computing operations such as databases, networks, hardware, programs, analytics, and so on are all part of the cloud computing service. As such, it may serve as an option to in-house hardware and software. However, dynamic consolidation of VMs is required to improve power consumption, load balance, the frequency of migrations, Quality of Service (QoS), and the rate at which SLA violations are addressed, all of which contribute to better resource use. VM technology has quickly become a pillar of data centers and cluster systems because to its utility in partitioning, consolidating, and moving workloads. VM placement is another thing that affects the quality of consolidation. It is important to design a system that improves energy efficiency by allocating resources to applications in a smart way while still meeting QoS requirements for applications. Moreover, the security of information that is being processed during the migration process is also one of the important tasks. Hence, in this paper, review and analysis based on parameters and metrics for the VM migration under the influence of energy optimization, consolidation, and security have been investigated in a wider manner. Moreover, some open issues that are still prevalent in the current field have also been highlighted.

Mesh of Trees FPGA Architecture: Exploration and Optimization

The design of large devices suggests fundamental and efficient innovation in the field programmable gate array (FPGA) interconnect structure to improve power consumption, density, and performance. Mesh-based FPGA architectures are generally designed to maximize logic utilization and to ensure layout scalability whereas tree-based FPGA architectures are designed to increase interconnect utilization. In this article, we propose a new mesh of trees (MoTs) FPGA architecture where we try to benefit from mesh of clusters (MoCs) FPGA layout scalability and tree-based FPGA efficient intracluster interconnect utilization, thanks to the butterfly fat-tree (BFT) topology. In order to attain the efficient use of the proposed routing interconnect resources, we develop computer-aided design (CAD) tools that respond to the target MoTs FPGA features. In addition, we define the power, area, and delay metric models according to the proposed architecture criteria. The experimentation results show that MoTs architecture with a cluster arity 32 offers the best tradeoff between power, area, and delay. Furthermore, we conduct a comparison between MoTs and MoCs FPGAs in general and the best MoTs and MoCs solutions, which ensure the best tradeoff between power, area, and delay in particular. The results show that the best MoTs architecture reduces power, area, delay, and energy by an average of 29%, 6%, 40%, and 47%, respectively, in comparison with the best MoCs architecture.