Improved Channel Mobility Research Articles

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN x gate insulator for high hole mobility

In this work, the GaN p-MISFET with LPCVD-SiN x is studied as a gate dielectric to improve device performance. By changing the Si/N stoichiometry of SiN x , it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN x gate dielectric, which leads to a respectably improved drive current of GaN p-FET. The record high channel mobility of 19.4 cm2/(V∙s) was achieved in the device featuring an Enhancement-mode channel. Benefiting from the significantly improved channel mobility, the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm, while simultaneously featuring a negative threshold-voltage (V TH) of –2.3 V (defining at a stringent criteria of 10 μA/mm). The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm. This suggests that a decent E-mode operation of the fabricated p-FET is obtained. In addition, the V TH shows excellent stability, while the threshold-voltage hysteresis ΔV TH is as small as 0.1 V for a gate voltage swing up to –10 V, which is among the best results reported in the literature. The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN x is a promising approach to improve the device performance of GaN p-MISFET.

Microscopic Evaluation of Al<sub>2</sub>O<sub>3</sub>/p-Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Improvement of channel mobility is required to improve the performance of the inversion channel MOSFETs using diamond. The previous studies have suggested that high interface defect density (Dit) at the Al2O3/diamond (111) interface has a significant impact on the carrier transport property on a channel region. To investigate the physical origins of the high Dit, especially from microscopic point of view, here we investigate Al2O3/p-type diamond (111) interfaces using scanning nonlinear dielectric microscopy (SNDM). We find the high spatial fluctuations of Al2O3/hydroxyl (OH)-terminated diamond (111) interface properties and their difference by the flatness of the diamond surface.

High-voltage SiC power devices for improved energy efficiency.

Silicon carbide (SiC) power devices significantly outperform the well-established silicon (Si) devices in terms of high breakdown voltage, low power loss, and fast switching. This review briefly introduces the major features of SiC power devices and then presents research works on breakdown phenomena in SiC pn junctions and related discussion which takes into account the energy band structure. Next, recent progress in SiC metal-oxide-semiconductor field effect transistors, which are the most important unipolar devices, is described with an emphasis on the improvement of channel mobility at the SiO2/SiC interface. The development of SiC bipolar devices such as pin diodes and insulated gate bipolar transistors, which are promising for ultrahigh-voltage (>10 kV) applications, are introduced and the effect of carrier lifetime enhancement is demonstrated. The current status of mass production and how SiC power devices can contribute to energy saving are also described.

High-temperature CO2 treatment for improving electrical characteristics of 4H-SiC(0001) metal-oxide-semiconductor devices

High-temperature CO2 treatments for 4H-SiC(0001) surfaces and SiO2/SiC structures were investigated. A stoichiometric SiO2 insulating layer was found to be grown on SiC by thermal oxidation in atmospheric CO2 ambient with an activation energy of 7.5 eV. Post-oxidation annealing (POA) in CO2 at a temperature of 1200 °C or more was effective in reducing interface fixed charges, oxide traps, and defect precursors, which are intrinsically involved in SiO2/SiC system grown with O2 oxidant. Furthermore, modification of the SiO2/SiC interface promoted by oxidizing SiC with CO2 at 1400 °C or more reduced the amount of interface states, thus the SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) treated with CO2 at 1400 °C exhibited improved channel mobility with a stable threshold voltage.

Electrothermal performance limit of β-Ga2O3 field-effect transistors

A β-Ga2O3 field effect transistor (FET) outperforms a GaN FET in Baliga's figure of merit (FOM) by 400% and Huang's chip area manufacturing figure of merit by 330%, suggesting that β-Ga2O3 could be a substrate of choice for next generation power transistors. However, its low thermal conductivity leads to extreme self-heating, which deteriorates the device performance during high voltage operation. A holistic evaluation of performance from a material-device-circuit perspective is necessary before reaching any conclusion regarding the technological viability of β-Ga2O3. In this paper, we develop a multiphysics and multiscale model for a material-device-circuit analysis of β-Ga2O3 FETs. The framework allows us to explore the effectiveness of various device design strategies (e.g., thermal shunts) for mitigating the thermal chokepoints and compare the performance of improved β-Ga2O3 FETs against that of GaN and SiC FETs. We highlight the limitations of traditional FOMs to analyze the relative performance of the new generation of power transistors whose structure incorporates stacked layers of materials with different thermal conductivities, like those of β-Ga2O3 FETs. We suggest device design strategies, such as wafer thinning, incorporation of heat shunts, and improved channel mobility, so that β-Ga2O3 FETs can compete commercially with GaN and SiC technologies.

Improved channel mobility of 4H-SiC n-MOSFETs by ultrahigh-temperature gate oxidation with low-oxygen partial-pressure cooling

An n-channel metal–oxide–semiconductor field-effect transistor (MOSFET) with high field-effect mobility (μFE) on 4H-SiC (0001) was fabricated using an ultrahigh-temperature gate-oxidation technique, and its improved channel mobility was demonstrated by employing a low-oxygen partial-pressure cooling procedure. The ideal flatband voltage for n-MOS and p-MOS capacitors and hysteresis-free drain current–gate voltage (Id–Vg) characteristics were obtained through gate oxidation at 1450 °C in 100% O2 ambient at 1 atm followed by the low-oxygen partial-pressure (1%) rapid-cooling procedure. From the Id–Vg characteristics, a μFE of 15.8 cm2 V−1 s−1 was obtained under the pure O2 gate-oxidation process.

Gate-Recessed Normally-OFF GaN MOSHEMT With Improved Channel Mobility and Dynamic Performance Using AlN/Si3N4 as Passivation and Post Gate-Recess Channel Protection Layers

In this letter, a gate recessed normally-off GaN metal–oxide–semiconductor high-electron-mobility transistor on silicon substrate is fabricated using AlN/Si3N4 as the passivation layer. The thin AlN layer serves the dual role of protecting the gate channel region from direct plasma bombardment during the RIE Si3N4 removal and passivating the surface states in the access region. As a result, the effective carrier mobility in the normally-off channel is found to improve from the 568 cm2/ $\text {V}\cdot \text {s}$ in conventional Si3N4 passivation process to a high value of 1154 cm2/ $\text {V}\cdot \text {s}$ . A saturated output current density of 603 mA/mm and an ON-resistance of $5.3~\Omega \cdot \text {mm}$ was obtained for devices with $\text{L}_{\text {G}}/\text{L}_{\text {GS}}/\text{L}_{\text {GD}}/\text{W}_{\text {G}} = 1.5$ /1.5/3/ $20~\mu \text{m}$ . Meanwhile, the degradation of dynamic ON-resistance is significantly suppressed due to the effective passivation of surface states by the AlN layer grown by plasma-enhanced atomic layer deposition.

High-performance normally off AlGaN/GaN-on-Si HEMTs with partially recessed SiN x MIS structure

Recessed MIS gate structures with SiNx gate dielectric layer were investigated for use in normally off AlGaN/GaN-on-Si high electron mobility transistors (HEMTs). The channel mobility and threshold voltage (Vth) instability were strongly affected by the recessed configuration. Employing a 30 nm SiNx gate dielectric layer composed of 6 nm PEALD and 24 nm ICP-CVD films on a 2 nm AlGaN recessed barrier layer resulted in excellent electrical and dynamic characteristics with reduced effective interface trap density. A maximum drain current density of 590 mA mm−1, an on-resistance of 0.75 mΩ · cm2, and a breakdown voltage of >1100 V were achieved for the gate-to-drain distance of 10 μm. Owing to the remaining AlGaN barrier layer under the recessed gate region of the partially recessed device, the interaction between MIS interface traps and channel electrons was suppressed effectively, resulting in improved channel mobility and Vth stability.

Improved Channel Mobility by Oxide Nitridation for N-Channel MOSFET on 3C-SiC(100)/Si

In this work we studied the gate oxidation temperature and nitridation influences on the resultant 3C-SiC MOSFET forward characteristics. Conventional long channel lateral MOSFETs were fabricated on 3C-SiC(100) epilayers grown on Si substrates using five different oxidation process. Both room temperature and high temperature (up to 500K) forward IV performance were characterised, and channel mobility as high as 90cm2/V.s was obtained for devices with nitrided gate oxide, considerable higher than the ones without nitridation process (~70 cm2/V.s).

High performance thin film transistors using low-temperature solution-processed Li-incorporated In2O3/ZrO2 stacks

We improved the performance of low-temperature solution-processed thin film transistors (TFTs) by lithium doping of In2O3/ZrO2 gate stacks. Li incorporation into In2O3 reduced interface diffusion of ZrO2 and improved channel mobility. Enhanced crystallization of Li-doped In2O3 thin films as well as the small equivalent oxide thickness of ZrO2 were determined to be key factors in the observed improvement in device performance. An increase in the [Li+]/[In3+] ratio over the optimum value resulted in performance degradation, which we attributed to the formation of higher energy barriers due to grain boundaries.

Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology

Integration of a high-k interfacial layer (IL) is a promising technological solution to improve the scalability of high-k /metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiOx/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nFETs (0.7 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and -0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> stack, i.e., improved channel mobility over SiOx/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /TiN gate stack is investigated, demonstrating 10-year expected lifetimes for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.

Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation

We propose another process for fabricating 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with high channel mobility. The B atoms were introduced into a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /4H-SiC interface by thermal annealing with a BN planar diffusion source. The interface state density near the conduction band edge of 4H-SiC was effectively reduced by the B diffusion and the fabricated 4H-SiC MOSFETs showed a peak field-effect mobility of 102 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs. The obtained high channel mobility cannot be explained by counter doping because B atoms act as acceptors in 4H-SiC. We suggest that the interfacial structural change of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> may be responsible for the reduced trap density and enhanced channel mobility.

High Channel Mobility 4H-SiC MOSFETs by Antimony Counter-Doping

Channel mobility of >100 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$ </tex-math></inline-formula> V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$ </tex-math></inline-formula> s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$ </tex-math></inline-formula> has been obtained on enhancement mode 4H-SiC MOSFETs using an antimony (Sb) doped surface channel in conjunction with nitric oxide (NO) postoxidation annealing. Temperature dependence of the channel mobility indicates that Sb, being an n-type dopant, reduces the surface electric field while the NO anneal reduces the interface trap density, thereby improving the channel mobility. This letter highlights the importance of semiconductor/dielectric materials processes that reduce the transverse surface electric field for improved channel mobility in 4H-SiC MOSFETs.

Improvement of Channel Mobility in 4H-SiC C-Face MOSFETs by H&lt;sub&gt;2&lt;/sub&gt; Rich Wet Re-Oxidation

4H-SiC(000-1) C-face was oxidized in H2O and H2 mixture gas (H2 rich wet ambient) for the first time. H2 rich wet ambient was formed by the catalytic water vapor generator (WVG) system, where the catalytic action instantaneously enhances the reactivity between H2 and O2 to produce H2O. The dependence of SiC oxidation rate on the H2O partial pressure was investigated. We fabricated 4H-SiC C-face MOS capacitor and MOSFET by the H2 rich wet re-oxidation following the dry O2 oxidation. The density of interface traps was reduced and the channel mobility was improved in comparison with the conventional O2 rich wet oxidation.

Nitridation Effects of Gate Oxide on Channel Properties of SiC Trench MOSFETs

We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH3 and N2O POA.

Comparative Study of 4H-SiC DMOSFETs with N&lt;sub&gt;2&lt;/sub&gt;O Thermal Oxide and Deposit Oxide with Post Oxidation Anneal

Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C(TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.

Systematic structural and chemical characterization of the transition layer at the interface of NO-annealed 4H-SiC/SiO2 metal-oxide-semiconductor field-effect transistors

We present a systematic characterization of the transition layer at the 4H-SiC/SiO2 interface as a function of nitric oxide (NO) post-annealing time, using high-resolution transmission electron microscopy for structural characterization and spatially resolved electron energy-loss spectroscopy for chemical analysis. We propose a systematic method for determining transition layer width by measuring the monotonic chemical shift of the Si-L2,3 edge across the interface, and compare its efficacy to traditional measures from the literature, revealing the proposed method to be most reliable. A gradual shift in the Si-L2,3 edge onset energy suggests mixed Si-C/Si-O bonding in the transition layer. We confirm an inverse relationship between NO-anneal time and transition layer width, which correlates with improved channel mobility, enhanced N density at the interface, and decreased interface trap density. No excess C was noted in the interfacial region.

Interaction of metal impurities with native oxygen defects in GeO2

Injection of metal atoms from a high-k oxide cap to a passivating GeO2 layer could ultimately affect the quality of Ge-based gate stacks. Here we investigate with first-principles calculations the incorporation of different metal atoms and their effect on the electronic properties of GeO2. We find that tetravalent Hf and Zr substitutional atoms have no beneficial influence on pre-existing defect states in GeO2 whereas trivalent Al species can passivate existing oxygen vacancies. The results are consistent with the improved channel mobility of devices employing Al2O3/GeO2 gate oxides.

Multiscale Modeling and Analysis of the Nitridation Effect of SiC/SiO&lt;sub&gt;2&lt;/sub&gt; Interface

We explain the role of nitrogen in simultaneously increasing the inversion channel mobility and reducing the threshold voltage of SiC MOSFET. A variety of computational techniques have been used to compute the atomic scale configuration of a nitridated SiC/SiO2 interface, and the corresponding change in Fermi level, inversion channel mobility, and threshold voltage. X-ray photoelectron spectroscopy (XPS) has been used to investigate the SiC/SiO2 interface to determine the nitrogen concentrations and chemical bonding. We elucidate the physics behind improved channel mobility due to NO anneal and demonstrate that the trade-off between threshold voltage and inversion channel mobility can be correlated to the extent of nitridation.

Improvement of Channel Mobility in Inversion-Type n-Channel GaN Metal–Oxide–Semiconductor Field-Effect Transistor by High-Temperature Annealing

Inversion- and depletion-type GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated on p- and n--type GaN epitaxial layers, respectively, grown on n+-type on-axis 4H-SiC(0001) substrates. After gate SiO2 was deposited by plasma-enhanced chemical vapor deposition at 350 °C, high-temperature annealing in N2 was carried out to modify the interface. The channel mobility was enhanced with increasing annealing temperature. The device annealed in N2 at 1100 °C after SiO2 deposition showed an inversion channel mobility of 108 cm2·V-1·s-1 at a gate voltage of 15 V. The authors also fabricated MOS capacitors on n--type GaN and characterized the interface state density at the SiO2/GaN interface from capacitance–voltage measurements using the Terman method, of which density was estimated to be in the range of (6–10)×1011 cm-2·eV-1 at an energy level of 0.2 eV below the conduction band edge. The interface state density tended to decrease with increasing annealing temperature, resulting in the improvement of the channel mobility.