Improve Test Coverage Research Articles

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF

Acceptability of routine HIV counselling and testing, and HIV seroprevalence in Ugandan hospitals

Mulago and Mbarara hospitals are large tertiary hospitals in Uganda with a high HIV/AIDS burden. Until recently, HIV testing was available only upon request and payment. From November 2004, routine free HIV testing and counselling has been offered to improve testing coverage and the clinical management of patients. All patients in participating units who had not previously tested HIV-positive were offered HIV testing. Family members of patients seen at the hospitals were also offered testing. Data collected at the 25 participating wards and clinics between 1 November 2004 and 28 February 2006 were analysed to determine the uptake rate of testing and the HIV seroprevalence among patients and their family members. Of the 51,642 patients offered HIV testing, 50,649 (98%) accepted. In those who had not previously tested HIV-positive, the overall HIV prevalence was 25%, with 81% being tested for the first time. The highest prevalence was found in medical inpatients (35%) and the lowest, in surgical inpatients (12%). The prevalence of HIV was 28% in the 39,037 patients who had never been tested before and 9% in those who had previously tested negative. Of the 10,439 family members offered testing, 9720 (93%) accepted. The prevalence in family members was 20%. Among 1213 couples tested, 224 (19%) had a discordant HIV status. In two large Ugandan hospitals, routine HIV testing and counselling was highly acceptable and identified many previously undiagnosed HIV infections and HIV-discordant partnerships among patients and their family members.

DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.

Improving test coverage of LAPACK

We discuss the way in which the Lapack version 3.0 suite of software is tested and look at how the application of software testing metrics affects our view of that testing. We analyse the ways in which some errors may be masked by the existing approach and consider how we might use the existing suite to generate an alternative test suite that is easily extensible as well as providing a high degree of confidence that the package has been well tested.

블랙박스 테스트 케이스의 리엔지니어링

Black-box testing needs to prepare fitting test data, execute software, and examine the result. If we test software effectively, not only selecting test cases but also representing test cases are important. In static testing effectiveness of testing activities also depends on how to represent test cases and checklist to validate. This paper suggests a method for finding ineffective critical test cases and reengineering them. An experiment of reengineering digital set-top box software shows the process and results of checking effectiveness and conformance of current test cases and patching test cases. The result shows how much save the test time and improve test coverage by reengineering test cases. Methods of reuse and restructuring test cases are also studied to fit into embedded product-line software.

A TOOL TO AUTOMATICALLY MAP IMPLEMENTATION-BASED TESTING TECHNIQUES TO CLASSES

The object-oriented (OO) paradigm provides several benefits during analysis and design of large-scale software systems, but scores lower in terms of testability. The low testability score for OO software is due mainly to the composition of OO systems exhibiting the characteristics of abstraction, encapsulation, genericity, inheritance, polymorphism, concurrency and exception handling. To address the difficulty of testing the features of a class, a plethora of implementation-based testing techniques (IBTTs) have been developed. However, no one IBTT has emerged as the preferred technique to test the implementation of a class. In this paper we present a technique that automatically identify those IBTTs that are most suitable for testing a class based on the characteristics of that class. Our approach uses a taxonomy of OO classes that is used to succinctly abstract the characteristics of a class under test (CUT). We have implemented a tool that automates the process of mapping IBTTs to a class. In addition to identifying the IBTTs that would be best suited for testing a class, our tool provides feedback to the tester facilitating the identification of the characteristics of the class that are not suitably tested by any of the IBTTs in the list. We provide results of a study supporting the notion that using more than on IBTT during testing improves test coverage of a CUT.

Efficient parametric fault detection in switched-capacitor filters

Advances in technology and IC design techniques have allowed for sophisticated analog and digital functions in a single chip, in which switched-capacitor (SC) networks perform fundamental operations such as filtering and A/D and D/A conversion. As a result, considerable effort has gone into improving test coverage and testable circuit design in general and SC networks in particular. This article presents an alternative SC-filter-testing methodology, which not only accurately detects but also locates parametric faults, using little additional circuitry. Based on structurally all-pass building blocks, the proposed technique fits into the DFT category. It uses considerably less additional circuitry for testing than other approaches because the testing procedure consists of forming notch filters out of existing second-order all-pass sections. Moreover, it does not require reconfiguration of the circuit under test, making it suitable for online testing. The testing scheme also belongs to the multifrequency analysis class, but it requires neither optimization nor sensitivity computations because the filter transfer function's synthesis procedure naturally reveals the optimum test frequencies and nodes. The scheme is readily extendable to other discrete- or continuous-time structures based on all-pass filters.

Peer-delivered hepatitis C testing and counselling: a means of improving the health of injecting drug users.

We hypothesized that providing injecting drug users (IDUs) with free hepatitis C testing and counselling at a needle and syringe programme (NSP) would be an effective model. Between August 1999 and January 2000, our peer outreach worker offered these services from a busy NSP in western Melbourne. Over 300 counselling episodes were provided, and 47 IDUs who were not tested in the previous 12 months were given tests and full pre- and post-test counselling, and were interviewed about reasons for not being tested, their knowledge of hepatitis C, and their risk behaviour. Twenty-eight IDUs (59.6%) tested antibody-positive, demonstrating the need to improve testing coverage and compliance with counselling requirements. Most were not tested because they did not think they were at risk, but their reported behaviour and antibody test results showed otherwise. Twenty people returned for a second interview, and improvements in their risk behaviour and knowledge of hepatitis C were detected. Our experience suggests that demand exists for hepatitis C testing and counselling of IDUs in Melbourne's western suburbs, that testing and counselling improve IDUs' ability to avoid harm, and that delivery of these services by a trained and experienced peer located at an NSP is an appropriate and effective model.

Incorporating I_DDQ Testing with BIST forImproved Coverage: An Experimental Study

In this paper we present an experimental study on the effectiveness of incorporating at-speed I_DDQ testing with traditional BIST for improved test coverage. The high speed I_DDQ testing is conducted using the differential built-in on-chip current sensor (BICS) that we have recently developed. Two test chips were designed and fabricated implementing a CMOS version of the 74181 ALU chip. In copies of this circuit we included the capability of activating 45 different “realistic” CMOS faults: inter- and intra-layer shorts and opens. We examine the fault coverage of both Boolean (voltage) testing andI_DDQ testing for these realistic faults. An interesting finding of our study is that I_DDQ testing also detected several of the open faults. Moreover, these include precisely those open faults for which two pattern voltage tests can get invalidated because of transient switching states. Our results show that combining both Boolean and current testing does enhance test coverage in a BIST environment.

Built-in self-test for folded bit-line Mbit DRAMs

In this paper an efficient and comprehensive algorithm for deriving near optimal parallel tests for neighborhood pattern sensitive faults (NPSFs) detection for an arbitrary type of neighborhood is presented. When k is odd (even) it is based on the decomposition of a directed (undirected) k-cube into a minimal number of edge-disjoint tours. The approach considerably simplifies test-pattern generator (TPG) requirements and makes it suitable for implementation on a VLSI chip. The proposed algorithm is utilized to derive a parallel self-test for detection of unidirectional NPSFs in solded bit-line Mbit DRAM chips. An integrated test strategy covers the most typical functional and parametric faults by execution of retention and marginal tests during the parallel test for unidirectional NPSFs detection. Results showed an improved test coverage of k-coupling faults by approximately 10–65% compared to “tiling” method when k varies from 2 to 9. The total chip area expansion is less than 0.5% for Mbit DRAMs. A test length is 1072 N w when a lower bound is 1024 N w, where N w is the number of word-lines. Thus 64 MBit DRAM {8192 × 8192} is tested within a second when the speed of the test clock is 10 MHz.

In Search of the Ultimate Test Strategy

In an attempt to illustrate the variety of test methods available to the modern electronic manufacturer, the paper describes the major alternatives and offers a method of matching alternative strategies to the particular test problems being faced. Test efficiency is described as a means of comparing alternative test strategies and choosing that which ‘fits best’. One form of test, In‐Circuit test, is examined in more detail and guidelines for improving test coverage are described.