Implementation Of Turbo Decoder Research Articles

A VLSI Design for the LTE Turbo Decoder

Due to the need of high performance, new wireless telecommunications standards such asWIMAX and LTE are using turbo-codes as a forward error correction (FEC) choice.This design targets either a self-contained IP (Intellectual Property) or integration into the physical layer project. This work presents all steps for the implementation of an LTE standard turbo decoder: from algorithm modeling in high level programming language to architecture using a sliding window approach seeking throughput needed, getting into physical implementation at TSMC 65nm. Each aspect of the specification and performance were analyzed in their proper stages.

Revisiting the Max-Log-Map Algorithm With SOVA Update Rules: New Simplifications for High-Radix SISO Decoders

This paper proposes a new soft-input soft-output decoding algorithm particularly suited for low-complexity high-radix turbo decoding, called local soft-output Viterbi algorithm (local SOVA). The local SOVA uses the forward and backward state metric recursions just as the conventional Max-Log-MAP algorithm does, and produces soft outputs using the SOVA update rules. The proposed local SOVA exhibits a lower computational complexity than the Max-Log-MAP algorithm when employed for high-radix decoding in order to increase throughput, while having the same error correction performance even when used in a turbo decoding process. Furthermore, with some simplifications, it offers various trade-offs between error correction performance and computational complexity. For instance, employing the local SOVA algorithm for radix-8 decoding of the LTE turbo code reduces the complexity by 33% without any performance degradation and by 36% with a slight penalty of only 0.05 dB. Moreover, the local SOVA algorithm opens the door for the practical implementation of turbo decoders for radix 16 and higher.

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding

The multiplication of connected devices goes along with a large variety of applications and traffic types needing diverse requirements. Accompanying this connectivity evolution, the last years have seen considerable evolutions of wireless communication standards in the domain of mobile telephone networks, local/wide wireless area networks, and Digital Video Broadcasting (DVB). In this context, intensive research has been conducted to provide flexible turbo decoder targeting high throughput, multi-mode, multi-standard, and power consumption efficiency. However, flexible turbo decoder implementations have not often considered dynamic reconfiguration issues in this context that requires high speed configuration switching. Starting from this assessment, this paper proposes the first solution that allows frame-by-frame run-time configuration management of a multi-processor turbo decoder without compromising the decoding performances.

High throughput implementation of an adaptive serial concatenation turbo decoder

The complete design of a new high throughput adaptive turbo decoder is described. The developed system isprogrammable in terms of block length, code rate and modulation scheme, which can be dinamically changed from frame to frame, according to varied channel conditions or user requirements. A parallel architecture with 16 concurrent SISOs has been adopted to achieve a decoding throughput as high as 35 Mbit/s with 10 iterations, while error correcting performance are within 1dB from the capacity limit. The whole system, including the iterativedecoder itself, de-mapping and de-puncturing units, as well as the input double buffer, has been mapped to a single FPGA device, running at 80 MHz, with a percentage occupation of 54%.

Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs

Stochastic computing has been recently proposed for the hardware implementation of both low-density parity-check (LDPC) decoders and turbo decoders, which facilitate near-optimal error correction capabilities in wireless communication applications. Previous contributions have demonstrated that stochastic LDPC decoders offer an attractive tradeoff between their error correction capabilities, hardware performance, and timing-error tolerance. Motivated by this, we propose a pair of stochastic turbo decoder (STD) designs having significantly enhanced timing-error tolerance and significantly reduced processing latency. Moreover, we characterize the tradeoffs between chip area, energy efficiency, latency, throughput, and error correction capabilities of both the timing-error-tolerant STD and of the reduced-latency STD. We demonstrate that our proposed timing-error-tolerant STD operated at 1.20 V, with a clock period of 2.2 ns and in the presence of a three-standard deviation power supply variation of 7%, exhibits an unimpaired performance, compared with the state-of-the-art STD, operated at 1.20 V and 4 ns and with no power supply variations. This corresponds processing throughput improvement by a factor of 2.42 and energy consumption reduction by a factor of 4. Finally, we demonstrate that our proposed reduced-latency STD has a processing latency that is an order of magnitude lower than that of the state-of-the-art STD. This is despite reducing the chip area by a factor of 4, increasing the processing throughput by a factor of 65, while consuming only 0.005 times the energy of the state-of-the-art STD, when using binary phase-shift keying for communication over an additive white Gaussian noise channel having ${E_{b}/N_{0}=3}$ dB.

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl–Cocke-Jelinek–Raviv (Log-BCJR) algorithm, the limited processing throughputs of conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time wireless communication schemes. Motivated by this, we recently proposed a fully parallel turbo decoder (FPTD) algorithm, which eliminates these serial data dependencies, allowing parallel processing and hence offering a significantly higher processing throughput. In this paper, we propose a novel resource-efficient version of the FPTD algorithm, which reduces its computational resource requirement by 50%, which enhancing its suitability for field-programmable gate array (FPGA) implementations. We propose a model FPGA implementation. When using a Stratix IV FPGA, the proposed FPTD FPGA implementation achieves an average throughput of 1.53 Gb/s and an average latency of 0.56 $\mu \text{s}$ , when decoding frames comprising ${N}=720$ b. These are, respectively, 13.2 times and 11.1 times superior to those of the state-of-the-art FPGA implementation of the Log-BCJR long-term evolution (LTE) turbo decoder, when decoding frames of the same frame length at the same error correction capability. Furthermore, our proposed FPTD FPGA implementation achieves a normalized resource usage of 0.42 (kALUTs/Mb/s), which is 5.2 times superior to that of the benchmarker decoder. Furthermore, when decoding the shortest $N=40$ -b LTE frames, the proposed FPTD FPGA implementation achieves an average throughput of 442 Mb/s and an average latency of 0.18 $\mu \text{s}$ , which are, respectively, 21.1 times and 10.6 times superior to those of the benchmarker decoder. In this case, the normalized resource usage of 0.08 (kALUTs/Mb/s) is 146.4 times superior to that of the benchmarker decoder.

VLSI Implementation of Fully Parallel LTE Turbo Decoders

Turbo codes facilitate near-capacity transmission throughputs by achieving a reliable iterative forward error correction. However, owing to the serial data dependence imposed by the logarithmic Bahl–Cocke–Jelinek–Raviv algorithm, the limited processing throughputs of the conventional turbo decoder implementations impose a severe bottleneck upon the overall throughputs of real-time communication schemes. Motivated by this, we recently proposed a floating-point fully parallel turbo decoder (FPTD) algorithm, which eliminates the serial data dependence, allowing parallel processing and hence significantly reducing the number of clock cycles required. In this paper, we conceive a technique for reducing the critical datapath of the FPTD, and we propose a novel fixed-point version as well as its very large scale integration (VLSI) implementation. We also propose a novel technique, which allows the FPTD to also decode shorter frames employing compatible interleaver patterns. We strike beneficial tradeoffs amongst the latency, core area, and energy consumption by investigating the minimum bit widths and techniques for message log-likelihood ratio scaling and state metric normalization. Accordingly, the design flow and design tradeoffs considered in this paper are also applicable to other fixed-point implementations of error correction decoders. We demonstrate that upon using Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm low-power technology for decoding the longest long-term evolution frames (6144 b) received over an additive white Gaussian noise channel having $E_{b}/N_{0}=1~ \text {dB}$ , the proposed fixed-point FPTD VLSI achieves a processing throughput of 21.9 Gb/s and a processing latency of $0.28~ \mu \text {s}$ . These results are 17.1 times superior to those of the state-of-the-art benchmarker. Furthermore, the proposed fixed-point FPTD VLSI achieves an energy consumption of $2.69~ \mu \text {J}$ /frame and a normalized core area of $5~ \text {mm}^{\vphantom {R^{'}}2}/\text {Gb/s}$ , which are 34% and 23% lower than those of the benchmarker, respectively.

Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder

This paper presents hardware and bit-error-rate (BER) performance analysis of simplified maximum-a-posteriori (MAP) algorithms based on piece-wise-linear-approximations and Maclaurin-series-expansion for the turbo codes. From this comparative study, a simplified MAP algorithm with optimal BER performance is selected and an architecture suitable for high speed application is suggested for the design of soft-input-soft-output (SISO) unit. Subsequently, a quantitative model is proposed for estimating the amount of memory required by SISO unit in terms of sliding window size, data width of internal metrics and total number of systematic and parity bits. Thereafter, a non-parallel-radix-2 architecture of turbo decoder which incorporates SISO unit and quadratic-permutation-polynomial interleaver is presented. Application-specific-integrated-circuit (ASIC) implementation of this turbo decoder is carried out in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology node and its power consumption, design area and operating clock frequency are reported. Finally, a comparison with similar contributions in the literature has shown that the implemented turbo decoder achieves energy efficiency of 0.28 nJ/b/iteraions. Similarly, it has achieved a highest throughput of 28 Mbps among radix-2 and radix-4 non-parallel turbo decoders.

Low Complexity Reconfigurable Turbo Decoder for Wireless Communication Systems

The development of turbo codes has allowed for near-Shannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate decoding techniques, the circuit complexity and power consumption of turbo decoder implementations can often be prohibitive for power-constrained systems. To address these issues, a reduced complexity, low power turbo decoder is proposed, specifically optimized for contemporary FPGA devices. The key power-saving technique in this work is the use of decoder run-time dynamic reconfiguration for different constraint lengths. Max-Log-MAP algorithm, which offers a good compromise between performance and complexity, is selected for implementation. One of the components of this algorithm namely, the branch metric calculation unit is studied and a new design of this unit is proposed. The branch metric normalization scheme proposed here builds upon a sliding window approach and is capable of providing high speed. The implementation of SISO-based turbo decoder with three different constraint lengths (K) on a field programmable gate array (FPGA) achieves a speed of 86.08 } more than the conventional design. The power consumption of the device for various constraint lengths is measured using synopsis design compiler- simplicity premier with DCP 2008 tool. The proposed reconfigurable architecture for a constraint length ‘K’ consumes very few megawatt of power more than the non-reconfigurable architecture for the corresponding constraint length.

Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes

Soft-input soft-output (SISO) maximum a-posteriori (MAP) decoders for convolutional codes (CCs) are an integral part of many modern wireless communication systems. Specifically, SISO-MAP decoding forms the basis for turbo decoders, as, e.g., specified for HSDPA or 3GPP-LTE, or for iterative detection and decoding in multiple-input multiple-output wireless systems, such as IEEE 802.11n. In this paper, we investigate the silicon-area, throughput, and energy-efficiency trade-offs associated with SISO-MAP decoders based on the algorithm developed by Bahl, Cocke, Jelinek, and Raviv (BCJR). To this end, we develop radix-2 and radix-4 architectures for high-throughput SISO-MAP decoding of CCs having 4, 8, 16, 32, and 64 states and present corresponding implementation results in 180 nm, 130 nm, and 90 nm CMOS technology. We validate technology-scaling rules and finally demonstrate the use of the presented trade-off analysis by identifying the key design parameters for parallel turbo-decoder implementations.

Low Power Design of near Shannon Limit Coding: Turbo Codes

In this paper secure channel coding schemes based on Turbo Codes are suggested and implemented. The design of encoder using Recursive Systematic Code (RSC) with puncturing techniques is presented. Component decoders are implemented by Log-Maximum-a-Posteriori (Log-MAP) algorithm and thereafter implementation of overall turbo decoder is illustrated in detail. Finally we have investigated low power design technique of the turbo decoder design with variable iteration techniques.

Design and VLSI Implementation of a High Throughput Turbo Decoder

Design and VLSI Implementation of a High Throughput Turbo Decoder

An FPGA realization of simplified turbo decoder architecture

The key issue of applying Turbo codes is to find an efficient implementation of turbo decoder. This paper addresses the implementation of a simplified and efficient turbo decoder in field programmable gate array (FPGA) technology. A simplified and efficient implementation of a Turbo decoder with minor performance loss has been proposed. An integer Turbo decoder based on the standard 2’s complement number system after considering the issues of dynamic range, truncation effect and other algorithm related subjects has been introduced. The efficient implementation comes from algorithm modification, integer arithmetic and compact hardware management. Based on the Max-Log-MAP decoding algorithm, the branch metric is modified by weighting a priori value, resulting in a significant BER improvement. The Turbo decoder takes in 8-level integer inputs generates 7-bit soft-decisions and calculates all metrics on integers, avoiding complex floating point or fixed-point arithmetic. By manipulating memory address, delay associated with interleaving and de-interleaving is eliminated, resulting in much higher throughput. Also, by taking advantage of identical decoder function, Turbo decoder is implemented in a single-decoder structure, making efficient use of memory and logic cells. Key words: Turbo, Max-Log-MAP, field programmable gate array, bit error ratio.

Parallelism Efficiency in Convolutional Turbo Decoding

Parallel turbo decoding is becoming mandatory in order to achieve high throughput and to reduce latency, both crucial in emerging digital communication applications. This paper explores and analyzes parallelism techniques in convolutional turbo decoding with the BCJR algorithm. A three-level structured classification of parallelism techniques is proposed and discussed: BCJR metric level parallelism, BCJR-SISO decoder level parallelism, and Turbo-decoder level parallelism. The second level of this classification is thoroughly analyzed on the basis of parallelism efficiency criteria, since it offers the best tradeoff between achievable parallelism degree and area overhead. At this level, and for subblock parallelism, we illustrate how subblock initializations are more efficient with the message passing technique than with the acquisition approach. Besides, subblock parallelism becomes quite inefficient for high subblock parallelism degree. Conversely, component-decoder parallelism efficiency increases with subblock parallelism degree. This efficiency, moreover, depends on BCJR computation schemes and on propagation time. We show that component-decoder parallelism using shuffled decoding enables to maximize architecture efficiency and, hence, is well suited for hardware implementation of high throughput turbo decoder.

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm2/Mbps and energy efficiency of 0.55 nJ/b/iter.

An improved low-power high-throughput log-MAP turbo decoder

This paper presents an efficient implementation of a high-throughput low-power turbo decoder. The design of the component decoder has been optimized so as to achieve low power implementation of the turbo decoder. A collision-free interleaver has been designed for appropriate parallel decoding operations. Performance enhancing techniques such as parallel processing and pipelining have been applied to realize the highly recursive and complex maximum a posteriori probability (MAP) decoder. Area, power and throughput of the proposed decoder architecture compare favorably with those of an architecture which has been recently reported in literature. The designed decoder, which achieves a throughput of 930 Mbps while consuming 265 mW of power, can be considered to be suitable for a number of real time applications.

Performance optimization and parallelization of turbo decoding for software-defined radio

This paper describes the optimization, parallelization, and simulated execution performance of a software double-binary turbo decoder implementation supporting the WiMAX standard suitable for software-defined radio (SDR). Turbo codes offer excellent error-correcting performance, but they introduce significant computational demands in a communication system. In order to enhance execution performance for SDR, software for a turbo decoder based on the maximum a posteriori (MAP) algorithm was first adapted from the open-source Coded Modulation Library. Optimization and parallelization of the adapted software were then pursued and assessed with a multiprocessor version of the SimpleScalar simulator. Simulation results show that serial optimizations of the original adapted stand-alone C decoder software improve performance by more than 200%. The use of special instructions to accelerate important functions provides a further benefit of nearly 40% relative to the new baseline for performance. Exploiting the parallelism available in the MAP algorithm then yields a speedup of 10.8 on 12 processors. Simulation also shows that cache effects do not have a significant impact on parallel execution times.

A Programmable Max-Log-MAP Turbo Decoder Implementation

In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology.

Implementation Issues in Turbo Decoding for 3GPP FDD Receiver

In the Frequency Division Duplex (FDD) mode of the Third Generation Partnership Project (3GPP) standard, implementation of the turbo decoder, especially for the mobile equipments, faces design decisions related to computational complexity, power efficiency, and memory requirements. In this paper we compare different approaches of low complexity implementation of the turbo decoder, with emphasis on the issues of signal scaling and quantization, the sliding window operation for memory size reduction and the iteration stopping algorithms. The demodulated signal at the output of the RAKE receiver may have a wide dynamic range and it may require many bits of precision. In order to overcome the numerical precision problem and to prevent Log Likelihood ratio (LLR) metric overflow, a scaling algorithm must be used. Our simulation results indicate that the Average Absolute (AA) algorithm using dynamic scaling outperforms other scaling schemes and it is less sensitive to the channel conditions. One of the major challenges in the implementation of a practical turbo decoder is optimization of memory requirements. In this paper we evaluate the performance of the sliding window algorithm using different main and guard window sizes. We show that the bit and block error rate performance of the sliding window scheme mainly depend on the guard window size rather than the main window size. The simulation results indicate that small guard window sizes can significantly decrease the iteration gain for large frames in fast fading channels. Iteration stopping algorithms reduce the power consumption and the latency of the decoder and help to dedicate more resources to other functions of the receiver. The block error distribution in the fading channels makes it even more essential to use an iteration stopping rule. Our simulations conclude that a rule called the minimum absolute value appears to be a very effective, low complexity and robust algorithm.