State Machine Implementation Research Articles

A microservice based control architecture for mobile robots in safety-critical applications

Mobile robots have become more and more common in public space. This increases the importance of meeting safety requirements of autonomous robots. Simple mechanisms, such as emergency braking, alone do not suffice in these highly dynamic situations. Moreover, actual robotic control approaches in literature and practice do not take safety particularly into account. A more sophisticated situational approach for assessment and planning is needed as part of the high-level process control. This paper presents the concept of a safety-critical Robot Control Architecture for mobile robots based on microservices and a Hierarchical Finite State Machine. It expands already existing architectures by drastically reducing the amount of centralized logic and thus increasing the overall system’s level of concurrency, interruptibility and fail-safety. Furthermore, it introduces new potential for code reuse that allows for straightforward implementation of safety mechanisms such as internal diagnostics systems. In doing so, this concept presents the template of a new type of state machine implementation. It is demonstrated with the application of a delivery robot, which was implemented and operated in real public during a broader research project.

Autonomous diode laser weeding mobile robot in cotton field using deep learning, visual servoing and finite state machine

Small autonomous robotic platforms can be utilized in agricultural environments to target weeds in their early stages of growth and eliminate them. Autonomous solutions reduce the need for labor, cut costs, and enhance productivity. To eliminate the need for chemicals in weeding, and other solutions that can interfere with the crop’s growth, lasers have emerged as a viable alternative. Lasers can precisely target weed stems, effectively eliminating or stunting their growth. In this study an autonomous robot that employs a diode laser for weed elimination was developed and its performance in removing weeds in a cotton field was evaluated. The robot utilized a combination of visual servoing for motion control, the Robotic operating system (ROS) finite state machine implementation (SMACH) to manage its states, actions, and transitions. Furthermore, the robot utilized deep learning for weed detection, as well as navigation when combined with GPS and dynamic window approach path planning algorithm. Employing its 2D cartesian arm, the robot positioned the laser diode attached to a rotating pan-and-tilt mechanism for precise weed targeting. In a cotton field, without weed tracking, the robot achieved an overall weed elimination rate of 47% in a single pass, with a 9.5 second cycle time per weed treatment when the laser diode was positioned parallel to the ground. When the diode was placed at a 10°downward angle from the horizontal axis, the robot achieved a 63% overall elimination rate on a single pass with 8 seconds cycle time per weed treatment. With the implementation of weed tracking using DeepSORT tracking algorithm, the robot achieved an overall weed elimination rate of 72.35% at 8 seconds cycle time per weed treatment. With a strong potential for generalizing to other crops, these results provide strong evidence of the feasibility of autonomous weed elimination using low-cost diode lasers and small robotic platforms.

Experimental assessment of a JANUS-based consensus protocol

This paper proposes a distributed, JANUS-based protocol that enables an underwater acoustic network to reach consensus on arbitrary local opinions as numeric state variables. An envisioned scenario where nodes shall agree on parameters describing the acoustic environment is used to evaluate the protocol. The scenario exemplifies the protocol’s potential in future applications where nodes use the environment description to decide on appropriate modulation and coding schemes.The evaluation is based on numerical simulations and sea experiments in a challenging acoustic environment. The numerical simulations allowed examining the performance for different parameter values regarding the timing of transmission events and state transitions in the finite state machine implementation of the protocol. The best parameter configuration was used in the sea experiments conducted in a bay in the Baltic Sea. The experiments comprised several deployments of five to six commercial modems.Results from the experiments show that the protocol can achieve a consensus up to 89% of the time in the tested environment, and up to 96% of the time if the state variables are permitted to differ by one discretisation step maximum across the network. In addition, if the network separates due to environmental conditions, connected components appear to achieve consensus more often when the links are more reliable. Finally, it is shown that when different consensus processes are active in parallel, packets from one process do not interfere with the opinions in different processes, besides the existing probability of packet loss due to packet collision.

Mapping Outputs and States Encoding Bits to Outputs Using Multiplexers in Finite State Machine Implementations

This paper proposes a new technique for implementing Finite State Machines (FSMs) in Field Programmable Gate Arrays (FPGAs). The proposed approach extends the called column compaction in two ways. First, it is applied to the state-encoding bits in addition to the outputs, allowing a reduction in the number of logic functions required both by the state transition function and by the output function. Second, the technique exploits the dedicated multiplexers usually included in FPGAs to increase the number of columns that can be compacted. Unlike conventional state-encoding techniques, the proposed approach reduces the number of logic functions instead of their complexity. An Integer Linear Programming (ILP) formulation that maximizes the number of compacted columns has been proposed. In order to evaluate the effectiveness of the proposed approach, experimental results using standard benchmarks are presented. In most cases, the proposed approach reduces the number of used Look-Up Tables (LUTs) with respect to the conventional FSM implementation.

Fast Adaptive Character Animation Synthesis Based on Greedy Algorithm

On the premise of ensuring the animation effect and real-time performance, it is of great significance and value for large-scale group character animation synthesis how to reduce the disaster coincidence degree among various models of fast adaptive character animation synthesis. The realization method of object-oriented finite state machine is studied in detail. Finite state machine (FSM) is an efficient behavior modeling method, which can describe the behavioral decisions of fast adaptive character animation synthesis in a complex virtual environment. Based on the implementation defects of the finite state machine in the traditional structure, using object-oriented thinking, combined with the state design mode, we further studied a finite state machine implementation method based on object-oriented technology. This achieves code reuse and simple program maintenance. The effect is extensible and effectively overcomes the shortcomings of traditional character animation synthesis. Secondly, the multipath matching tracking algorithm of the greedy algorithm is studied to generate multiple candidate sets through multiple paths, and finally, the candidate set with the minimum residual error is selected as the estimated support set, so as to improve the reconstruction performance. Further, based on the idea of multipath, using the regularization method of the ROMP algorithm, the regularized multipath matching tracking RMSP algorithm is proposed. It uses the regularized subset method to generate multiple paths and chooses the path with the fastest residual reduction as the support set of this iteration. The simulation results show that the RMSP algorithm has better reconstruction performance than the SP algorithm.

Finite State Machine-Based Realization of Sparse Matrix Converter

Matrix converters (MCs), compared to traditional back-to-back converters, offer a series of advantages for ac-ac power conversion. However, increased realization complexity and cost have restricted the proliferation of MCs to a limited number of commercially available solutions. In this article, an efficient sparse matrix converter realization is presented as a step toward the development of simpler, lower-cost, and reliable realization architectures. In contrast to common practices that utilize a flexible logic fabric, such as a field programmable gate array or a complex programmable logic device, and a digital signal processor, the proposed implementation is based on a single commercial off-the-shelf microcontroller unit. This method is possible due to the novel implementation of a synchronous finite state machine that realizes the four-step commutation strategy required by the current source rectifier stage. Since the complete control scheme is implemented in one IC, it inherently avoids important MC realization issues, such as communication delays and synchronization between controllers. In addition, both software and hardware requirements are reduced and lower the overall development effort and cost.

Methodology for Distributed-ROM-Based Implementation of Finite State Machines

This brief explores the optimization of distributed-ROM-based finite state machine (FSM) implementations as an alternative to conventional implementations based on look-up tables (LUTs). In distributed-ROM implementations, LUTs with constant output value (called constant LUTs) and LUTs with the same content (called equivalent LUTs) can be saved. We propose a methodology to implement FSMs using distributed ROM that includes: 1) a greedy state encoding algorithm; 2) an algorithm to find the way of interconnecting the address signals to the ROM that maximize the number of constant or equivalent LUTs; and 3) a set of architectures to implement the columns of the ROM. The results obtained have been compared with conventional LUT-based implementations using standard benchmarks. The proposed technique reduces the number of LUTs in a 91% of cases and increases the speed in all cases.

State Machine Implementation for Human Object Tracking using Combination of MobileNet, KCF Tracker, and HOG Features

State Machine Implementation for Human Object Tracking using Combination of MobileNet, KCF Tracker, and HOG Features

Design and Evaluation of Low-Cost and Energy-Efficient Magneto-Inductive Sensor Nodes for Wireless Sensor Networks

A set of low-cost and energy-efficient sensor nodes are designed and implemented using magnetic induction (MI) communications for wireless sensor networks (WSN), which are especially suited for underwater and underground networks where the conventional mode of communication does not perform well. Hardware features of the sensor nodes include a three-dimensional MI coil antenna and its different configurations for transmit and receive operations, low-power circuits for sleep mode, several types of sensors, data storage, and best transmit/receive circuits selected to achieve the maximum communication range with low-power consumption. The material cost of a sensor node is less than $\$$ 100 USD at the prototyping stage and can be drastically reduced at volume production. Software design utilizes low-power modes of microcontrollers and power supply circuits, state machine implementation of sleep, receive, sensing, and transmit modes, range estimation from received signal strength indicators (RSSIs), and medium access protocols, such as carrier sense multiple access (CSMA). Extensive lab and field tests conducted with the sensor nodes demonstrate promising performance in terms of low-power consumption, communication range, range estimation, and robustness against mismatching of coil orientations, and networking capabilities. The current consumption is as low as 60 $\mu$ A in sleep mode, 0.49 $\text{m}$ A in receive mode, and 253 $\text{m}$ A in transmit mode. The sensor node achieves a maximum of 40-m range with 1 kb/s data rate at 125 kHz carrier frequency.

A comparison of schedulability analysis methods using state and digraph models for the schedulability analysis of synchronous FSMs

Synchronous reactive models are widely used in the development of embedded software and systems. The schedulability analysis of tasks obtained as the code implementation of synchronous finite state machines (FSMs) can be performed in several ways. One possible option is to leverage the correspondence between the execution of actions in an FSM and the execution of jobs in a digraph task model, thereby applying all the analysis methods developed for these digraph task systems. Another option is to directly leverage the state information and use dynamic programming methods to compute the worst possible sequence of (state dependent) reactions for a given FSM model. In this paper we compare these analysis methods in terms of accuracy and runtime.

FSM Based VLSI Architecture for Decision Based Neighborhood Referred Asymmetrical Trimmed Variant Filter

A VLSI architecture using Finite State Machine Based for logic based vicinity inferred asymmetrically trimmed variants filter is proposed. The filter was checked on MATLAB environment and found to suppress high density salt and pepper noise. For better speed & power constraints the algorithm was implemented on VIRTEX FPGA using VHDL as part of system on chip implementation. The Proposed VLSI architecture uses one hot encoding for Finite state machine implementation of the filter. The architecture has 5 different modules and each computes the desired values using Finite state machine. There are three main computations implemented in this filter as separate module titled asymmetrical trimmed median, Midpoint, Mean of 4 Neighbors and local mean. The FSM uses one hot encoding Technique for lower power consumption. The architecture was targeted on FPGA device XCV1000-4bq560 using VHDL. The synthesis of the architecture utilizes 2744 slices of FPGA, operates at 54.630 MHz frequency and consumes 32 mw of power.

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

The mathematical model for designing a complex digital system is a finite state machine (FSM). Applications such as digital signal processing (DSP) and built-in self-test (BIST) require specific operations to be performed only in the particular instances. Hence, the optimal synthesis of such systems requires a reconfigurable FSM. The objective of this paper is to create a framework for a reconfigurable FSM with input multiplexing and state-based input selection (Reconfigurable FSMIM-S) architecture. The Reconfigurable FSMIM-S architecture is constructed by combining the conventional FSMIM-S architecture and an optimized multiplexer bank (which defines the mode of operation). For this, the descriptions of a set of FSMs are taken for a particular application. The problem of obtaining the required optimized multiplexer bank is transformed into a weighted bipartite graph matching problem where the objective is to iteratively match the description of FSMs in the set with minimal cost. As a solution, an iterative greedy heuristic based Hungarian algorithm is proposed. The experimental results from MCNC FSM benchmarks demonstrate a significant speed improvement by 30.43% as compared with variation-based reconfigurable multiplexer bank (VRMUX) and by 9.14% in comparison with combination-based reconfigurable multiplexer bank (CRMUX) during field programmable gate array (FPGA) implementation.

Reverse engineering concurrent UML state machines using black box testing and genetic programming

This paper presents a technique for reverse engineering, a software system generated from a concurrent unified modeling language state machine implementation. In its first step, a primitive sequential finite-state machine (FSM) is deduced from a sequence of outputs emitted from black box tests applied to the systems’ input interface. Next, we provide an algorithmic technique for decomposing the sequential primitive FSM into a set of concurrent (orthogonal) primitive FSMs. Lastly, we show a genetic programming machine learning technique for discovering local variables, actions performed on local and non-binary output variables, and two types of intra-FSM loops, called counting-loops and while-loops.

Контрактный метод спецификации реактивных требований

The verification of many practical systems - in particular, embedded systems - involves processes executing over time, for which it is common to use models based on temporal logic, in either its linear (LTL) or branching (CTL). Some of today’s most advanced automatic program verifiers, however, rely on non-temporal theories, particularly Hoare-style logic. Can we still take advantage of this sophisticated verification technology for more challenging systems? As a step towards a positive answer, we have defined a translation scheme from temporal specifications to contract-equipped object-oriented programs, expressed in Eiffel and hence open for processing by the AutoProof program prover. We have applied this scheme to a published CTL model of a widely used realistic example, the “landing gear” system which has been the subject of numerous competing specifications. An attempt to verify the result in AutoProof failed to prove one temporal property, which on further inspection seemed to be wrong in the original published model, even though the published work claimed to have verified an Abstract State Machine implementation of that model. Correcting the CTL specification to reflect the apparent informal attempt, re-translating again to contracted Eiffel and re-running the verification leads to success. The LTL-to-contracted-Eiffel process is still ad hoc, and tailored to generate the kind of scheme that the target verification tool (AutoProof) can handle best, rather than the simplest or most elegant scheme. Even with this limitation, the results highlight the need for rigor in the verification process, and (on the positive side) demonstrate that the highly advanced mechanized proof technology developed over several decades for the verification of traditional programs also has the potential of handling the demanding needs of embedded systems and other demanding contemporary developments.

High-Speed and Area-Efficient Reconfigurable Multiplexer Bank for RAM-Based Finite State Machine Implementations

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.

On the global optimization of checking sequences for finite state machine implementations

A checking sequence for a given domain of deterministic finite state machine implementations is an input sequence for which exactly the non-faulty members of the domain produce a non-faulty response. In the paper, we reconsider a popular family of methods which construct a checking sequence by performing its digraph-based global optimization. Recently, it was demonstrated that many of the methods are unsafe. As a remedy, a simple, but sufficient set of additional constraints on the structure of the employed digraph was introduced. In this paper, we show that the constraints sometimes ban also some of those originally considered checking sequence candidates which are sound. To safely restore the original power of the checking sequence construction approach, we perform its thorough re-engineering. This results in a very transparent and flexible generic method from which various methods of practical interest, both new ones and analogues of the traditional ones, can be derived simply by specialization.

Accelerated model-based robustness testing of state machine implementations

In this paper, we present an approach for accelerating model-based robustness testing of state-based software components. We use the Z3 SAT solver to derive executable test cases fully automatically from a state model based on a UML Statechart. The test cases are paths along the Statechart comprising states and transitions. The main advantage of our approach is an accelerated execution of the test cases by refining already reached states as starting points for further test cases using reverse execution. Furthermore, the presented approach is able to check whether a correct target state has been reached or not when executing the path-based test cases using runtime verification and therefore increases the test significance. The runtime verification is done without instrumenting the source code of the component under test.

Designing Run-Time Environments to Have Predefined Global Dynamics

The stability and the predictability of a computer network algorithm's performance are as important as the main functional purpose of networking software. However, asserting or deriving such properties from the finite state machine implementations of protocols is hard and, except for singular cases like TCP, is not done today. In this paper, we propose to design and study run-time environments for networking protocols which inherently enforce desirable, predictable global dynamics. To this end we merge two complementary design approaches: (i) A design-time and bottom up approach that enables us to engineer algorithms based on an analyzable (reaction) flow model. (ii) A run-time and top-down approach based on an autonomous stack composition framework, which switches among implementation alternatives to find optimal operation configurations. We demonstrate the feasibility of our self-optimizing system in both simulations and realworld Internet setups.

An object-oriented implementation of concurrent and hierarchical state machines

ContextState machine diagrams are a powerful means to describe the behavior of reactive systems. Unfortunately, the implementation of state machines is difficult, because state machine concepts, like states, events and transitions, are not directly supported in commonly used programming languages. Most of the implementation approaches known so far have one or more serious drawbacks: they are difficult to understand and maintain, lack in performance, depend on the properties of a specific programming language or do not implement the more advanced state machine features like hierarchy, concurrency or history. ObjectiveThis paper proposes and examines an approach to implement state machines, where both states and events are objects. Because the reaction of the state machine depends on two objects (state and event), a method known as double-dispatch is used to invoke the transition between the states. The aim of this work is to explore this approach in detail. MethodTo prove the usefulness of the proposed approach, an example was implemented with the proposed approach as well as with other commonly known approaches. The implementation strategies are then compared with each other with respect to run-time, code size, maintainability and portability. ResultsThe presented approach executes fast but needs slightly more memory than other approaches. It supports hierarchy, concurrency and history, is human authorable, easy to understand and easy to modify. Because of its pure object-oriented nature depending only on inheritance and late binding, it is extensible and can be implemented with a wide variety of programming languages. ConclusionThe results show that the presented approach is a useful way to implement state machines, even on small micro-controllers.

Semi-Automatic Car Anti-Theft Design using ATMega168 Microcontroller

ABSTRACT The design and manufacture of anti-theft systems have become more and more complex due to the rise in complexity of theft in the system. Most of the anti-theft systems available on market, are the alarm types that audibly deter some thieves away but do not prevent one’s car from being stolen and also may not be good enough to meet the growing complexity of theft in the country. This paper presents a simpler and a more efficient car anti-theft system that provides users with improved security by the use of efficient access mechanisms and immobilization systems. Access mechanisms were put in place to request authorization from the user and a hidden button which gives permission to start the car when it is pressed. Immobilizers where put in place to disable car in case it is stolen. The system was based on the ATMega168 microcontroller programming which involve the use electronic components such as limit switches, LEDs and transistors. The programming concept follows the graph theory well known as state machine implementation in Micro-processing and the language adopted was the C programming language.