Digital Hardware Implementation Research Articles

Parametric controllable planar multi-scroll chaotic attractors in a 3-D memristive tabu learning single neuron model

In this paper, a three-dimensional (3D) autonomous tabu learning single neuron model is proposed, which is achieved by using a sinusoidal activation function and introducing a memristor synapse. This model exhibits the remarkable capability to produce a series of planar multi-scroll chaotic attractors, and its unique feature lies in the ability to control the number of scrolls. The investigation of the planar multi-scroll chaotic attractors and its dynamical behaviors is conducted through the analysis of phase plane portraits, bifurcation diagrams, and spectral entropies. The numerical simulations unveil a compelling relationship between the number of chaotic scrolls and specific control parameters governing the model. To further validate the findings, a 3D autonomous tabu learning single neuron model is implemented on a digital hardware platform. In an effort to extend the practical significance of this research, the multi-scroll chaotic phenomenon generated by the proposed model is deployed for image encryption. The fusion of mathematical modeling, digital hardware implementation, and practical application underscores the universality and significance of the proposed single neuron model in the fields of chaotic systems and engineering applications.

FPGA-Microprocessor Based Sensor for Faults Detection in Induction Motors Using Time-Frequency and Machine Learning Methods.

Induction motors (IM) play a fundamental role in the industrial sector because they are robust, efficient, and low-cost machines. Changes in the environment, installation errors, or modifications to working conditions can generate faults in induction motors. The trend on IM fault detection is focused on the design techniques and sensors capable of evaluating multiple faults with various signals using non-invasive analysis. The methodology is based on processing electric current signals by applying the short-time Fourier transform (STFT). Additionally, the computation of the mean and standard deviation of infrared thermograms is proposed as main indicators. The proposed system combines both parameters by means of Support Vector Machine and k-nearest-neighbor classifiers. The development of the diagnostic system was done with digital hardware implementations using a Xilinx PYNQ Z2 card that integrates an FPGA with a microprocessor, thus taking advantage of the acquisition and processing of digital signals and images in hardware. The proposed method has proved to be effective for the classification of healthy (HLT), misalignment (MAMT), unbalance (UNB), damaged bearing (BDF), and broken rotor bar (BRB) faults with an accuracy close to 99%.

Digital Hardware Implementation of Morris-Lecar, Izhikevich, and Hodgkin-Huxley Neuron Models With High Accuracy and Low Resources

Digital Hardware Implementation of Morris-Lecar, Izhikevich, and Hodgkin-Huxley Neuron Models With High Accuracy and Low Resources

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

Dynamical analysis, geometric control and digital hardware implementation of a complex-valued laser system with a locally active memristor

In order to make the peak and offset of the signal meet the requirements of artificial equipment, dynamical analysis and geometric control of the laser system have become indispensable. In this paper, a locally active memristor with non-volatile memory is introduced into a complex-valued Lorenz laser system. By using numerical measures, complex dynamical behaviors of the memristive laser system are uncovered. It appears the alternating appearance of quasi-periodic and chaotic oscillations. The mechanism of transformation from a quasi-periodic pattern to a chaotic one is revealed from the perspective of Hamilton energy. Interestingly, initial-values-oriented extreme multi-stability patterns are found, where the coexisting attractors have the same Lyapunov exponents. In addition, the introduction of a memristor greatly improves the complexity of the laser system. Moreover, to control the amplitude and offset of the chaotic signal, two kinds of geometric control methods including amplitude control and rotation control are designed. The results show that these two geometric control methods have revised the size and position of the chaotic signal without changing the chaotic dynamics. Finally, a digital hardware device is developed and the experiment outputs agree fairly well with those of the numerical simulations.

Data-Driven Control for Continuum Robots Based on Discrete Zeroing Neural Networks

The effectiveness of continuous-time zeroing neural network (CZNN) in continuum robot control has been preliminarily verified. However, CZNN is not friendly to digital devices and hardware implementation. Although discrete ZNN (DZNN) has been investigated in other tasks, all the existing DZNNs are designed with fixed time steps, which cannot meet the needs of different tasks. This motivates us to develop a generic DZNN model with variable number of time steps and apply it to continuum robot control. In this paper, we present a data-driven scheme based on CZNNs to learn the unknown kinematics of continuum robots and solve the kinematic control problem. Further, a unified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> -step forward discretization formula is derived to discretize the CZNN-based scheme into DZNN-based control algorithms. Finally, we take the 1-step and the 3-step algorithms as examples to show the discretization process, and verify their efficacy by simulations and experiments.

Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments

Digital hardware implementations of Spiking Neural Networks designed using Selective Input Sparsity (SIS) are proposed for edge inference applications in image classification where the image acquisition environment is controlled. These sparsely connected networks are well-suited to area-constrained applications as they require fewer neurons and synapses than baseline Fully Connected (FC) networks of analogous structures. The SIS networks were validated on FPGA, and baseline FC networks were also implemented on FGPA for comparison. The SIS networks require fewer hardware resources and make inferences faster than the baseline FC networks without substantial impact on the classification accuracy.

Efficient Digital Realization of Endocrine Pancreatic β-Cells.

The accurate implementation of biological neural networks, which is one of the important areas of research in the field of neuromorphic, can be studied in the case of diseases, embedded systems, the study of the function of neurons in the nervous system, and so on. The pancreas is one of the main organs of human that performs important and vital functions in the body. One part of the pancreas is an endocrine gland and produces insulin, while another part is an exocrine gland that produces enzymes for digesting fats, proteins and carbohydrates. In this paper, an optimal digital hardware implementation for pancreatic β-cells, which is the endocrine type, is presented. Since the equationsof the original model include nonlinear functions, and the implementation of these functions results in greater use of hardware resources as well as deceleration, to achieve optimal implementation, we have approximated these nonlinear functions using the base-2 functions and LUT. The results of dynamic analysis and simulation show the accuracy of the proposed model compared to the original model. Analysis of the synthesis results of the proposed model on the Spartan-3 XC3S50 (5TQ144) reconfigurable board (FPGA) shows the superiority of the proposed model over the original model. These advantages include using fewer hardware resources, a performance almost twice as fast, and 19% less power consumption, than the original model.

Investigation on the Wilson Neuronal Model: Optimized Approximation and Digital Multiplierless Implementation.

Neuromorphic engineering is an essential science field which incorporates the basic aspects of issues together such as: physics, mathematics, electronics, etc. The primary block in the Central Nervous System (CNS) is neurons that have functional roles such as: receiving, processing, and transmitting data in the brain. This paper presents Wilson Multiplierless Neuron (WMN) model which is a modified version of the original model. This model uses power-2 based functions, Look-Up Table (LUT) approach and shifters to apply a multiplierless digital realization leads to overhead costs reduction and increases in the final system frequency. The proposed model specifically follows the original neuron model in case of spiking patterns and also dynamical pathways. To validate the proposed model in digital hardware implementation, the FPGA board (Xilinx Virtex II XC2VP30) can be used. Hardware results show the increasing in the system frequency compared with the original model and other similar papers. Numerical results demonstrate that the proposed system speed-up is 210 MHz that is higher than the original one, 85 MHz. Additionally, the overall saving in FPGA resources for the proposed model is 96.86 % that is more than the original model, 95.13 %. From case study viewpoint for CNS consideration, a network consisting of Wilson neurons, synapses, and astrocytes have been considered to test the controlling effects on LTP and LTD processes for investigating the neuronal diseases (medical approaches) such as Epilepsy.

Wideband Radio Frequency Interference Cancellation for High-Sensitivity Phased Array Receivers With True Time Delays and Truncated Hadamard Projection

Radio frequency interference (RFI) is a significant challenge for high-sensitivity phased array instruments. RFI can be suppressed using digital signal processing, but to improve dynamic range for wideband RFI, it can be desirable to remove interference in the analog domain before sampling. In previous work, it has been shown that analog true time delay (TTD) stages with a truncated Hadamard transform can place a wide-band spatial null on RFI from a given direction of arrival. We show that TTD and Hadamard projection is mathematically equivalent to a bank of classical narrow-band subspace projection beamformers, but with a structure that allows efficient implementation in either analog circuitry or digital hardware. We analyze how loss in the TTD blocks and time delay errors affect beamformer performance and propose methods for calibrating time delays. Simulation results show that ideal TTD and Hadamard projection matches the bank of subspace projection beamformers and places deep nulls over wideband RFI signals while achieving SNR performance comparable to the maximum signal-to-interference and -noise ratio beamformer.

Analog/Digital Multiplierless Implementations for Nullcline-Characteristics-Based Piecewise Linear Hindmarsh-Rose Neuron Model

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme.

High-impedance fault detection on downed conductor in overhead distribution networks

High impedance faults (HIF) may occur in the medium voltage distribution systems and constitute a danger to human beings. Many cases of HIF are caused due to downed power cables in the distribution network. These cables in contact with the ground generate a great risk to the population, animals and fire risk. In this paper, a methodology for detecting HIF, generated by cable breakage, is presented. The algorithm is based on the analysis of the harmonic and symmetrical components of the current. The method aims to gain reliability in HIF detection, where the detection of conductor breakage incorporated into the method allows a better distinction of HIF from other events. A distribution network based on a Brazilian real feeder was implemented, as well as two well know HIF models. The method is validated using real-time digital simulations and hardware implementation, or HIL (hardware-in-the-loop) concept with OPAL-RT real-time simulator. A comparison with other methods is also performed in order to evaluate the performance of the method. The results show that the proposed methodology has presented a better performance under different types of HIF, models of HIF, and achieved a general accuracy of 90% and security of 100% for the tests performed.

Multiple Source Angle of Arrival Estimation Through Phase Interferometry

The evaluation of the Angle of Arrival (AoA) of a received signal is a basic tool for many RF location systems. This brief introduces a new technique for estimating the AoA via a phase interferometric approach when multiple sources are present. After briefly recalling some widespread algorithms and methods, the proposed technique is described from a mathematical point of view. This brief also reports the results of an experimental campaign, along with a comparison of the results with those obtained using the Estimation of Signal Parameters via Rotational Invariant Techniques (ESPRIT) and Root MUltiple SIgnal Classification (RMUSIC) algorithms. The experiments demonstrate that the proposed approach gives accurate results with low computational complexity, thus being eligible for direct implementation in digital custom hardware.

High-performance and ultra-compact spike-based architecture for real-time acoustic echo cancellation

In recent years, the implementation of advanced adaptive filters in embedded devices for acoustic echo cancellation has increased because most of them are used in portable devices, especially in Internet of Things systems, in which high-performance and low-area digital hardware implementations are required. In this work, we present a high-performance and ultra-compact spike-based hardware architecture to efficiently compute adaptive filters to be used as an acoustic echo canceller (AEC). To achieve this architecture, we address two factors. (1) We propose a new data-selective adaptive filter along with subband decomposition least mean square (LMS) method to reduce the computational cost by minimizing the number of operations required to efficiently update the filter coefficients. The proposed method requires approximately 40% fewer updates when compared with conventional subband adaptive filters. As a consequence, the spike-based hardware architecture simulates the proposed adaptive filter at high processing speeds. (2) We propose a compact and high-precision neural multiplier since acoustic echo cancellers require a large number of high-precision multiplications to efficiently identify the echo path. The proposed neural multiplier expends up to 15 times fewer synapses when compared with existing approaches, which represents a significant improvement in terms of area. In addition, this improvement avoids routing problems by implementing large-scale synapse connectivity in advanced FPGAs. Herein, we carry out exhaustive testing by simulating several acoustic echo scenarios. The results demonstrate that the features of the model and the hardware implementation techniques potentially allow easy integration into portable devices for use in real-world acoustic echo cancellation scenarios.

FV 12. Non-invasive Suppression of Essential Tremor via Phase-Locked Disruption of its Temporal Coherence

Aberrant neural oscillations hallmark the pathophysiology of numerous neurological and psychiatric disorders. Here, we first report a method to accurately track the phase of neural oscillations in real-time by a Hilbert transform that avoids the characteristic Gibbs distortion at the end of the signal, aka endpoint-corrected Hilbert transform (ecHT). The ecHT method maintains the same computational complexity class of the original Hilbert transform allowing implementation in simple digital hardware. We then used the ecHT method to show that the aberrant neural oscillation that hallmarks treatment-resistant essential tremor (ET), the most common adult movement disorder, can be noninvasively supressed via transcranial electrical stimulation at a fixed phase lag over the cerebellar hemisphere ipsilateral to the tremor movement. This was tested in a quadruple-replication randomized way including stimulation at 6 fixed phases, sham and without phase-locking. In a total of 11 subjects, the suppression of ET activity was sustained after the end of the stimulation and was phenomenologically predicted, post-hoc, from the features of the tremor movement before the start of the stimulation. To test for reproducibility, 6 of the original participants werer stimulated exactly the same way three years after the original experiments: the observed, significant stimulation response remained, i.e. responders continued to respond and non-responders did not. Finally, we used a highly-comparative feature extraction (> 8000 features) with statistical learning and neurophysiological computational modelling to show that the suppression of ET activity can be mechanistically attributed to a disruption of the temporal coherence in the tremor movement that can be originated in a higher bursting entropy at the cortico-olivo-cerebello-thalamic circuitry. The suppression of aberrant neural oscillation via phase-locked driven disruption of temporal coherence may represent a powerful neuromodulatory strategy to treat neurological and psychiatric disorders.

Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing

The emerging brain-inspired computing paradigm known as hyperdimensional computing (HDC) has been proven to provide a lightweight learning framework for various cognitive tasks compared to the widely used deep learning-based approaches. Spatio-temporal (ST) signal processing, which encompasses biosignals such as electromyography (EMG) and electroencephalography (EEG), is one family of applications that could benefit from an HDC-based learning framework. At the core of HDC lie manipulations and comparisons of large bit patterns, which are inherently ill-suited to conventional computing platforms based on the von-Neumann architecture. In this work, we propose an architecture for ST signal processing within the HDC framework using predominantly in-memory compute arrays. In particular, we introduce a methodology for the in-memory hyperdimensional encoding of ST data to be used together with an in-memory associative search module. We show that the in-memory HDC encoder for ST signals offers at least 1.80x energy efficiency gains, 3.36x area gains, as well as 9.74x throughput gains compared with a dedicated digital hardware implementation. At the same time it achieves a peak classification accuracy within 0.04% of that of the baseline HDC framework.

Efficient Spike-Driven Learning With Dendritic Event-Based Processing.

A critical challenge in neuromorphic computing is to present computationally efficient algorithms of learning. When implementing gradient-based learning, error information must be routed through the network, such that each neuron knows its contribution to output, and thus how to adjust its weight. This is known as the credit assignment problem. Exactly implementing a solution like backpropagation involves weight sharing, which requires additional bandwidth and computations in a neuromorphic system. Instead, models of learning from neuroscience can provide inspiration for how to communicate error information efficiently, without weight sharing. Here we present a novel dendritic event-based processing (DEP) algorithm, using a two-compartment leaky integrate-and-fire neuron with partially segregated dendrites that effectively solves the credit assignment problem. In order to optimize the proposed algorithm, a dynamic fixed-point representation method and piecewise linear approximation approach are presented, while the synaptic events are binarized during learning. The presented optimization makes the proposed DEP algorithm very suitable for implementation in digital or mixed-signal neuromorphic hardware. The experimental results show that spiking representations can rapidly learn, achieving high performance by using the proposed DEP algorithm. We find the learning capability is affected by the degree of dendritic segregation, and the form of synaptic feedback connections. This study provides a bridge between the biological learning and neuromorphic learning, and is meaningful for the real-time applications in the field of artificial intelligence.

Digital Multiplier-Less Spiking Neural Network Architecture of Reinforcement Learning in a Context-Dependent Task

Neuromorphic engineers develop event-based spiking neural networks (SNNs) in hardware. These SNNs closer resemble the dynamics of biological neurons than conventional artificial neural networks and achieve higher efficiency thanks to the event-based, asynchronous nature of the processing. Learning in the hardware SNNs is a more challenging task, however. The conventional supervised learning methods cannot be directly applied to SNNs due to the non-differentiable event-based nature of their activation. For this reason, learning in SNNs is currently an active research topic. Reinforcement learning (RL) is a particularly promising learning method for neuromorphic implementation, especially in the field of autonomous agents' control. An SNN realization of a bio-inspired RL model is in the focus of this work. In particular, in this article, we propose a new digital multiplier-less hardware implementation of an SNN with RL capability. We show how the proposed network can learn stimulus-response associations in a context-dependent task. The task is inspired by biological experiments that study RL in animals. The architecture is described using the standard digital design flow and uses power- and space-efficient cores. The proposed hardware SNN model is compared both to data from animal experiments and to a computational model. We perform a comparison to the behavioral experiments using a robot, to show the learning capability in hardware in a closed sensory-motor loop.

An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

Posture coordination control of two-manipulator system using projection neural network

Nowadays, there are many models/algorithms designed for redundant manipulator control. Nevertheless, two-manipulator system is usually more efficient than single manipulator. However, there are a few studies investigated for the two-manipulator system control. Specifically, the posture control of the two-manipulator system is investigated in this paper. By analyzing the kinematics and considering the control task, two posture control schemes are proposed for two manipulators, respectively. Then, a posture coordination control scheme is proposed in the form of standard quadratic programming (QP). The projection neural network (PNN) model is further developed to handle the posture coordination control scheme. In addition, a one-iteration discrete PNN (DPNN) model is proposed for convenient numerical algorithm development and digital hardware implementation. Finally, sufficient experiments based on the two-manipulator system verify the effectiveness and superiority of the posture coordination control scheme, PNN model and one-iteration DPNN model.