IGBT Chip Research Articles

Impacts of the Pressure Distribution on Dynamic Avalanche in Single Press-Pack IGBT Chip

Impacts of the Pressure Distribution on Dynamic Avalanche in Single Press-Pack IGBT Chip

Power-cycling degradation monitoring of an IGBT module with VCE(sat) measurement in continuous operation of a chopper circuit

This paper presents a power-cycling degradation monitoring method of an IGBT module with a VCE(sat) sensing circuit and junction temperature prediction by a three-dimensional structure model. A chopper circuit was introduced to provide a continuous-current-conducting operation of the IGBT module. The VCE(sat) sensing circuit with a low-cost IoT platform “Leafony” was utilized to monitor the junction temperature of an IGBT chip, which transferred the measured signal as digital data, and thus obtained a higher noise immunity than an analog-based circuit. The junction temperature of IGBT chip in the power module was analyzed from the dissipated power of IGBT and the transient thermal impedance between the chips and the ambient. This analysis is effective not only to observe the degradation but also to estimate the thermal resistance. Comparing the temperature profile between experiment and prediction provides health condition of the IGBT model.Predicted thermal profiles agreed with measured ones with 10 % increase of thermal resistance, which was degraded by a power cycle tester. From these results, the proposed monitoring method is effective to detect the progress of power cycle degradation.

An Analytical Formula for the PETT Oscillation Over a Wide Voltage Range in NPT Planar IGBT Chips

An Analytical Formula for the PETT Oscillation Over a Wide Voltage Range in NPT Planar IGBT Chips

The design considerations of stray inductance for power modules with parallel-connected IGBT chips for a digital gate driver control

This paper aims to clarify the effect of asymmetric gate inductance Lg and emitter inductance Le inside power modules with two parallel-connected IGBTs on switching characteristics when a three-step digital gate driver is employed. Five types of IGBT modules with different Lg and Le were fabricated to implement double pulse tests by conventional gate driving and digital gate driving with three-step vectors. Under the conventional gate driving, the asymmetric Le introduced an imbalanced current during on-stage, and the asymmetric Lg introduced gate voltage spike Vg_spike and an imbalanced current during the turn-off interval. Large Lg introduced large Vg_spike. From the miller plateau in the turn-off, the current started to concentrate on the IGBT whose Lg is small. In the turn-on interval, the asymmetric Le made current share in two IGBTs become imbalanced, and the occurred large Vg_spike is positively corresponding to the difference of emitter current Ie flowing through two IGBTs. Under digital gate driving, it was found that the tradeoff between switching loss and voltage/current overshoots can be improved. And, the difference of Eoff between two IGBT chips, which results from asymmetric Le mainly, could be decreased more than that in conventional gate driving. In the turn-on interval, the large Vg_spike can be suppressed by a small vector number at the second step, and the difference of turn-on loss Eon could be also decreased. According to the above switching characteristics, the design considerations of power modules with parallel-connected IGBTs were proposed as the digital gate driver is applied.

Thermal simulation analysis of power module of combined converter for metro vehicle

In order to reduce the occupancy space and equipment cost of the on-board converter, a combined traction-auxiliary converter for subway vehicles is proposed in this paper. The power loss of the main traction converter module (MCM) and the auxiliary converter module (ACM) was calculated according to the speed and power variation of the vehicle running between five consecutive stations, and the flow rate of cooling air was calculated through the heat balance theory. The air volume of MCM and ACM and the plate temperature of the radiator are analysed by step method. Then, according to the instantaneous maximum temperature of the radiator obtained by simulation and the thermal parameters of the IGBT module, the junction temperature of the IGBT and diode chips is calculated by means of the junction temperature equivalent circuit. The results show that the plate temperature of the heat sink and junction temperature meet the design requirements. The design and thermal simulation method in this paper provide theoretical reference for the design of railway vehicle converters.

Lifetime prediction for press pack IGBT device by considering fretting wear failure

The reliability of the Press-Pack Insulated Gate Bipolar Transistor (PP-IGBT) device is important to guarantee the safety of modular multilevel converter (MMC). The fretting wear failure is the typical failure mode of long-time operation in the PP-IGBT device. However, the traditional fretting wear lifetime model of the PP-IGBT device only considers the fretting wear failure of the IGBT chip, which is difficult to accurately predict the reliability of the PP-IGBT device. The influence of fretting wear failure of all layers on the device's lifetime is ignored. This paper proposes a lifetime model of the PP-IGBT device by considering the fretting wear failure of all layers using the fault tree method. First, a finite element (FE) model of the PP-IGBT device is established by considering the multi-physics coupling, and the contact surface roughness change of each layer is obtained by power cycling simulation. Then, based on fretting wear failure and Basquin law, the lifetime of each layer is obtained, and a fault tree method is established to build the fretting wear lifetime model of the PP-IGBT device by considering the fretting wear failure of all layers. Finally, the power cycling experiment of the PP-IGBT device is established, and the experiment results are used to verify the effectiveness of the proposed lifetime model. The results show that the relative error between the proposed lifetime model and the experimental results is nearly 5 %.

Thermal cross-coupling effect analysis of multi-chips IGBT models considering chip size

With the increasing demand of high capacity of power converter, multi-chips IGBT modules are widely applicated. Taking thermal cross-coupling (TCC) effect among IGBT chips into account, the uneven temperature distribution should be investigated in-depth. Thus, in this paper, a steady-state finite-element model (FEM) of a conventionally utilized IGBT module in thermal domain is developed to analyse the effective heat transfer area from the chip to baseplate of the IGBT module. Moreover, the TCC coefficient is proposed in the light of effective transfer area to quantify the TCC effect. The influence of power loss distribution, heat dissipation ability and chip size on the TCC effect is discussed in the end. The results show larger power loss on neighbouring chips and smaller equivalent heat transfer coefficient (EHTC) cause larger TCC coefficient. Chip size has negligible influence on TCC effect at low EHTC, while larger chips size leads to severer TCC effect at high EHTC.

Investigation on peak reverse recovery current for junction temperature estimation of FWD

A good knowledge of junction temperature of high voltage power modules is of great significance for thermal management, lifetime prediction and condition monitoring. Power modules usually incorporate multi IGBT chips and FWD chips. Investigations about junction temperature estimation of IGBT are sufficient, while research about that of FWD is not sufficient with the problems of low sensitivity, invasive implement and unclear theoretical analysis. To address these issues, this paper investigates the peak reverse recovery current and presents a corresponding extraction circuit. Experiments are conducted to validate the established peak reverse recovery current model and the feasibility of the designed peak current detector. The results manifest the superiority of peak reverse recovery current on junction temperature estimation for its good linearity, high sensitivity and non-invasive.

Investigation on fatigue mechanism of solder layers in IGBT modules under high temperature gradients

With the increase in the power density of power semiconductor chips, the lateral temperature gradient over the chip surface becomes more pronounced. Temperature gradients play an important role in reliability evaluation of IGBTs and have attracted great attentions. In this paper, the influence of IGBT chip temperature gradients on the crack initiation site and propagation path of the solder layer is investigated by finite-element analysis (FEA). Results indicated that the temperature gradient could influence the mechanism of solder layer fatigue. With the temperature gradient increasing, the crack initiation site shifts from the edge of solder layer to the center. The crack propagation path also changed. The fatigue mechanism of the solder layer under high temperature gradients is investigated by FEA. The inelastic strain energy density per cycle (ΔW) is found to be unequal at crack initiation and crack propagation stages. Accordingly, a novel energy-based lifetime prediction model based on Darveaux's model for solder layer fatigue of IGBTs is proposed, which takes into account the variation of ΔW within these two stages and can better characterize the processes of crack initiation and propagation in the solder layer. Subsequently, two lifetimes of IGBT modules under accelerated aging tests from the existing publications are used to verify the effectiveness of the proposed model. Finally, the accelerated aging tests were carried out to support the theoretical analysis on the direction of crack propagation under high temperature gradients.

Measurement method of the IGBT chip temperature fluctuation based on electrothermal model derivation

The IGBT chip temperature is an important index affecting device reliability. Due to the existence of packaging, the temperature data of the IGBT chip is difficult to obtain directly. Because the large IGBT switching frequency, the temperature changes quickly. The chip junction temperature fluctuation is too difficult to measure. Based on the Cauer electrothermal coupling model, this paper deduces the calculation formula of the IGBT chip temperature fluctuation. Through the on-stage voltage, collector current, thermal resistance, thermal capacitance, on time and off time that can be directly monitored, the chip temperature fluctuation inside the package can be calculated. Then the accuracy of the calculation formula of temperature fluctuation is verified by experimental method, and the experimental results confirm the feasibility of this method. The chip temperature fluctuation monitored by this method is the premise for the lifetime prediction and reliability research of the IGBT, which plays a great role in the engineering field.

Research on Long-term Reliability of Silver Sintered Press-Pack IGBT Modules

Owing to the advantages of short-circuit failure mode, double-sided heat dissipation, and low thermal resistance, press-pack insulated gate bipolar transistors (PP-IGBTs) are widely used in high-power-density applications, such as high-voltage direct-current converters. As the core device of large-capacity power equipment, the reliability of a PP-IGBT is directly related to the security of the power system. In recent years, a silver-sintered package has been proposed to improve the electro-thermal performance of PP-IGBTs. However, the long-term reliability of this package has not been proven. In response to this problem, 3300-V/50-A silver-sintered PP-IGBT (SPP-IGBT) modules are used in long-reliability research. First, electro-thermal-stress finite-element models of PP-IGBTs and SPP-IGBTs were proposed and the accuracy of models verified by experiments. Through a simulation comparison, the results show that under the rated operating conditions, the on-voltage and maximum temperature of SPP-IGBTs dropped by 9.3% and 3.7%, respectively. In addition, the temperature and stress of each component were reduced, among which the surface stress of the IGBT chip emitter dropped by as much as 24.7%. Subsequently, a power-cycle test platform was established, and three PP-IGBTs and three SPP-IGBTs were tested. Finally, the experimental results were compared and analyzed, and the reasons for the sharp increase of on-voltage and metal melt were explored. The results show that the silver-sintered package improves the electrical-thermal performance and long-term reliability of the module. • Electro-thermal-stress finite-element models of PP-IGBT and SPP-IGBT were established separately. The accuracy of the model is verified by the temperature in the experiment, and the error is less than 5%. • Electrical, thermal, and stress indexes of PP-IGBTs and SPP-IGBTs were analyzed and compared. The on-voltage, maximum temperature and IGBT chip emitter surface stress of SPP-IGBTs dropped by 9.3%, 3.7% and 24.7%, respectively. • Three PP-IGBTs and three SPP-IGBTs were used for power-cycle test under same condition. The results also show that the SPP-IGBT has better electro-thermal performance, less surface wear of the chip emitter, and better long-term reliability.

A thermal network model for monitoring IGBT chip solder degradation based on feedback PI control

Under long-term thermal cycles, the solder layers in IGBT modules degrade inevitably, which affects their heat dissipation performance and eventually leads to the failure of IGBT modules. In order to monitor the degradation degree of the IGBT chip solder layers according to the junction temperature, a thermal network model for monitoring the IGBT chip solder degradation based on feedback PI control is proposed. Firstly, the finite element simulation model of the IGBT module is established and the degradation degrees of the chip solder layers are defined in the simulation model. Then the thermal network model is extracted according to the finite element simulation model and the thermal impedance functions are fitted from the different power loss and chip solder degradation degrees. Meanwhile, a control loop with PI controller is established to regulate the thermal impedances. Finally, the accuracy of the proposed thermal network based on feedback PI control for chip solder degradation monitoring and junction temperature calculation is verified under different chip solder degradation degrees.

IGBT finite element model for fibre bragg grating sensor installation analysis

An IGBT finite element model aimed at facilitating the assessment of Fibre Bragg Grating sensing based direct on-chip temperature monitoring is first presented in this paper. A commercial off-the-shelf IGBT module geometry is characterised, and a thermo-electrical finite element model is then established using its features. The model is subsequently employed to evaluate the local thermal disturbances that may be introduced by the installation of the optical based temperature sensor directly on the top surface of the IGBT chip. The effects of the sensor thermal interface material characteristics, e.g., thermal conductivity and size, in the local temperature environment are investigated.

Thermal Mitigation and Optimization Via Multitier Bond Wire Layout for IGBT Modules Considering Multicellular Electro-Thermal Effect

The stitch wire configuration is widely adopted for large-area IGBT chips. However, an inhomogeneous wire current density introduces uneven self-heating and nonuniform chip heating, which exacerbates the chip thermal stress. In this article, a multicellular electro-thermal model considering the stitch-bonding wires is derived to optimize the wire layout parameters. Furthermore, the current density alleviation of wire bonds is investigated to be the most sensitive and effective method to comprehensively mitigate the thermal nonequilibrium and local overheating. Consequently, an improved multitier layout is proposed to further achieve thermal stress suppression without any additional components and advanced materials. Finally, a triple-tier-bonded IGBT module with optimal design parameters is fabricated to validate the thermal mitigation performance. The prototype experimental results demonstrate that the modeling error is less than 3.0%. The multitier layout decreases the current density by 57.6%, hence, the maximum and average chip temperature are reduced by 21.8% and 12.4%, respectively.

A Fault Detection Method for Partial Chip Failure in Multichip IGBT Modules Based on Turn-Off Delay Time

Multichip IGBT module has been widely used in high-power converters. Detecting the status of the IGBT chip is a cost-effective approach to improving the reliability of power devices. This article proposes a novel method based on turn-off delay time to detect chip fault in multichip IGBT modules. First, the effect of chip failure on the turn-off process is analyzed, which causes a decrease in turn-off delay time. Then, a detection method of chip failure based on turn-off delay is proposed, which is validated by experimental results. Furthermore, the effects of chip failure on turn-off delay time in different working conditions are investigated through effective experimental results. The tested results show that the proposed method not only has high linearity and sensitivity to chip failure, but can also eliminate the influence of working environments on detection. The proposed method can be used to monitor the health status of multichip modules and is of great significance for enhancing operation reliability.

Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

In this work, the H3TRB performance of power modules with SiC MOSFET chips is investigated and compared to their silicon counterparts with similar electrical ratings. For this purpose, SiC MOSFETs and silicon IGBT chips are packaged in the same housing and with the same packaging technology and an H3TRB test is performed on both types of test devices. The results show that while both types exhibit an excellent H3TRB performance, the SiC MOSFETs had a significantly longer time to failure but also a wider failure distribution. Hence, the investigations presented in this paper confirm that properly designed SiC devices feature an equal or even better ruggedness against electro-chemical stress than standard silicon devics and are equally suitable for applications, which require operation in harsh environments.

Aging Monitoring Method of Bond Wires-Based on Phase-Frequency Characteristics of Differential Mode Conducted Interference Signal for IGBT Module

This paper presents an on-line monitoring method of IGBT module bond wires aging based on the phase-frequency characteristics (PFCs) of differential mode (DM) interference signal. Firstly, the collector current variation during IGBT chip switching is analyzed, and the relationship between the aging degree of bond wires and the PFCs of DM interference signal is studied; Secondly, a phase angle characteristic measurement system of DM interference signal is built and used to online monitor the aging of bond wires in IGBT module; Finally, taking the buck converter composed of IGBT module as the equipment under tested, the interference signal is extracted by the RF current probe and processed by the low-pass filter and signal amplifier, then the phase angle characteristics are measured by the oscilloscope board to realize the on-line monitoring of the bond wires aging of IGBT module. The experimental results show that compared with buck converter with healthy IGBT module, the phase angle of DM interference signal in Buck Converter with aging IGBT module is reduced. The proposed method does not need expensive equipment such as spectrum analyzer, and only needs to monitor the aging state of bond wires in IGBT module online through oscilloscope board. Besides, the research method in this paper provides an approximate linear monitoring method for bonding wire lift-off.

Electric Field Mitigation in High-Voltage High-Power IGBT Modules Using Nonlinear Conductivity Composites

Wide bandgap (WBG) semiconductor devices are developing rapidly due to their superior performance compared to traditional silicon-based devices. However, the packaging technology of traditional devices has limited the application of WBG semiconductor devices because of the challenges in electrical insulation. The complex environment of high blocking voltage, high frequency, and high temperature is the major reason for insulation failure of encapsulation structure. Therefore, in this article, an epoxy resin composite with nonlinear conductivity is proposed to be used as a coating to improve the electric field distribution of high-voltage high-power IGBT modules. First, an electrical field simulation model was built considering the thermal stress. It was found that the electric field in high temperature was improved compared with that in room temperature due to the temperature-dependent conductivity of silicone gel. Nevertheless, the risk of insulation failure still exists. After the application of nonlinear conductivity materials (NCMs) coating, the maximum electric field at the triple junctions and the ratio of electric field distortion in high field areas were significantly decreased. Further analysis showed that the optimization ratio of electric field increased with the increase of the blocking voltages or power losses in the IGBT chip. The results have demonstrated that the NCMs can reduce the maximum electric field in the IGBT encapsulation structure by 73% under the operating conditions of 120 W 10 kV. Partial discharge (PD) tests show that the partial discharge initial voltage (PDIV) of the substrates with NCM coating is increased by 33% compared with the normal encapsulation structure and the coating significantly inhibits the growth of electric trees. The presented results indicate that the NCMs have the potential to improve the insulation performance of high-voltage high-power IGBT modules.

Improved HV-H3TRB robustness of a 1700 V IGBT chip set in standard power modules

High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) is the standard to test power modules for humidity driven degradation. This test has contributed significantly to detect and fix weak points in device designs, especially of the junction termination. Thus, the latest junction termination designs offer unprecedented humidity robustness. This work reports on a comparative HV-H3TRB test on 1.7 kV IGBT modules with chips sets of two consecutive generations tested at two different test voltages each. The progress in the chip design and material composition provides more than an order of magnitude better performance in HV-H3TRB. Failure analyses have indicated vastly reduced degrees of aluminium corrosion in the junction termination area, leading to a slowed down failure mechanism.

Distributions of the electric field of stakpak IGBT submodule based on electricatic field simulation

The press pack-package for IGBT devices is more compatible with the serial application such as the converter valve. The Stakpak IGBT package, which is the preferred solution in HVDC apparatuses, shows the advantage in the pressure-balance of paralleled chips compared with the rigid press-pack package. It is necessary for insulation evaluation to investigate the characteristic of the electric field distribution in such a package, which may provide a reference for the design and modification of the package strategy. In this paper, we build the model of the Stakpak submodule with the practical structural details. The distribution of the electric field in the submodule is analyzed with the FEM method. As the first package with surface-covered silicone gel, the effect for covering thickness on electric field distribution is further simulated and analyzed. It is revealed that the field strength around the IGBT or FRD chips can be reduced with the silicone-gel covered. The reduction of the field strength is proportional to the thickness of the silicone gel.