Identical Processing Elements Research Articles

Algorithm for Computation of DCT and its Implementation using a Systolic Architecture

In this paper a new algorithm for computing N-point DCT, where N=4r, r>1 is presented. A new algorithm has been derived that can compute the 1D DCT and it is realized in systolic array that utilizes identical processing elements (PE’s). The proposed approach can be used to obtain other transform like Discrete Sine Transform (DST), Discrete Hartley Transform (DHT). The suggested algorithm requires reduced number of multiplications as compared to the other methods of computing DCT. This suggests structure meets the architectural challenge and it is simple, regular design and cost-effective for special-purpose system.

Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic Environment and Its FPGA Implementation

This paper presents a hardware-efficient algorithm and a very large scale integration architecture for finding a path for a mobile robot on the image of an environment captured by an overhead camera. The algorithm computes a distance map to identify the collision-free region for the robot and then constructs a breadth-first search tree to find a path in that region. The path obtained from a start point to the goal is the shortest path in terms of the number of steps. The time-critical part of the algorithm is mapped onto a 2-D cellular architecture that consists of a locally interconnected array of identical processing elements. In view of this local interconnection and regular structure, the architecture can be operated at high speed. An extension based on the assignment of multiple pixels to a processing element and processing them in pipeline is proposed to enhance the scalability of the design. The design has been implemented and evaluated on a Xilinx ML403 evaluation platform with Virtex-4 XC4VFX12 field-programmable gate array (FPGA). The maximum frequency of operation obtained is 375 MHz. This results in computing a collision-free path on images of size 100 × 100 in less than 27.6 μs. The FPGA design is capable of processing images at video rate for real-time path planning in a dynamic environment.

A versatile linear insertion sorter based on an FIFO scheme

A linear sorter based on a first-in first-out (FIFO) scheme is presented. It is capable of discarding the oldest stored datum and inserting the incoming datum while keeping the rest of the stored data sorted in a single clock cycle. This type of sorter can be used as a co-processor or as a module in specialized architectures that continuously require to process data for non-linear filters based on order statistics. This FIFO sorting process is described by four different parallel functions that exploit the natural hardware parallelism. The architecture is composed of identical processing elements; thus it can be easily adapted to any data lengths, according to the specific application needs. The use of compact identical processing elements results in a high performance yet small architecture. Some examples are presented in order to understand the functionality and initialization of the proposed sorter. The results of synthesizing the proposed architecture targeting a field programmable gate array (FPGA) are presented and compared against other reported hardware-based sorters. The scalability results for several sorted elements with different bits widths are also presented.

Configurable 3D‐integrated focal‐plane cellular sensor–processor array architecture

AbstractMixed‐signal cellular visual microprocessor architecture with digital processors is described. An Application Specific Integrated Circuit (ASIC) implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face‐to‐face‐type integration, and one or several cascaded array of mainly identical (single instruction multiple data, SIMD) processing elements. The individual array elements were derived from the same general Hardware Description Language (HDL) description and could be of different sizes, aspect ratio, and computing resources. Copyright © 2008 John Wiley & Sons, Ltd.

A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition

In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.

Large-capacity high-throughput low-cost pipelined CAM using pipelined CTAM

A novel approach toward realizing a large capacity high-throughput pipelined content addressable memory (CAM) or associative memory (AM) at low cost has been described. It employs only commercial random access memory (RAM) along with a simple binary search pipeline (BSPL). In order to search a (2/sup n/-1)-word search key field (SKF) storage RAM, the BSPL employs n identical and simple binary search processing elements, each having its local copy of the SKF storage RAM (SKFSR). The SKFSR stores, in an ordered manner, the SKFs of all the words in the CAM, whereas a data field storage RAM (DFSR) stores the unordered CAM data words. The n-times replicated SKFSR, along with the n-processor BSPL, functions as a simple n-stage pipelined content-to-address memory (CTAM). The CTAM, a new kind of memory that performs the inverse function of a RAM, serves as the first and the most important stage in the proposed 3-stage pipelined CAM architecture. In response to the stream of input query words (search keys) fed to the pipelined CAM, the pipelined CTAM first produces the corresponding stream of SKFSR addresses where the query words reside. These SKFSR addresses corresponding to the queries are next mapped back by the second stage, namely, the address mapping RAM, to their original addresses in the CAM, i.e., in the DFSR, which had been altered due to data ordering in the SKFSR. Now, the third stage of the pipelined CAM, namely, the DFSR, is read out at the mapped, i.e., the original CAM addresses, to obtain the desired stream of responses from the CAM. An augmented version of the pipelined CTAM has been designed to handle the presence of duplicate search keys in the CAM. A few illustrative examples of querying a simple database stored in the CAM have been included. The proposed pipelined CAM has a modular and highly scalable architecture. Its throughput rate, which is independent of the CAM size, is a little less than the RAM access rate and its latency is a little more than (n+2) times the RAM access time.

Efficient reconfigurable techniques for VLSI arrays with 6-port switches

This paper proposes an efficient techniques to reconfigure a two-dimensional degradable very large scale integration/wafer scale integration (VLSI/WSI) array under the row and column routing constraints, which has been shown to be NP-complete. The proposed VLSI/WSI array consists of identical processing elements such as processors or memory cells embedded in a 6-port switch lattice in the form of a rectangular grid. It has been shown that the proposed VLSI structure with 6-port switches eliminates the need to incorporate internal bypass within processing elements and leads to notable increase in the harvest when compared with the one using 4-port switches. A new greedy rerouting algorithm and compensation approaches are also proposed to maximize harvest through reconfiguration. Experimental results show that the proposed VLSI array with 6-port switches consistently outperforms the most efficient alternative proposed in literature, toward maximizing the harvest in the presence of fault processing elements.

Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

Abstract. One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper. The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementations.

A pipelined array architecture for Euclidean distance transformation and its FPGA implementation

The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O( n) hardware algorithm for computing EDT of an n× n image is presented. A pipelined 2D array architecture for harware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Such an array architecture is easily scalable to handle images of different sizes and is suitable for implementation on reconfigurable devices like FPGAs. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512×512 per second which is much higher than the video rate of 30 frames per second.

A reconfigurable architecture for autonomous visual-navigation

This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hard-ware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size and weight restrictions. Two different vision algorithms have been implemented in the reconfigurable pipeline, for which some experimental results are shown.

A parallel systolic array ASIC for real-time execution of the Hough transform

Many pattern recognition problems can be solved by mapping the input data into an n-dimensional feature space in which a vector indicates a set of attributes. One powerful pattern recognition method is the Hough transform. In reducing the n-dimensional feature space to two dimensions, the coordinate transform can be executed by a systolic array consisting of time-delay processing elements and adders. The application-specific integrated circuit (ASIC) implementation of the Hough transform as a systolic array for real-time recognition of curved tracks in multiwire drift chambers is presented. The array can handle 32 parallel input data streams. It mainly consists of 512 identical programmable processing elements. Sixteen histogram pixels in the feature space are produced in parallel per clock cycle. The ASIC is implemented in 0.6 /spl mu/m CMOS, two-metal layer technology (CUB) from Austria Micro Systems (AMS) and operates with a clock frequency of 100 MHz. The interconnectivity pattern of the processing elements required to initialize the chip according to the pattern recognition task is computed on the host computer using the Hough-transform equations. This pattern is then downloaded to the chip via the data input lines. The Hough-transform ASIC is suitable for a wide range of pattern recognition applications. The integrated circuit is a powerful building block for systems requiring real-time execution of the Hough transform.

AMAP for typecasting

We introduce a design of an associative memory array processor (AMAP) to be used in character recognition. The design example is based upon the bit-parallel organization. The AMAP consists of identical processing elements that can store information about a specific position into the pattern and also contain some logic gates to carry out logical operations. No effort has been made to perform either processing or feature extraction of any kind.

An empirical study of dynamic scheduling on rings of processors

We empirically analyze and compare two low-overhead, deterministic policies for scheduling dynamically evolving tree-structured computations on rings of identical processing elements (PEs). Our computations have each task either halt or spawn two independent children and then halt; they abstract, for instance, computations generated by multigrid methods. Our simpler policy, koso, has each PE keep one child of a spawning task and pass the other to its clockwise neighbor in the ring; our more sophisticated policy, koso *, operates similarly, but allows child-passing only from a more heavily loaded PE to a more lightly loaded one. Both policies execute waiting tasks in increasing order of their depths in the evolving task-tree. Our study focuses on two conjectures: (a) Both policies yield good parallel speedup on large classes of the computations we study. (b) Policy koso * outperforms policy koso in many important situations. We verify these conjectures via a suite of experiments, supplemented by supporting mathematical analyses. We view our methodology of experimental design and analysis as a major component of our study’s contribution, which will prove useful in other such studies.

Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory.

High-speed collision detection plays an essential role in a collision warning system for highly-safe vehicles. In collision detection, high computational power is required to perform matching operation between discrete points of obstacles and a vehicle. This paper presents design of a collision detection VLSI processor using content-addressable memories (CAMs) for parallel matching operation. The VLSI processor consists of identical CAMs and processing elements (PEs) for coordinate transformation. If they are fully utilized and the fixed computation time of the VLSI processor is given as a constraint, area minimization of the VLSI processor is attributed to minimization of the area-time product of the CAM and the PE. To reduce the area-time product of the CAM, a multiport CAM (MCAM) is proposed. Each word stored in the MCAM is shared between multiple matching units so that matching operation can be performed in parallel with multiple input words without increasing memory capacity. It is shown that the area of the VLSI processor using 4-port CAMs can be reduced to 43% in comparison with the area of the VLSI processor without them under a time constraint.

Parallel image understanding algorithms on MIMD multicomputers

The heterogeneous nature of data types and computational structures involved in Computer Vision algorithms make the design and implementation of massively parallel image processing systems a not yet fully solved problem. It is common belief that in the next future MIMD architectures with their high degree of flexibility will play a very important role in this research area, by using a limited number of identical but powerful processing elements. The aim of this paper is to show how a selected list of algorithms in which a unique Image Understanding process can be decomposed could map onto a distributed-memory MIMD architecture. The operative modalities we adopt are the SPMD modality for the low level processing and the MIMD modality for the intermediate and high levels of processing. Either efficient parallel formulations of the algorithms with respect to the interconnection topology of processors and their optimized implementations on a target transputer-based architecture are reported.

Catastrophic faults in reconfigurable systolic linear arrays

In regular architectures of identical processing elements, a widely used technique to improve the reconfigurability of the system consists of providing redundant processing elements and connections together with mechanisms of reconfiguration. In this paper we consider linear arrays of processing elements, with unidirectional bypass links of length g. We study those sets of faulty processing elements, called catastrophic, which prevent the reconfiguration. We show that the number of catastrophic faults of g elements is equal to the ( g − 1)th Catalan number. We also provide algorithms to rank and unrank all catastrophic sets of g faults. Finally, we describe a linear-time algorithm that generates all such sets of faults. Our results are useful to provide reliability estimates of linear arrays and for testing the behavior of reconfiguration strategies in the presence of catastrophic faults.

Fuzzy cellular systems for a new computational paradigm

In this paper a new approach for processing arrays of data is proposed. It is based on fuzzy logic and the concepts of cellular computation. Arrays of simple, identical processing elements (called fuzzy cells) are defined by using fuzzy rules. Moreover, each fuzzy cell interacts with its local neighbors. The overall behavior of these locally interacting fuzzy systems is used to process arrays of data. Some examples of practical applications are proposed. Among these, the new approach is applied to image-processing problems, and to the simulation of heat diffusion phenomena.

Collective Behaviour of Cellular Fuzzy Systems for a New Paradigm of Computation

In this paper a new approach for processing arrays of data is proposed. It is based on Fuzzy Logic and the concepts of cellular computation. Arrays of simple, identical processing elements (called fuzzy cells) are defined by using Fuzzy Rules. Moreover, each fuzzy cell interacts with its local neighbours. The overall behaviour of these locally interacting fuzzy systems is used to process arrays of data. Some examples of practical applications are proposed. Among these, the new approach is applied to image processing problems and to the simulation of heat diffusion phenomena. This research represents the final results of the scientific activity developed by our group in the field of Fuzzy Logic.

Configurable digit-serial convolver of type F

The semi-systolic architecture, known as design F, is used as a basic structure for synthesis of a digit-serial fault-tolerant convolver. The proposed convolver has the structure of a tree with connected leaves. Leaves are multiplier cells, while nodes are adder cells. The Diogenes approach is a well-known reconfiguration technique for structures with identical processing elements (PEs), and is accepted for reconfiguration of the proposed convolver. In order to apply the Diogenes approach to the proposed structure, we propose the modification of this approach which relates to involving PEs of two types. The proposed modification provides configuration of the convolver structure in a number of taps in the presence of faults, so the fault tolerance is achieved through dynamic reconfiguration.

Yield enhancement of a 16.6 cm/sup 2/ monolithic large-area integrated multiprocessor system using laser reconfiguration

A 16.6 cm/sup 2/ monolithic large-area integrated multiprocessor system comprising nine identical programmable video signal processing elements was reconfigured by excimer laser-formed connections and discontinuities of conductor lines in a redundant bus system. The total yield enhancement of processors using laser reconfiguration amounts to 13.3%. On the prototypes, up to six processors per chip were functional at 66 MHz, providing a peak arithmetic performance of 6 GOPS per multiprocessor system. The power supply to defective processors with a high stand-by power consumption was terminated by laser, leading to a halving of power consumption. Furthermore, for the improvement of the laser process, vertical links between two metallization levels were formed on two chips with different standard CMOS layer sequences on special test structures. For the yield statistics of the formed vertical links, a contact resistance R/sub K/ larger than 3 /spl Omega/ was treated as a failure. With the laser processing of vertical links with an area of 14/spl times/14 /spl mu/m/sup 2/, a yield of 100% has been achieved. Beyond those, conventional accelerated life time tests were performed to examine the reliability of laser-formed vertical links. In microelectronic systems, a failure rate of 10 FIT/layer in 11.4 years corresponding to 0.1% failures is accepted. An extrapolation of Black's equation to operating conditions (100/spl deg/C, 2.5 mA) resulted in a failure rate of 0.1% in a time of 39 years.