Ideal Transistors Research Articles

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors.

Boltzmann distribution thermal tails of carriers restrain the subthreshold swing (SS) of field-effect transistors (FETs) to be lower than 60 mV/decade at room temperature, which restrains the reduction of operate-voltage and power consumption of transistors. The negative-capacitance FET (NC FET) is expected to break through this physical limit and obtain a steep SS by amplifying the gate voltage through the negative capacitance effect of the ferroelectric thin film, providing a new way to further reduce the power consumption of the transistor at the end of Moore's law. Here, we show a MoS2 NC FET with a CuInP2S6 ferroelectric, exhibiting a large on/off ratio of 108, a steep SS as low as 6 mV/decade, and a wide sub-60 mV/decade drain current range of more than 4 orders of magnitude while sacrificially inducing a huge hysteresis larger than 500 mV. Furthermore, we found that by inserting the h-phase boron nitride (h-BN) layer with suitable thickness, the dielectric capacitance matches the ferroelectric negative capacitance better, and thus the hysteresis on the transfer curve is reduced, and the ideal switching-behavior transistors with SS as low as 62 mV/decade and only 5 mV negligible hysteresis were obtained. Our work demonstrates that under the capacitance-matching condition, the hysteresis-free negative-capacitance transistors do not act as the predicted steep-slope transistors, but their voltage-saving still occurs instead as a type of effective transconductance booster with more than 20 times transconductance amplification.

Approaching Ohmic Contacts for Ideal Monolayer MoS2 Transistors Through Sulfur-Vacancy Engineering.

Field-effect transistors (FETs) made of monolayer 2D semiconductors (e.g., MoS2 ) are among the basis of the future modern wafer chip industry. However, unusually high contact resistances at the metal-semiconductor interfaces have seriously limited the improvement of monolayer 2D semiconductor FETs so far. Here, a high-scale processable strategy is reported to achieve ohmic contact between the metal and monolayer MoS2 with a large number of sulfur vacancies (SVs) by using simple sulfur-vacancy engineering. Due to the successful doping of the contact regions by introducing SVs, the contact resistance of monolayer MoS2 FET is as low as 1.7 kΩ·µm. This low contact resistance enables high-performance MoS2 FETs with ultrahigh carrier mobility of 153 cm2 V-1 s-1 , a large on/off ratio of 4 × 109 , and high saturation current of 342 µA µm-1 . With the comprehensive investigation of different SV concentrations by adjusting the plasma duration, it is also demonstrated that the SV-increased electron doping, with its resulting reduced Schottky barrier, is the dominant factor driving enhanced electrical performance. The work provides a simple method to promote the development of industrialized atomically thin integrated circuits.

Achieving ideal transistor characteristics in conjugated polymer semiconductors.

Organic thin-film transistors (OTFTs) with ideal behavior are highly desired, because nonideal devices may overestimate the intrinsic property and yield inferior performance in applications. In reality, most polymer OTFTs reported in the literature do not exhibit ideal characteristics. Supported by a structure-property relationship study of several low-disorder conjugated polymers, here, we present an empirical selection rule for polymer candidates for textbook-like OTFTs with high reliability factors (100% for ideal transistors). The successful candidates should have low energetic disorder along their backbones and form thin films with spatially uniform energetic landscapes. We demonstrate that these requirements are satisfied in the semicrystalline polymer PffBT4T-2DT, which exhibits a reliability factor (~100%) that is exceptionally high for polymer devices, rendering it an ideal candidate for OTFT applications. Our findings broaden the selection of polymer semiconductors with textbook-like OTFT characteristics and would shed light upon the molecular design criteria for next-generation polymer semiconductors.

Ambipolar operation of progressively designed symmetric bidirectional transistors fabricated using single-channel vertical transistor and electrochemically prepared copper oxide.

In this study, a symmetric bidirectional transistors (SBT) is proposed. The device simultaneously implements the "strong-inversion" and "accumulation" mechanisms of a metal-oxide semiconductor field-effect transistor and TFT, respectively, in different bias directions in a single-channel vertical transistor (V-Tr). This ideal SBT device is designed and fabricated by selecting appropriate materials exhibiting a narrow bandgap and intrinsic characteristics of Sb-doped p-type Cu2O, using a V-Tr to optimize the device structure for high-field-induced short-channel and ambipolar operation, and implementing facile electrochemical deposition for channel and plasma channel treatments. To adopt artificial conductivity control for producing the transporting path of minority electron carriers, the patterned-channel-layer sidewall is locally treated using oxygen plasma, thereby suppressing the minority-carrier self-compensation. The SBT device exhibits an excellent on-current (i.e., symmetric accumulation and strong inversion modes in the p- and n-type channel regions, respectively) and excellent midregion off-current, similar to those of ideal ambipolar transistors. Moreover, owing to multilevel signals and excellent inverter behaviors, the SBT device is suitable for application in complementary-metal-oxide-semiconductors and logic memories.

Graphene film transistors based on asymmetric gate design combining with chemical doping

Graphene is considered a promising transistor component for future integrated circuits. Due to high operating speed and low power consumption, high on/off ratio and low off state current are ideal transistors. However, due to the inherent ambipolarity of graphene, a significant ambipolarity behavior with a fairly high off state current is usually observed in graphene transistors. In this work, an asymmetric gate design combined with a chemically doped method to suppress the ambipolarity of graphene transistors was reported. Thus, the off-state current is effectively reduced and the on-state current is increased. The on/off ratio is increased by nearly two orders of magnitude. Compare to the normal gate structure device, better threshold swing and smaller threshold voltage are obtained.

Analysis and design of output matching network for Doherty power amplifiers

In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power amplifier is designed and measured. The operating frequency is from 1.75 to 1.95 GHz with the saturated output power of 43.5 dBm to 44.2 dBm. The measured peak drain efficiency is 58.8% to 71.7% and the 6 dB back-off drain efficiency is 50.9% to 61.4%.

Selective etching in graphene–MoS2 heterostructures for fabricating graphene-contacted MoS2 transistors

Semiconducting molybdenum disulfide (MoS2) has drawn a lot of attention for its exceptional electronic and optoelectronic properties. Despite the potential advantages, the large contact resistance at the metal–MoS2 interfaces has been one of the biggest obstacles for the realization of ideal MoS2 transistors. One solution to improve the metal–MoS2 interfaces is to use the graphene electrodes. Here, we provide a selective etching method for fabricating graphene-contacted MoS2 transistors. It has been proved that the graphene could be totally etched with Ar+ plasma treatment, and the multilayer MoS2 flake can also be reduced layer by layer with Ar+ plasma treatment. By etching graphene selectively in graphene–MoS2 heterostructures, one can obtain graphene-contacted MoS2 transistors successfully. The transistor reported in this paper shows an on–off ratio about 106 and a carrier mobility about 42 cm2 V−1 s−1. This selective etching method would be beneficial for some other graphene-contacted electronic devices.

Understanding, Optimizing, and Utilizing Nonideal Transistors Based on Organic or Organic Hybrid Semiconductors

AbstractMany advanced materials have been developed for organic field‐effect transistors (OFETs) or thin‐film transistors (TFTs) based on organic and organic hybrid materials. However, although many new OFETs exhibit superior characteristic parameters (such as high mobility), most of them show nonideal performances that have strongly limited progress in the design of molecules, the understanding of transport mechanisms, and the circuit applications of OFETs. In this review, the device physics of ideal and nonideal OFETs is discussed first to understand the factors that limit effective mobility in semiconducting channels, distort the potential distribution, or reduce the drift electric field. Then, recent advances in optimizing the material combinations, device structures, and fabrications of OFETs toward ideal transistors are discussed. Based on the good control of materials and interfaces, some new and novel concepts to utilize the nonideal properties of OFETs to build low‐power circuits and integrated sensors are also discussed.

Transferred via contacts as a platform for ideal two-dimensional transistors

Two-dimensional semiconductors have a number of valuable properties that could be used to create novel electronic devices. However, creating 2D devices with good contacts and stable performance has proved challenging. Here we show that transferred via contacts, made from metal embedded in insulating hexagonal boron nitride and dry transferred onto 2D semiconductors, can be used to create high-quality 2D transistors. The approach prevents damage induced by direct metallization and allows full glovebox processing, providing a clean, stable and damage-free platform for 2D device fabrication. Using the approach, we create field-effect transistors (FETs) from bilayer p-type tungsten diselenide (WSe2) that exhibit high hole mobility and low contact resistance. The fabricated devices also exhibit high current and stability for over two months of measurements. Furthermore, the low contact resistance and clean channel allow us to create a nearly ideal top-gated p-FET with a subthreshold swing of 64 mV per decade at 290 K. Bilayer WSe2 field-effect transistors with near ideal device characteristics can be created using transferred via contacts made from metal-embedded hexagonal boron nitride.

Fabrication of Two-Dimensional Crystalline Organic Films by Tilted Spin Coating for High-Performance Organic Field-Effect Transistors.

We developed a facile method for fabricating large-area, two-dimensional (2D), organic, highly crystalline films and extended it to organic thin-film transistor arrays. Tilted spinning provided oriented flow at the three-phase contact line, and a 2D crystalline film that consisted of layer-by-layer stacked 2,7-diocty[1]benzothieno[3,2- b]benzothiophene (C8-BTBT) was obtained facilely for organic thin-film transistors (OTFTs). The extracted field-effect mobility is 4.6 cm2 V-1 s-1, but with nonideal features. By applying this method to microdroplet arrays, an oriented crystal was fabricated, and the channel region for OTFTs was covered by adjusting the spinning speed. By tuning the tilt angle (θ) of the revolving substrate, we fabricated high-performance OTFT arrays with average and maximum mobilities of 7.5 and 10.1 cm2 V-1 s-1, respectively, which exhibited high reliability factors of over 90% and were close to that of ideal transistors. These results suggest that high-quality crystalline films can be obtained via a facile tilted-spinning method.

Study of the side gate junctionless transistor in accumulation region

PurposeThe purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition.Design/methodology/approachThe device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation.FindingsWe have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime.Originality/valueThe proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

(Invited) Flexible GHz Frequency and Low-Power Nanoelectronics Based on 2D Nanomaterials

2014 is the 10th year anniversary of the groundbreaking work on graphene by several pioneering workers. Since then, the field has expanded exponentially and now includes two-dimensional (2D) atomic sheets beyond graphene such as hexagonal boron nitride (hBN), transition metal dichalcogenides (TMDs), and group IV elemental monolayers (e.g. silicene, germanene). While there are many opportunities for these 2D crystals to enable transformational impact, it is widely understood that their greatest prospects are for flexible nanoelectronics where their combined synergistic properties are unmatched by conventional organic or inorganic materials. The 2D atomic sheets have emerged as near ideal nanomaterials to overcome the long running challenge of achieving Si CMOS like performance on soft substrates at scales that can be suitable for large integration. For instance, the high mobility and velocity accessible in monolayer graphene affords GHz analog transistor devices while the large bandgap of graphene’s semiconducting analogues (MoS2 and similar dichalcogenides) naturally lead to near ideal digital transistors with high on/off current ratio and low subthreshold slope while sustaining mobilities much larger than organic semiconductors or amourphous bulk semiconductors. Together, these physically similar atomic layers with vastly different electronic properties can serve as the electronic platform for low-power digital, high-speed mixed-signal, and high-frequency analog transistor building blocks for flexible nanoelectronic systems.In this work, we present the latest findings on the high frequency properties of graphene with record frequencies in the microwave regime. These high frequencies are suitable for realizing GHz wireless analog circuits on soft substrates. The current frequencies are limited by the poor thermal conductivity and reliability of the plastic substrates. In addition, we report on the coupled device mechanics and device physics of 2D semiconducting sheets. The device mechanics on plastic substrate as a function of tensile strain reveal that dielectric cracking is responsible for off-current degradation while buckling is largely responsible for on-current degradation. The buckling scales with the thickness of the dichalcogenide semiconductor and can be mitigated by reducing the driving force for delamination. Optimized dielectric patterning for strain relaxation was found to improve device reliability at low bending radius. Our results collectively indicate that graphene is the most suitable material for flexible radio-frequency transistors while TMDs are ideal for low-power flexible transistors.

Metallic, Linear, and Saturated Output Characteristics of Oxide Nanowire Transistors

Ideal nanowire transistors exhibit saturation and square-law behavior in their output characteristics. The current saturation above the pinch-off voltage is an essential characteristic for transistors to be applied to a display device that is required to produce a consistent level of brightness even during long operation periods. However, fabricated oxide nanowire transistors exhibit three representative output characteristics-metallic, linearly increasing, and saturated curves-within a measurable range. In this study, through experiments and simulations using In 2O3 nanowire transistors, we show that fewer oxygen vacancies in the nanowire produce output characteristics more similar to ideal MOSFET characteristics. This result indicates that differences in electrical characteristics of the nanowire transistor are derived from the difference in the number of oxygen vacancies in the oxide nanowire.

A Method of Transformation from Symbolic Transfer Function to Active-<emphasis>RC</emphasis> Circuit by Admittance Matrix Expansion

Active-RC circuits containing 2-terminal linear passive elements and ideal transistors or operational amplifiers are derived from symbolic voltage or current transfer functions by admittance matrix transformations without any prior assumption concerning circuit architecture or topology. Since the method is a reversal of symbolic circuit analysis by Gaussian elimination applied to a circuit nodal admittance matrix, it can generate all circuits using the specified elements that possess a given symbolic transfer function. The method is useful for synthesis of low-order circuits, such as those used for cascade implementation, for deriving alternative circuits with the same transfer function as an existing circuit or for realizing unusual transfer functions, as may arise, for example, where a transfer function is required that contains specific tuning parameters

Systematic Synthesis of Active-RC Circuit Building-Blocks

In this paper, we show how some basic building blocks for active-RC circuit design, such as amplifiers, impedance converters and simulated inductance circuits, may be synthesised in a systematic way by expansion of their port admittance matrices. The circuit topology emerges from the synthesis procedure, allowing all possible implementations to be identified and explored. Nullors representing ideal op-amps and transistors are represented within the nodal admittance matrix of a synthesised circuit by linked infinity parameters. In nodal admittance matrices describing ideal circuits synthesised, the replacement of linked infinity parameters by finite parameters provides a seamless transition to non-ideal analysis and practical circuit design.

Exponential state space filters: a generic current mode-design strategy

A new method of analog filter design is proposed where nonlinear active components are a natural part of a filter realizing an overall linear transfer function. This approach to design is articulated in the generation of the class of so-called Exponential State Space (ESS) filters. An outgrowth of log ESS filters are created via a mapping on the state space of a linear filter. Specifically, the state variables are equal to simple functions of exponentials or node voltages. The use of exponential, hyperbolic tangent, and hyperbolic sine mappings is shown to produce realizable nodal equations that result in log, tanh and filters, respectively. Aspects of interpretation and realization of the transformed state equations are discussed. It is shown that sinh filters are class AB filters, which is an intriguing extension of a concept introduced by Seevinck (1990). The different filter types are compared to an analogous standard transconductance-C filter via simulation of a band-pass filter with a Q of 5. All filters demonstrate tunability over a 100 to 1 range with excellent frequency response stability and accuracy over the tuning range, which extends to 5 MHz. These results and IMD and noise performance are given using both ideal transistors and transistors whose cutoff frequency equals approximately 300 MHz.

Comparison of bipolar NPN polysilicon emitter interface formation at three different manufacturing sites

The formation of polysilicon emitters at three different fabrication facilities is examined with a view to understanding critical manufacturing steps. This work demonstrates the effects of different interface procedures on the formation of the native oxide interfaces and how the transistor electrical properties are affected. The sensitivity of the interface break up, by rapid thermal annealing, to the initial interface thickness is quantified. Polysilicon emitter transistors from the three processes are compared and it is found that the devices with recrystallized polysilicon behave as ideal single crystal transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the temperature dependence of polysilicon emitter transistors

This paper investigates the s f temperature behaviour of polysilicon emitter transistors with a view to understanding the device physics. Realigned polysilicon emitters are shown to behave as ideal single crystal transistors. Transistors with true polysilicon emitters exhibit a reduced temperature sensitivity of s f . This is thought to result from a potential barrier at the interface. This potential barrier is dependent on the polysilicon doping level.

Note on transistor-fed active-array antennas

The feed requirements for an active radiating array in which each element is independently excited by a transistor are shown to be less dependent on the elemental mutual coupling effects than in the corresponding passive case. Using a simple transistor equivalent network, it is predicted that as the limit of ideal transistors is approached the input impedance of the active array should exhibit less variation with frequency.

Transistor-resistor realizations of negative resistance circuits employing two ideal transistors†

A number of methods for realizing different active circuit elements have been provided by diffferent authors. Each new circuit or configuration was the result of the contributing authors's experience and insight. It would be very convenient if all such configurations could be derived as a special case from a general theory, instead of depending on the customary cut-and-try procedure. In this paper the outcome of such a general theory is given ; i.e. all of the possible negative resistance configurations which can be obtained by employing two ideal transistors along with some special kinds of resistance networks will be given.