Horizontal Constraint Graph Research Articles

Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation

A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. We call a floorplan room-to-room when adjacencies between rooms are considered. Fujimaki and Takahashi showed that any room-to-room floorplan can be represented as a permutation. In this paper, we give an O(n)-time algorithm that constructs the vertical and the horizontal constraint graphs of a floorplan for a given permutation under this representation.

The quarter-state-sequence floorplan representation

A floorplan of a bounding box is its dissection into rectangles (rooms) by horizontal and vertical segments. This paper proposes a string data structure called the Quarter-state sequence (or Q sequence) to represent the floorplan. The Q sequence is a concatenation of the states of rooms along the Abe order and is related to the VH graph, which is the union of the vertical-constraint and horizontal-constraint graphs. It is proved that any floorplan of n rooms is uniquely encoded by a Q sequence and any Q sequence is uniquely decoded to a floorplan, both in O(n) time. An exact formula for counting distinct floorplans is given and compared with existing bounds. A linear time transformation of one Q sequence to another is defined. An n-room packing algorithm based on simulated annealing was implemented and found to compare favorably with existing packing algorithms.

A Faster One-Dimensional Topological Compaction Algorithm with Jog Insertion

We consider the problem of one-dimensional topological compaction with jog insertions. By combining both geometric and graph-theoretic approaches we present a faster and simpler algorithm to improve over previous results. The compaction algorithm takes as input a sketch consisting of a set F of features and a set W of wires, and minimizes the horizontal width of the sketch while maintaining its routability. The algorithm consists of the following steps: constructing a horizontal constraint graph, computing all possible jog positions, computing the critical path, relocating the features, and reconstructing a new sketch homotopic to the input sketch, which is suitable for detailed routing. The algorithm runs in O(|F| ⋅ |W|) worst-case time and space, which is asymptotically optimal in the worst case. Experimental results are also presented.

Efficient height reduction over-the-cell channel router

The authors present a new algorithm for both two-layer and three-layer over-the-cell channel routing in the standard cell VLSI design. The approach exploits vacant terminals on the channel boundary effectively. It considers the following factors simultaneously to select net segments for routing over the cells: density distribution in the channel, the longest path in the vertical constraint graph, elimination of cycles in the vertical constraint graph and reduction in maximum cliques in the horizontal constraint graph. With respect to the PRIMARY 1 benchmark examples, the router achieved a 41.3% improvement over the Greedy channel router (one without using over-the-cell area) for a two-layer routing model and a 61.0% improvement for a three-layer routing model. This outperforms all previous algorithms.

Some sequential graph colouring algorithms for restricted channel routeing

Channel routeing, as originally envisaged, can be visualized as constrained colouring of a graph, called a horizontal constraint graph. We describe how this can be effective in real-life channel routeing problems with different kinds of simple heuristics. The problem, without heuristics, is actually combinatorially explosive in nature. Compared with certain benchmark problems, the algorithms give encouraging results. The redeeming features of the algorithms presented here are simplicity, with tolerable results at a faster speed and a classical approach reopened.

A topological sorting algorithm for three‐layer channel routing

Abstract Three‐layer channel routing is an important problem in VLSI layout. In this paper, we present a topological sorting algorithm to determine the topological order on nets depending on the operations of the vertical constraint graph (VCG) and the horizontal constraint graph (HCG). According to the order, the base router can finish the connections of all nets. In the algorithm, the HVH mode is assumed, and some examples including Deutsch's difficult example are used as test problems.

A graph-based heuristic channel router

This paper presents the formulation of a graph-based heuristic channel routing algorithm and its implementation. The algorithm uses a vertical constraint digraph to select nets that can be routed on a horizontal track, and uses a horizontal constraint graph and heuristics to decide which of those nets should be routed to obtain an optimal solution. The graph-based model has been selected due to its simplicity and its accurate representation of the routing process. The channel router has been implemented in C on an Apollo DN660 workstation. The router has produced minimum channel height solutions for nine of the twelve examples selected from published literature, using a single set of parameters. By adjusting the parameters slightly, minimum solutions were generated for all twelve examples. In particular, Deutsch's Example was routed in minimum non-dogleg channel height in less than 1.3 seconds on the Apollo workstation.