Hole Inversion Layer Research Articles

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Novel Backside Structure for Reverse Conducting Insulated-Gate Bipolar Transistor With Two Different Collector Trench

A novel reverse-conducting insulated gate bipolar transistor (RC-IGBT) with two different collector trench (DCT) is proposed. One of the collector trenches is filled with heavily doped N-type polysilicon (N-poly) and the other is filled with heavily doped N- and P-poly. An electron accumulation layer is formed along the sidewall of trench owing to built-in potential difference between the N-poly and the N-drift region. The electron accumulation layer and collector trenches block the electric field, which behaves just like the N-buffer layer of the conventional RC-IGBT (Con. RC-IGBT). Similarly, due to potential difference between the P-poly and N-drift region, a high-density hole inversion layer is formed to narrow the electron current path as a high resistance. The DCT RC-IGBT achieves snapback-free in a small cell pitch without additional control. Moreover, the DCT RC-IGBT shows better tradeoff between turn-off loss and ON-state voltage drop than that of con. RC-IGBT. For the same forward voltage drop, the turn-off loss is reduced by 26%.

Influence of a hole inversion layer at the In2O3 / BiVO4 interface on the high-efficiency photocatalytic performance

Recently, Due to the importance of photocatalysts in different applications, numerous strategies have been studied to improve its performance. Herein, we refuge to create a built-in electric field by building the hole inversion layer at the interface layer between In2O3/BiVO4 composite as n-n heterojunction semiconductor. The results show an enhancement in photocatalytic activity due to the impact of spontaneous internal polarization. Photoelectrochemical properties confirmed a decrease in the quick recombination of photo-induced electrons (e−) and holes (h+). The bode curve also shows an enhancement in the charges transfer in the bulk of material and at interface layers. Mott-Schottky plots revealed an inversion layer created at the In2O3 ǀǀ BiVO4 interface that drives electrons and holes to transfer along with the opposite directions. This inversion layer converts the behavior of the composite to work as a virtual p-n heterojunction. These results enhance the composite's photo-activity to duplicate the degradation of Methylene blue (MB) dye.

A 3-D TCAD Framework for NBTI—Part I: Implementation Details and FinFET Channel Material Impact

The time kinetics of interface trap generation and passivation ( $\Delta {N} _{\textsf {IT}}$ ) and its contribution ( $\Delta {V} _{\textsf {IT}}$ ) during and after negative bias temperature instability (NBTI) stress is calculated by using Sentaurus TCAD. The framework consists of Sentaurus process for the formation of realistic device structures and to obtain material and strain information, while Sentaurus device is used to implement the double-interface reaction–diffusion (RD) model for trap kinetics. Capture–emission depassivation (CED) model is used for the inversion layer hole and oxide electric field ( ${E} _{\textsf {OX}}$ )-assisted breaking of hydrogen (H) passivated defects at channel/gate insulator interface. Multistate configuration (MSC) model is used for diffusion of atomic and molecular hydrogen (H and H2) and further reactions with other H passivated defects in gate insulator bulk. Quantum effects are considered for hole density, and band structure calculation is used including mechanical strain for CED model parameters. Electron capture in the generated traps during recovery is calculated using transient trap occupancy model (TTOM) and implemented as a postprocessor. Measured data from silicon (Si) and silicon germanium (SiGe) p-channel FinFETs are used for validating the TCAD framework.

Quantum kinetics approach to calculation of the low field mobility in the hole inversion layers of silicon MOSFET’s

Analytic expressions for low field mobility have been obtained in the quantized p-type inversion layers. The confining potential is approximated by a triangular quantum well. Main attention is paid to study the dependence of the hole mobility on transverse effective field at different temperatures and concentrations of the ionized impurities. Acoustic and optical phonons, charged impurities, and surface roughness have been adopted as scattering system. Theoretical considerations are based on the quantum kinetic equation and special form of the non-equilibrium distribution function (shifted Fermi distribution). Calculations show that the acoustic phonon limited mobility does not depend on the transverse effective electrical field $$E_\mathrm{eff} $$ and has a temperature dependence closer to experiment than known expression for the universal mobility. At the same time, the mobility limited by scattering with optical phonons and surface roughness is proportional to $$E_\mathrm{eff} ^{-1/3}$$ and $$E_\mathrm{eff} ^{-2}$$ , respectively. The mobility limited by scattering by ionized impurities is a weak function of the transverse effective field. Results of the calculations are compared with known experimental data.

Simulation Study of a Novel Snapback-Free and Low Turn-Off Loss Reverse-Conducting IGBT With Controllable Trench Gate

A novel ultra-fast snapback-free controllable trench gate (CTG) reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed and investigated by simulation. It features a CTG in the collector side and a bias voltage ( ${V}_{\text {RC}}$ ) is applied between the CTG and collector electrode. In the forward conduction state with ${V}_{{\text {RC}}} , a high-density hole inversion layer is formed around the CTG. The CTG acts as not only a folded controllable hole injector to enhance the hole injection efficiency, but also an electron barrier to increase the distributed resistance. The CTG RC-IGBT achieves a low on-state voltage drop ( ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) and snapback-free with a small cell pitch. In the blocking state with ${V}_{\text {RC}} > {0}$ , an electron accumulation layer is formed around the CTG. The electron layer together with the CTG acts as an equivalent N-buffer layer to stop the electric field and support high breakdown voltage. During turn-off, the CTG RC-IGBT behaves like a unipolar device without long tail current because the hole injection is deactivated by properly switching the ${V}_{\text {RC}}$ . Compared with conventional RC-IGBT, the proposed device decreases the ${V}_{\text {on}}$ and turn-off energy loss ( ${E}_{\text{off}}$ ) by 34% and 74%, respectively, under the load current of 100 A/cm2 and bus voltage of 600 V.

Bismuth Vanadate Photoelectrodes with High Photovoltage as Photoanode and Photocathode in Photoelectrochemical Cells for Water Splitting.

Using dual-photoelectrode photoelectrochemical (PEC) devices based on earth-abundant metal oxides for unbiased water splitting is an attractive means of producing green H2 fuel, but is challenging, owing to low photovoltages generated by PEC cells. This problem can be solved by coupling n-type BiVO4 with n-type Bi4 V2 O11 to create a virtual p/n junction due to the formation of a hole-inversion layer at the semiconductor interface. Thus, photoelectrodes with high photovoltage outputs were synthesized. The photoelectrodes exhibited features of p- and n-type semiconductors when illuminated under an applied bias, suggesting their use as photoanode and photocathode in a dual-photoelectrode PEC cell. This concept was proved by connecting a 1 mol % W-doped BiVO4 /Bi4 V2 O11 photoanode with an undoped BiVO4 /Bi4 V2 O11 photocathode, which produced a high photovoltage of 1.54 V, sufficient to drive stand-alone water splitting with 0.95 % efficiency.

A hole inversion layer at the BiVO4/Bi4V2O11 interface produces a high tunable photovoltage for water splitting.

The conversion of solar energy into hydrogen fuel by splitting water into photoelectrochemical cells (PEC) is an appealing strategy to store energy and minimize the extensive use of fossil fuels. The key requirement for efficient water splitting is producing a large band bending (photovoltage) at the semiconductor to improve the separation of the photogenerated charge carriers. Therefore, an attractive method consists in creating internal electrical fields inside the PEC to render more favorable band bending for water splitting. Coupling ferroelectric materials exhibiting spontaneous polarization with visible light photoactive semiconductors can be a likely approach to getting higher photovoltage outputs. The spontaneous electric polarization tends to promote the desirable separation of photogenerated electron- hole pairs and can produce photovoltages higher than that obtained from a conventional p-n heterojunction. Herein, we demonstrate that a hole inversion layer induced by a ferroelectric Bi4V2O11 perovskite at the n-type BiVO4 interface creates a virtual p-n junction with high photovoltage, which is suitable for water splitting. The photovoltage output can be boosted by changing the polarization by doping the ferroelectric material with tungsten in order to produce the relatively large photovoltage of 1.39 V, decreasing the surface recombination and enhancing the photocurrent as much as 180%.

Design and simulation of high-breakdown-voltage GaN-based vertical field-effect transistor with interfacial charge engineering

A high-breakdown-voltage GaN-based vertical field-effect transistor with negative fixed interfacial charge engineering (GaN ICE-VHFET) is proposed in this work. The negative charge inverts an n-GaN buffer layer along the oxide/GaN interface, inducing a vertical hole layer. Thus, the entire buffer layer consists of a p+-hole inversion layer and an n-pillar buffer layer, and the p-pillar laterally depletes the n-GaN buffer layer, and the electric field distribution becomes more uniform. Simulation results show that the breakdown voltage of the GaN ICE-VHFET increases by 193% and the on-resistance of such a device is still very low when compared with those of conventional vertical FETs. Its figure of merit even exceeds the GaN one-dimensional limit.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Assessment of pseudo-bilayer structures in the heterogate germanium electron-hole bilayer tunnel field-effect transistor

We investigate the effect of pseudo-bilayer configurations at low operating voltages (≤0.5 V) in the heterogate germanium electron-hole bilayer tunnel field-effect transistor (HG-EHBTFET) compared to the traditional bilayer structures of EHBTFETs arising from semiclassical simulations where the inversion layers for electrons and holes featured very symmetric profiles with similar concentration levels at the ON-state. Pseudo-bilayer layouts are attained by inducing a certain asymmetry between the top and the bottom gates so that even though the hole inversion layer is formed at the bottom of the channel, the top gate voltage remains below the required value to trigger the formation of the inversion layer for electrons. Resulting benefits from this setup are improved electrostatic control on the channel, enhanced gate-to-gate efficiency, and higher ION levels. Furthermore, pseudo-bilayer configurations alleviate the difficulties derived from confining very high opposite carrier concentrations in very thin structures.

Conductance Along the Interface Formed by 400 °C Pure Boron Deposition on Silicon

The conductance along the interface between an as-deposited pure boron layer and n-type Si, fabricated at 400 °C, is found to be reliably formed with high-ohmic sheet resistance values going from $\sim 30$ k $\Omega $ /sq to 1 M $\Omega $ /sq, depending on the exact substrate doping and biasing. The temperature coefficient is negative. It is proposed that this behavior is due to an interface monolayer of electron-filled acceptor states attracting an inversion layer of holes that provide ideal p+n junction behavior and lateral carrier transport unperturbed by interface defects.

500 V dual gate deep‐oxide trench SOI‐LIGBT with improved short‐circuit immunity

A 500 V deep-oxide trench silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with improved short-circuit capability is proposed. The structure features dual trench gates: one gate (G1) extended to the buried oxide and the other gate (G2) arranged in the deep-oxide trench in the drift region. In the off-state, G2 acts as an emitter-side field plate to shield the lateral electric field from the collector side. In the on-state, negative voltage is applied to G2, leading to a hole inversion layer close to the deep-oxide trench. The hole inversion layer reroutes the hole current and provides an additional heat dissipation path. Experimental results show that the proposed structure exhibits high short-circuit immunity without degradation of the breakdown voltage. The short-circuit withstand time of the proposed structure is 1.55 times that of the conventional one, when the voltage of G2 is −5 V.

Assessment of field-induced quantum confinement in heterogate germanium electron–hole bilayer tunnel field-effect transistor

The analysis of quantum mechanical confinement in recent germanium electron–hole bilayer tunnel field-effect transistors has been shown to substantially affect the band-to-band tunneling (BTBT) mechanism between electron and hole inversion layers that constitutes the operating principle of these devices. The vertical electric field that appears across the intrinsic semiconductor to give rise to the bilayer configuration makes the formerly continuous conduction and valence bands become a discrete set of energy subbands, therefore increasing the effective bandgap close to the gates and reducing the BTBT probabilities. In this letter, we present a simulation approach that shows how the inclusion of quantum confinement and the subsequent modification of the band profile results in the appearance of lateral tunneling to the underlap regions that greatly degrades the subthreshold swing of these devices. To overcome this drawback imposed by confinement, we propose an heterogate configuration that proves to suppress this parasitic tunneling and enhances the device performance.

Aluminum-oxide-based inversion layer solar cells on n-type crystalline silicon: Fundamental properties and efficiency potential

We introduce a rear-emitter inversion layer (IL) solar cell on n-type crystalline silicon (n-Si). The hole IL is induced by the high density of negative fixed charges in an aluminum oxide (Al2O3) surface passivation layer. For the formation of contacts to the inversion layer, we employ a single-step p+ laser doping process, using aluminum from the Al2O3 layer as dopant source. Lateral hole transport through the IL underneath the n-Si/Al2O3 interface is analyzed by electrical measurements. The IL hole mobility is shown to be only marginally reduced by scattering at the high density of fixed charges at the n-Si/Al2O3 interface, resulting in an inversion layer sheet resistance of 15–18 kΩ/sq (in the dark). The effective sheet resistance of the IL is shown to decrease to below 4 kΩ/sq under solar cell operating conditions. Based on two-dimensional device simulations, we show that the proposed type of n-type silicon IL solar cell has a very high efficiency potential exceeding 26% including contact recombination losses.

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

The electron-hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg ~ 40 mV/dec up to VDD. Furthermore, it has been demonstrated that high on current levels ( ~ 40 μA/μm) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases.

Electrical characterization and modelling of n–n Ge-Si heterojunctions with relatively low interface state densities

We investigated the electrical behavior of n–n Ge-Si isotype heterojunction diodes prepared by surfactant-mediated epitaxy of relaxed n-Ge layers on (100) n-Si substrates. Current-voltage characteristics were measured at different temperatures between 10 °C and 90 °C. The experimental results were interpreted with a new heterojunction model based on Shockley-Read-Hall kinetics for electron and hole capture/emission at the interface traps, which describes the bias dependent interface and semiconductor charges, the trap-mediated currents, and the thermionic electron transmission current. The modeled thermionic electron emission current was in excellent agreement with the experimental current-voltage characteristics in the whole temperature range for negative (≥−0.5 V) and positive (≤0.1 V) Ge biases. Trap-mediated currents were much smaller for reasonable trap capture cross sections σ ≤ 10−14cm2. From the experimental data, we extracted an electron barrier height of 0.59 eV at room temperature and an effective density of interface traps of only 5·1012cm−2eV−1 near the Si midgap. The charge carrier exchange between these traps with the Ge side was found to be much more efficient than with the Si side. The presence of a hole inversion layer at the interface proved to be essential for the interpretation of the heterojunction characteristics.

Charge losses in segmented silicon sensors at the Si–SiO2 interface

Using multi-channel time-resolved current measurements (multi-TCT), the charge collection of p+n silicon strip sensors for electron–hole pairs produced close to the Si–SiO2 interface by a focussed sub-nanosecond laser with a wavelength of 660nm has been studied. Sensors before and after irradiation with 1MGy of X-rays have been investigated. The charge signals induced in the readout strips and the rear electrode as a function of the position of the light spot are described by a model which allows a quantitative determination of the charge losses and of the widths of the electron-accumulation and hole-inversion layers close to the Si–SiO2 interface. Depending on the applied bias voltage, biasing history and environmental conditions, like humidity, incomplete electron or hole collection and different widths of the accumulation layers are observed. In addition, the results depend on the time after biasing the sensor, with time constants which can be as long as days. The observations are qualitatively explained with the help of detailed sensor simulations. Finally, their relevance for the detection of X-ray photons and charged particles, and for the stable operation of segmented p+n silicon sensors is discussed.

On the origin of the mobility reduction in n- and p-metal–oxide–semiconductor field effect transistors with hafnium-based/metal gate stacks

We examine the mobility reduction measured in hafnium-based dielectrics in n- and p-MOSFETs by means of extensive comparison between accurate multi-subband Monte Carlo simulations and experimental data for reasonably mature process technologies. We have considered scattering with remote (soft-optical) phonons and remote Coulomb interaction with single layers and dipole charges. A careful examination of model assumptions and limitations leads us to the conclusion that soft optical phonon scattering cannot quantitatively explain by itself the experimental mobility reduction reported by several groups for neither the electron nor the hole inversion layers. Experimental data can be reproduced only assuming consistently large concentrations of Coulomb scattering centers in the gate stack. However, the corresponding charge or dipole density would result in a large threshold voltage shift not observed in the experiments. We thus conclude that the main mechanisms responsible for the mobility reduction in MOSFETs featuring Hafnium-based high-κ dielectric have not been completely identified yet. Additional physical mechanisms that could reconcile simulations with experimental results are suggested and critically discussed.

PMOSFET Performance Enhancement With Strained $ \hbox{Si}_{1 - x}\hbox{Ge}_{x}$ Channels

The inversion-layer hole mobility in MOSFETs with thin silicon-germanium (Si1-xGex) channels grown pseudomorphically on Si is calculated using a self-consistent 6 × 6 k ·p Poisson-Schrodinger mobility simulator calibrated to experimental and simulation data. The addition of uniaxial compressive stress to the inherent biaxial compressive strain of the pseudomorphic Si1-xGex layer is found to further enhance hole mobility by up to 2.5×. Two-dimensional device simulations are used to assess the benefit of the Si1-xGex heterostructure channel for boosting the ON-state current (Ion) of p-channel MOSFETs with a gate length (Lg) of 18 nm; the results show a moderate (10%-40%) improvement over a bulk-Si MOSFET.