Hold Power Research Articles

Decentralization as spectacle: An empirical reflection from Pakistan

AbstractMotivationLocal government can develop democracy and community participation if institutions support it. But when a military regime takes over following a coup d'état, it may use familiar methods of patronage, corruption, and exploitation of kinship ties to render decentralization a spectacle—that is, done for show, but without substantial change. Local elites may then capture local administration and extract public resources.PurposeDoes decentralization as spectacle bring positive change — when the military hold power and the state is laden with corruption, patronage, and kinship ties?Methods and approachesWe analyse how respondents experienced two periods of local government, including post‐election public interactions between representatives and their constituents.Data comes from responses to qualitative interviews with 70 key informants from the Qambar Shahdadkot and Larkana districts of Sindh, Pakistan. We analysed the themes generated by responses to questions.FindingsSome 40% of respondents reported those who came into local government power aimed first and foremost to promote the interests of their own class. Some 29% of respondents reported local government made empty promises to provide services with public participation.Pakistan's decentralization has been a spectacle, to serve powerful elites. Local government has been captured by local elites.Policy implicationsDecentralization, muzzled by the military, is mere spectacle, and predatory to boot. Donor agencies should explore possibilities for change at the local level; for example, where local networks and informal governmentality can build up trust amongst hyper‐local communities.

Design analysis of a low-power, high-speed 8 T SRAM cell using dual-threshold CNTFETs

Recently, carbon nanotube field-effect transistors (CNTFETs) have garnered significant attention from VLSI engineers due to their exceptional electrical properties. This paper proposes a novel high-speed, low-power eight-transistor (8 T) static random-access memory (SRAM) cell based on 32-nm CNTFET technology. The SRAM cell was simulated using the HSPICE tool with a VDD of 0.9 V. The high-speed and low-power characteristics of the SRAM design are attributed to the high subthreshold slope and high carrier mobility of metal-oxide-semiconductor field-effect transistor (MOSFET)-like CNTFETs utilized in the simulations. The implementation of dual threshold transistors, coupled with a transmission gate for bitline access, contributes to the enhanced performance. Key performance metrics such as noise margins, power consumption, delay, and SRAM electrical quality metric (SEQM) of the proposed SRAM have been evaluated and compared with existing CNTFET-based SRAM designs. The proposed cell demonstrates reductions of 73.73%, 43.18%, and 58.70% in read power, write power, and hold power, respectively, compared to the lowest respective power values of other examined SRAM designs. The proposed SRAM ranks second, third, and second in write static noise margin (WSNM), hold static noise margin (HSNM), and read static noise margin (RSNM), respectively, among other designs. Additionally, the proposed SRAM exhibits the least sensitivity to parametric variations compared to other designs. The SEQM, which provides a comprehensive assessment of access times, noise margins, and power usage for the SRAM cell, has been calculated. The SEQM of the proposed SRAM is 10.6, 1.89, 13.15, and 1.82 times higher than that of C6T, BLP8T, Mani’s 10 T, and LP8T, respectively.

A Neurocognitive Model for Analyzing End Time Narratives: the Book of Revelation 14–16 as a Test Case

Abstract In this article, we introduce a neurocognitive model as a useful analytical approach to a wide range of representations (written, oral, and/or visual) of a comprehensive and dramatic collapse of the world order (cosmic, social, and/or moral). We gather these variegated representations under the term End Time Narratives (ETN). The widespread reception of ETNs, and their popularity and variability across different periods and cultures, is evidence that these representations continually affect us and hold power over us. Prominent and well-known examples of ETNs are the Jewish and Christian apocalypses from antiquity, which have been widely influential through the centuries. This prevalence raises the question of why ETNs exercise such an influence. The reasons, we suggest, are based on the following hypotheses: (1) that the efficacy and attraction of ETNs can be traced to identifiable cognitive mechanisms, (2) that these underlying mechanisms are linked to certain emotional reactions activated by the particular structure and design of these narratives, and (3) ETNs – as cultural products – seem to be designed and structured to elicit cognitive and emotional responses through effects on the brain. To investigate the possible neurocognitive and psychological mechanisms that are simulated and enacted in recipients by ETNs, we apply the model through an “enactive reading” of a classical ETN, the Book of Revelation 14–16.

A 45nm AND 65nm CMOS IMPLEMENTATION OF 12T SRAM CELL WITH SOFT ERROR READ STABILITY OF MULTINODE UPSET RECOVERABILITY FOR AEROSPACE APPLICATION

With technology advancing rapidly, the size of transistors and the distance between them is decreasing quickly. This reduction in size is causing the critical charge of sensitive nodes in SRAM cells to decrease, making them more susceptible to soft errors, especially in aerospace applications. When a radiation particle strikes a open node in a standard 6T SRAM cell, the storage data in the cell can be changed, leading to a single-event upset (SEU). To address this issue, a new Soft Error Read and write Stability improves Low Power 12T (SARP12T) SRAM cell has been introduced in this study to reduce the impact of SEUs. The performance of SARP12T has been compared to other recently developed soft-error-aware SRAM cells like QUCCE12T, QUATRO12T, RHD12T, RHPD12T, and RSP14T. SARP12T is designed for the recoverability of all stored data in sensitive nodes even if they are affected by radiation strikes. Additionally, SARP12T can overcome single-event multi-node upsets (SEMNUs) that may happened at its sensitive node pair. This proposed cell also boasts the higher read stability, as the storage node holding '0' can regain from any upset during read operations. Moreover, SARP12T consumes the minimum amount of hold power, has greater write ability, and lower write delay compared to other similar cells. Despite a almost greater read delay and higher read and write energy consumption, the improvements in the proposed SARP12T cell make it a promising solution for mitigating soft errors in SRAM cells

Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM for Aerospace Applications

As the technology has rapidly evolved and also high-speed task implementation has come into picture the chance for an error to occur has also increased though there are many precision algorithms to increase the precision of the system significantly this paper proposes one such error reducing application for aerospace applications. Using a Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications (QUCCE12T) is more susceptible to data loss as the QUCCE12T SRAM has high sensitivity and the sensitive nodes are at higher risk. To reduce this, we propose to use Soft-Error Reduction and Enhancement of Write Stability and Hold Power Optimization by using 12T SRAM (SREWH12T). Basically, the initial thought is to reduce the soft error created by voltage drops by passing the data through the inverters. The Single Event Upset (SEU) that arise in the usage of QUCCE12T SRAM can be recovered using a SREWH12T SRAM instead. The sensitive components of SREWH12T have the capability to recover their data even in cases where the values have been altered by radiation impact. The SREWH12T SRAM cell to mitigate upsets, compares it with other cells, and demonstrates its superior performance in terms of soft-error tolerance, recovery from upsets and having low power consumption. Furthermore, the added advantage of SREWH12T cell is that it can recover from Single Event Multiple Nodes Upset (SEMNU). Average power consumed by SREWH12T is 2.988363e-007 watts. Along with this the SREWH12T SRAM can provide high write stability due to its recovery rate. All these added advantages and recovery of data all comes at high utility range and with slightly high read energy consumption, which is very minimal, the system also exhibits slightly high read delay.

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

Single ended 12T cntfet sram cell with high stability for low power smart device applications

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

A robust radiation resistant SRAM cell for space and military applications

Many charged particles in space, including α-particles, neutrons, heavy ions, electrons, and photons, wreak havoc on the stability and reliability of memory circuits. In addition, these high-energy particles produce an ion track within the memory chip, which disrupts the storage bit. Standard 6T SRAM cannot withstand this upset condition. This paper presents a novel RRS-14T radiation-resistant SRAM memory cell with redundant nodes and a polar design to address the soft error issue. The performance of the proposed RRS-14T memory cell is compared to the performance of existing radiation-resistant memory cells, such as RHS-14T, RHMC-12T, NRHC-14T, QCCS-12T, HRRT-13T, and RHBD-13T. The RRS-14T cell protects against single and multiple-node disruptions. The read stability of the proposed RRS-14T memory cell is 2.83x/ 1.5x/ 2.10x/ 1.34x/ 3.38x/ 1.68x greater than the existing RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. Moreover, 1.08x/ 1.27x/ 1.06x/ 1.05x/ 1.16x/ 1.07x larger write trip voltage than RHS-14T/ RHMC-12T/ NRHC-14T/ QCCS-12T/ HRRT-13T/ RHBD-13T memory cells. In addition, the write access time, hold power, and critical charge are enhanced when the supply voltage is at 1 V.

High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput. 30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell

A new carbon nano-tube field-effect transistors (CNTFETs) based Power Efficient and Robust 8T (PER-8T) SRAM cell is proposed to reduce sub-threshold leakage currents, data dependency by improving RBL swing due to which RSNM is improved. Leakage power is reduced by using only single pull-up transistor with High V t in storage latch. Half-select issue is eliminated since proposed work uses de-coupled read port. This CNTFET based proposed PER-8T cell is analysed for performance parameters like power, delay and stability and compared to 8T SRAM cells at 45 nm technology. All simulations are performed at supply voltage of 0.9 V considering Stanford Virtual Source CNTFET(VS-CNTFET) model. It shows that RSNM and WSNM are improved by 12.07%, 14.85%, 56% and 46.46%, 20.39%, 66.05% compared to single ended 8T SRAM cells available in recent literature. Effects of VS-CNTFET parameters such as dielectric material, temperature, oxide thickness and carbon nano tube diameter values on hold power is analysed and best values are considered. The cadence tool is used for measuring all design metrics at room temperature of 25 °C.

A highly stable and low‐cost 12T radiation hardened SRAM cell design for aerospace application

SummaryIn this paper, a highly stable and low‐cost 12T (HSLC12T) radiation hardened static‐random‐access‐memories (SRAM) cell is proposed in 55 nm CMOS technology. Based on polarity reversal design and read/write separation structure, the proposed HSLC12T cell can recover from any single event upsets (SEUs) induced at all its sensitive nodes and even single event double‐node‐upsets (SEDNUs) induced at its internal storage node pair Q‐QN, while also having the maximum read static noise margin (RSNM) and lower static hold power, as well as excellent write speed and write‐ability. Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed HSLC12T cell a better choice for aerospace applications.

Mathematical study and simulation on stenosed carotid arteries with the help of a two‐phase blood flow model

AbstractThe present study is focused on a medical problem called stenosed carotid artery. The problem is formulated with the help of a two‐phase blood flow model. The non‐Newtonian nature of blood is considered that hold power law. Physical quantities were expressed in tensorial form. Analytical and numerical methods are used to solve equations under given boundary conditions. The effects of various parameters on blood flow like stenosis size, flow flux, resistance, haematocrit, pressure drop, etc. were studied and shown through various graphs. Parameter , which ensures that the fluid is Newtonian or non‐Newtonian; its impact on pressure drop; resistance to flow; and flow flux were obtained during the disease and presented through the graph. A relationship between pressure drop and haematocrit was obtained, which was helpful to predict fluctuation in blood flow during stenosis. We have also given a medical use for this model with the help of pathological data. We also analyzed steady and laminar flow in a carotid artery for different heights of stenosis. The study of various physiological parameters has been performed on the basis of blockage percentage and concentration of haematocrit. The nature of the red blood corpuscle (RBC) phase is considered liquid packets in a semi‐permeable membrane, which makes this model close to reality.

High-performance and highly-stable soft error resistant 12T SRAM cell for space applications

In this paper, a high-performance and highly-stable soft error resistant 12T (HPHS12T) SRAM cell is proposed. Based on polarity reversal design and NMOS stacked structure, the proposed HPHS12T cell can recover from any single event upsets (SEU) induced at all its sensitive nodes and even single event multiple-node-upsets (SEMNU) induced at its internal storage node pair Q-QN, while also having the maximum read static noise margin (RSNM) and write noise margin (WNM), as well as excellent write-ability. Though the HPHS12T cell exhibits a larger static hold power, it has the best overall performance of all the other cells. This is proven by having the highest electrical quality metric (EQM) value, thus making the proposed cell a better choice for space applications.

Hdt. 4.79 διεπρήστευσε

This paper examines the form διεπρήστευσε, obelized in the editions of Herodotus. There have been two ways of interpreting the form: some scholars have taken it to refer to an act of speech, while others have sought here a verb of motion. Both groups of scholars proposed a variety of conjectures, some of them addenda lexicis and none of them commanding immediate acceptance. After a review of various solutions that have been proposed to-date, this paper argues in favor of retaining the reading of the paradosis and analyzing (-)πρηστεύω as a verb of quick motion. The verb is argued to be an Ionic colloquialism (or even Herodotus’ own Augenblicksbildung), derived from the root of πίμπρημι in its original meaning ‘to blow’ (of which ‘to burn’ is a secondary development) via an agent noun πρηστήρ / *πρήστης, cf. μνηστεύω ‘woo’ : μνηστήρ ‘suitor’ or δυναστεύω ‘hold power’ : δυνάστης ‘person with power’. The proposed translation ‘blasted, dashed’ is supported by typological parallels for the semantic development ‘to blow’ → ‘to move (impetuously)’, such as Old English bl.́stan ‘to blow; to move impetuously’ or Russian dut’ ‘to blow; to dash, to rush’. Interestingly, Hittite (parip) parāi-, the cognate of Gk. πίμπρημι, may show the same semantic

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

With technology scaling, transistor sizing as well as the distance between them, is decreasing rapidly, thereby reducing the critical charge of sensitive nodes. This reduction makes SRAM cells used for aerospace applications more susceptible to radiation as it can cause single-event upsets (SEUs) and also single-event multi-node upsets (SEMNUs). This article presents an energy-efficient dual-node-upset-recoverable 12T SRAM cell for low-power aerospace applications, EDP12T, in 65-nm CMOS technology. The proposed cell mitigates SEUs as well as SEMNUs. To judge the relative performance of EDP12T, a comparative study is made between it and other radiation-hardened cells: RHM12T, QUCCE12T, QUATRO12T, RHD12T, SRRD12T, RHPD12T, RSP14T, LWS14T, SAR14T, and S8P4N16T. EDP12T can recover from SEUs induced at all the sensitive nodes and from SEMNUs that have occurred at its internal node-pair. EDP12T exhibits better write performance than most of the comparison cells, it also consumes the least energy during write mode, and lower energy than most of the comparison cells during read mode. EDP12T exhibits a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.08\times /1.17\times /1.37\times /1.56\times /2.32\times $ </tex-math></inline-formula> higher read stability than S8P4N16T/RHPD12T/QUCCE12T/QUATRO12T/LWS14T. Additionally, EDP12T dissipates the lowest hold power among all the cells for comparison, except for RHM12T. These improvements are obtained by the proposed cell while consuming a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.03\times /1.06\times /1.07\times /1.08\times /1.14\times /1.43\times /2.01\times $ </tex-math></inline-formula> lower area than SAR14T/RHD12T/S8P4N16T/RSP14T/LWS14T/RHPD12T/SRRD12T. However, these advantages come with a slight penalty in the read delay.

The Whiteness of the White

The Whiteness of the White

Accountability in electoral accounting: the electorate perspective

Purpose: The objective of the work is to analyze the aspects evidenced by voters about the duty of provision of electoral accounts.&#x0D; Methodology: Data were collected in Imperatriz/MA by application of an online questionnaire. In the end, 329 responses were obtained, which made up the textual corpus for lexical analysis. In the treatment of data, a combination of quantitative and qualitative approaches was used. The IRaMuTeQ software was used to support the following analyses: lexicographical, word cloud, similitude and correspondence.&#x0D; Results: Campaigns are useful to demonstrate how electoral assets are managed, and the appropriate means to this end is provision of accounts. There is a conflict of interests in the analyzed agency relationship, that is, between citizens and governments. It’s just that, for the electorate, it is up to their representatives to prove the fulfillment of even promises, which is justifiable based on the principle that the people hold power. It so happens that, by law, political agents are only required to record accounting and financial information on electoral campaigns. Another indication of the informational disparity is that voters perceive a lack of reliability in the data of the provision of electoral accounts themselves. However, the problem of the quality of the information provided can be solved through the conservation of an ethical political environment, the permanent political participation of citizens and the incisive action of constitutional powers and bodies.&#x0D; Contributions of the study: It investigates how the provision of electoral accounts is seen by voters, who are some of the main stakeholders in the accuracy of accounting and financial information. It defines, therefore, a panorama based on the vision of these users about the referred duty, considered as a necessary mechanism for political representation, but also ideal for guaranteeing the fulfillment of the government plan. Informational asymmetry was identified in the participants discourse when they punctuated certain problems for which they also indicated possible solutions.

Commemorative contention: The Taipei National Revolutionary Martyrs’ Shrine and the politics of death

AbstractThis article addresses the Taipei National Revolutionary Martyrs’ Shrine (Guomin geming zhonglie ci) as a site of contention over national sovereignty and belonging. The shrine originated in Sun Yat-sen's aspiration to commemorate the anti-imperial martyrs of the 1911 Republic and in the Nationalist government's attempt to marshal political allegiance in the 1920s–1940s. Upon fleeing from the mainland to Taiwan after losing to the Communist forces in 1949, the Nationalist leadership renovated the Japanese-built National Protection Shrine in Taipei, transforming it into the National Revolutionary Martyrs’ Shrine to house the displaced spirits of the national dead. Throughout the Cold War era, the spring and autumn sacrifices performed by heads of state and visits to the shrine by foreign dignities served to affirm the sovereignty of the Republic of China vis-à-vis the People's Republic of China. Even though the end of martial law in 1987 opened a new era marked by the Nationalist Party's loss of political hegemony, the shrine continued to adhere to the Nationalist Party's ideology and version of history. Far from embodying a place of remembrance and mourning for war victims, the palace-style compound is a site of contested sovereignty exaggerated by China's extraordinary growth and Taiwan's transforming identity. The enshrined dead have found a new role as both an assertion of the island's autonomy and a reflection of its dynamism. The departed, albeit silent, hold power in the malleability of their memories, and each permutation of how the past is remembered hosts its own tension.

The Case for Bearing Psychic Pain as Social and Clinical Action

While humans are hardwired to avoid pain and seek good feelings, it has become imperative to override this proclivity in order to properly address the socio-cultural atrocities which are at the heart of the crumbling of American society. This paper delineates the psychosocial reasons why people avoid psychic pain, the multitude of bastions available which enable, aid and abet this shielding, as well as negative consequences of these systemic dynamics. The case for bearing and holding psychic pain and suffering is made with regard to positive personal consequences and social justice dialectical reverberations. The many ways in which the therapist or analyst hold power and privilege within the dyad is reviewed. Bearing sociocultural pain in the therapist’s own transference and countertransference is reviewed and linked to clinical illustrations. Implications for socio-cultural and therapeutic repair are delineated.

A highly reliable radiation tolerant 13T SRAM cell for deep space applications

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (HPWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (TRA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (VDD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (QC) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at VDD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (TWA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at VDD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell.