High On-currents Research Articles

Variable-area capacitors controlled by HfO2-based ferroelectric-gate field-effect transistors

We propose a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a paraelectric thin-film capacitor. Owing to the large charge controllability and nonvolatile memory function of the ferroelectric Hf0.86Ce0.14O2 (14% Ce-HfO2) gate insulator, the variable-area capacitors exhibited high capacitance tuning ratios of up to 184 with steep modulation to gate voltage swing (440 mV/decade), a capacitance-switching speed of less than 10 ms, and capacitance-memory-retention characteristics of up to 105 s. An FeFET with an indium tin oxide (ITO) channel and a ferroelectric 14% Ce-HfO2 gate insulator was fabricated as a switching FET via chemical solution deposition, followed by stacking a sputtered Al2O3 film as a variable capacitor. The fabricated FeFETs exhibited a high on-current of ∼0.15 A/mm, a large on/off current ratio of 107, a field-effect mobility of 15.6 cm2/V s, and a memory window of ∼5 V. The high on-current, i.e., low on-resistance (84 Ω), and the large on/off current ratio allow the ITO channel to act as a wiring that connects and disconnects two capacitors with different electrode areas; therefore, the proposed variable capacitor can achieve wide and steep modulation by ferroelectric gating. This study provides prospects for the future integration of passive and active components for advanced high-efficiency and miniaturized electronics such as power devices and communication equipment.

Unveiling the electrical and photo-physical properties of intrinsic n-type 2D WSe2 for high performance field-effect transistors

Atomically thin semiconducting 2D transition metal dichalcogenides have garnered remarkable attention from the scientific community due to their prodigious contributions in the field of next-generation electronic and optoelectronic devices. In this continuation, we report a facile synthesis protocol of monolayer WSe2 films via the atmospheric-pressure chemical vapor deposition (APCVD) technique using hydrothermally synthesized hexagonal-phase tungsten oxide (h-WO3) nanorods. The as synthesized WSe2 crystal is a monolayer of ∼0.9 nm thickness as confirmed by atomic force microscopy. The confocal Raman and photoluminescence (PL) mapping suggests that the grown monolayer WSe2 triangles have lattice defects at edge sites, with a slight red-shift of ∼2 nm in PL, a blue-shift of ∼2 cm−1 in Raman peak and reduction in both the intensities. Confocal time-resolved PL mapping at edges reveals a fast-decay component of ∼582 ps and a slow-decay component of ∼2.18 ns that also signifies the presence of lattice defects, which serves as localized-states for photon-generated charge excitons. Furthermore, we have also investigated its electrical property by devising field-effect transistors (FETs). The fabricated WSe2 based FET shows intrinsic n-type behavior. WSe2 FET offers an electron mobility (μ) of ∼13.2 cm2 V−1 s−1, current ON/OFF ratio of ∼107 with a subthreshold slope (SS) of ∼397 mV/decade, which is relatable to the other reported works on WSe2 based FETs. In addition, the device exhibits very high on-current of order of ∼150 μA/μm. These results indicate that h-WO3 nanorod assisted APCVD synthesized WSe2 has prospective of being a competitor for next-generation optoelectronic, and valley-tronic devices.

Self-Aligned Double Injection-Function TFT for Deep Sub-Micrometer Channels’ Length—Application to Solution-Processed Indium Gallium Zinc Oxide

We propose and demonstrate self-aligned Double Injection Function Thin Film Transistor (DIF-TFT) architecture that mitigates short channel effects in 200 nm channel on non-scaled insulator (100 nm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). In this conceptual design, a combination of ohmic-like injection contact and a high injection-barrier metal allows maintaining the high ON currents while suppressing drain-induced barrier lowering (DIBL) effects. Using an industrial 2-D device simulator (Sentaurus), we propose two methods to realize the DIF concept. We use one of them to demonstrate, experimentally, a DIF-TFT based on solution-processed indium gallium zinc oxide (IGZO). Using molybdenum as the ohmic contact and platinum as the high injection barrier, we compare three transistors’ source-contacts: ohmic, Schottky, and DIF. The fabricated DIF-TFT exhibits saturation at sub 1 V drain bias with only about a factor of 2 loss in ON current compared to the ohmic contact.

Atomically thin In2O3 field-effect transistors with 1017 current on/off ratio

Recent advances have enabled the demonstration of record high-performance atomically thin n-type indium oxide (In2O3) field-effect transistors with low thermal budget suitable for back-end-of-line logic or memory applications. By using ultra-thin layers of In2O3, its degenerate carrier density is suppressed so that it can be modulated by conventional dielectric gating. These devices have high on-currents due to its high mobility and low contact resistance; meanwhile they can have exceptionally low off-currents due to its wide bandgap. For both low-power logic and memory, the off-state performance should be understood in more detail, although they are constrained by the limits of traditional measurement techniques. In this Letter, we systematically probe the off-current of ultra-thin In2O3 transistors by adopting a wide channel geometry with temperature-dependent electrical measurements and demonstrate the potential for record high current on/off ratios of 1017 on In2O3 transistors.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (I ON ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher I ON /I OFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

Impactful Study of F-shaped Tunnel FET

In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric field crowding effect at the corners of the source region which reflect in terms of high ON-current (Ion). The Ion of the proposed device is increased up to 10− 4 A/μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.

Strain-tuning PtSe2 for high ON-current lateral tunnel field-effect transistors

We use full-band quantum transport simulations to show that monolayer platinum diselenide (PtSe2) tunnel field-effect transistors (TFETs) can deliver high ON currents (ION) under biaxial tensile strain, while maintaining a sub-60 mV/dec subthreshold swing. When strained, monolayer PtSe2 develops a lower effective mass and a small gap across which an efficient tunneling can occur, translating to a high ION when used in a TFET channel. At a drain voltage of 0.8 V and OFF current of 1×10−7 μA/μm, a simulated device with a 5% strained channel has an ION &amp;gt; 116 μA/μm, which is three orders of magnitude greater than that of the unstrained unoptimized device. The corresponding I60 is also increased by 600 times. This improvement comes at a reasonable cost of degradation in the OFF state and has a minimal effect on the switching characteristics down to 10 nm channel length. Our results present the mechanical flexibility of 2D materials as a powerful tuning parameter toward their use in high-performance tunneling devices.

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

PurposeHigh packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.Design/methodology/approachSilicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.FindingsThe proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.Originality/valueGermanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Van der waals BP/InSe heterojunction for tunneling field-effect transistors

Introducing heterogeneous architecture is a prospective way to improve tunneling field-effect transistors (TFETs). We investigate the van der Waals (vdW) heterojunction based on monolayer black phosphorene and indium selenide (BP/InSe heterojunction) and the double-gated 10-nm TFETs based on the vdW BP/InSe heterojunction with the contact length and position by using the ab-initio quantum transport simulations. The vdW BP/InSe heterojunction shows a type-II band edge alignment. The optimal vdW BP/InSe heterojunction TFETs have a 1-nm-length BP/InSe heterojunction at the channel’s left and right sites (1L and 1R for short). Novelty, the BP/InSe heterojunction TFETs with 1L and 1R configurations are n- and p-type devices, respectively, and corresponding high on-currents of 240 and 408 μA/μm are obtained for high-performance application (off-current: 0.1 μA/μm) at a very low supply voltage (0.3 V).

Investigation of Subthreshold Characteristics of Negative Capacitance Single-Active Layer Double-Gate (NC-SALDG) Thin-Film Transistor (TFT)

In this paper, for the first time, the performance evaluation of negative capacitance single-active layer double-gate (NC-SALDG) TFT is presented. In the proposed NC-SALDG TFT, amorphous InGaZnO material is used as an active layer owing to its enhanced carrier mobility and improved optical transmittance properties. By coupling the TCAD numerical simulation with 1D Landau-Khalatnikov (LK) equation, a semi-analytical model of NC-SALDG TFT is developed. The subthreshold characteristics of NC-SALDG TFT are analyzed by varying the thickness of aluminum (Al) doped HfO2 and different ferroelectric materials. Further, high ON current, low OFF current, and better minimum & average subthreshold swing of NC-SALDG TFT are observed for Al-doped HfO2 material compared to its counterparts. From the result analysis, the proposed NC-SALDG TFT shows superior subthreshold performance over conventional SALDG TFT. The baseline SALDG TFT was simulated with 2D TCAD simulator Atlas™ from Silvaco.

Silicon Nanowire Parameter Extraction Using DFT and Comparative Performance Analysis of SiNWFET and CNTFET Devices

The performance and scalability of silicon nanowire field-effect transistor (SiNWFET) and carbon nanotube field-effect transistor (CNTFET) with surround gate geometry were studied using such tools as material exploration and design analysis (MedeA) and device modeling and simulation SilvacoTCAD. The SiNWFET and CNTFET with gate-all-around (GAA) structure offer good gate electrostatic control, high On-current and better suppression of short-channel effects with complete encirclement of the device channel. Rather than using the bulk properties of silicon, estimation of properties silicon nanowire (SiNW) was made using MedeA VASP tool based on density functional theory (DFT). In this study, the device input (ID–VGS) and output (ID–VDS) have been analyzed and parameters like threshold voltage, IOn/IOff ratio, drain induced barrier lowering and sub-threshold slope extracted, and comparison is made between SiNWFET and CNTFET devices. The results point towards the DFT-based material parameter estimation to incorporate the quantum effects and use of SiNW/CNT-based GAA structure below 10 nm to meet scaling targets. The results suggest that the SiNWFET and CNTFET device with GAA geometry could be a better alternative to conventional MOSFETs and FinFET for numerous high-performance and low-power device applications.

First RF Power Operation of AlN/GaN/AlN HEMTs With &gt;3 A/mm and 3 W/mm at 10 GHz

The AlN/GaN/AlN heterostructure is attractive for microwave and millimeter-wave power devices due to its thin top barrier, tight carrier confinement, and improved breakdown voltage. This work explores the large-signal RF performance of high-electron-mobility transistors on this heterostructure. Results are highlighted by record high on-current of 3.6 A/mm, and record maximum oscillation frequency ( $f_{max}$ ) of 233 GHz. The load-pull power sweep at 10 GHz demonstrate a peak power added efficiency (PAE) of 22.7% with an associated gain ( $G_{T}$ ) of 8.7 dB and output power ( $P_{out}$ ) of 3 W/mm. When optimized for power, the peak $P_{out}$ of 3.3 W/mm has an associated PAE of 14.7% and $G_{T}$ of 3.2 dB. This first demonstration is encouraging for the mm-wave power potential of the AlN/GaN/AlN HEMT.

Special Topic on Tunnel Field-Effect Transistors

The tunneling field-effect transistor (T-FET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage ( $V_{\mathrm {DD}}$ ). Reducing supply voltage while keeping a low leakage current and a reasonably high ON-current is critical for minimizing energy consumption and continue Moore’s law by helping with energy efficiency of computing. The thermal limit of the MOSFET transistor subthreshold swing (SS) restricts lowering its threshold voltage ( $V_{t}$ ), causing significant performance degradation at low $V_{\mathrm {DD}}$ . A T-FET’s SS is not limited by this thermal tail and may perform better at low $V_{\mathrm {DD}}$ .

A hybrid self-aligned MIS-MESFET architecture for improved diamond-based transistors

Diamond is a promising electronic semiconductor candidate that has recently attracted intense interest in the implementation of its superior physical properties in electronic devices. In particular, attention has been focused on the surface transfer doping of diamond, in which the hydrogen-terminated diamond (diamond:H) benefices of a unique conductive two-dimensional hole gas (2DHG) layer at the diamond's sub-surface upon coverage with a suitable surface acceptor. Several diamond:H transistors have been developed. However, their inherent architecture dependence on the diamond:H conductive surface sensitivity to harsh processing environments has been a major barrier to the realization of high-performance devices. Here, we report on a diamond:H transistor structure that incorporates a mutual diamond:H active channel into the hybrid model of a metal-semiconductor field-effect transistor (MESFET) and a self-aligned metal-insulator-semiconductor FET (MISFET) with a common gate connection. The resulting diamond:H hybrid transistor exhibits a beneficial symbiosis that includes the advantages of both the MISFET (a high ON current of 0.8 μA/μm and a low OFF current of ∼10−9 μA/μm) and MESFET (almost an ideal subthreshold swing of 67 mV/dec) performance operations in the same multilayered device.

Investigation of the Electrical Properties of Double-Gate Dual-Active-Layer (DG-DAL) Thin-Film Transistor (TFT) with HfO2|La2O3|HfO2 (HLH) Sandwich Gate Dielectrics

In this paper, the electrical properties of a double-gate dual-active-layer (DG-DAL) thin-film transistor (TFT) are investigated. To increase the ON-current and pixel intensity, and control the voltage stress bias, the conventional gate oxide material (silicon dioxide, SiO2) is replaced with a tri-high-k gate dielectric layer, hafnium dioxide (HfO2)/lanthanum oxide (La2O3)/hafnium dioxide (HfO2)—(HLH). Further, the performance of the proposed DG-DAL structure is compared with the single-active-layer (SAL) and dual-active-layer (DAL) TFTs. The amorphous indium-gallium zinc-oxide (a-IGZO) is considered as active layer for SAL channel region, and on the other hand, a-IGZO and indium-tin-oxide (ITO) are considered as active layers for DAL TFT and DG-DAL TFT channel regions. The parameters such as OFF-current, ON-current, ION/IOFF ratio, threshold voltage, mobility, average subthreshold swing, etc. are evaluated for the considered structures. It is observed that the DG-DAL TFT with HLH dielectric offers high ON-current of 3.85 × 10–3 A/μm, very low OFF-current of 2.53 × 10–17 A/μm, very high ION/IOFF ratio of 1.51 × 1014, threshold voltage of 0.642 V, high mobility of 35 cm2 v–1 s–1 and average subthreshold swing of 127.84 mV/dec. A commercial TCAD simulation tool ATLAS from SilvacoTM is used to investigate all the parameters for considered structures.

First-principles investigations on MXene-blue phosphorene and MXene-MoS2 transistors

In the semiconductor industry, one of the most important steps in the development of electronic devices is the discovery of electrode materials that are suitable for ohmic contact. As a newly found type of 2D materials, MXenes have been explored as materials for use in field effect transistors (FETs) with promising performances, which urges for the underlying mechanisms to be understood. In this work, the behaviors of the 5–10 nm device models for monolayer blue phosphorene (BlueP) and MoS2 with a MXene electrode are investigated using ab initio quantum transport simulations. Firstly, the interfacial properties of BlueP and MoS2 in contact with M3C2T2 (M = Ti, Zr, or Hf; T = F, OH, or O) MXene are studied. The results show that OH and some of the F functionalized MXenes form an n-type ohmic contact with BlueP or MoS2, while the O functionalized MXenes form a p-type ohmic contact with BlueP and MoS2. Accordingly, when the FET model is built with M3C2(OH)2 electrodes, these FETs exhibit high on-currents due to the ohmic contacts with subthreshold swing between 100 ∼ 200 mV/decade, and high on/off ratios up to 106 at a bias voltage of 0.5 V. Our results imply that a FET with a sub-10 nm channel length can satisfy the requirements of both high performance and low power logic applications. The results from this study indicate that MXenes may act as the appropriate electrode for high-performance BlueP and MoS2 FETs, which may provide new clues to guide the application of various 2D materials in electronics.

The influence of low indium composition ratio on sol–gel solution-deposited amorphous zinc oxide thin film transistors

In this work, we examined the influence of In doping on the morphological and structural characteristics of ZnO active layers grown by the spin coating and the electrical performance of ZnO-based thin film transistors. XRD results indicated that the active layers were amorphous due to the absence of any sharp peaks. XPS analysis was carried out to determine indium amounts as an atomic percentage in ZnO and oxidation state of In. AFM images indicated that the roughness of the active layers decreased with increasing indium concentration in ZnO. The indium doping has dramatically improved the electrical parameters of ZnO-based transistors. The field-effect mobility of undoped TFT increased ~ 157 times by adding %3 In content. The highest field-effect mobility (μsat) of 12.9 cm2V−1 s−1 was obtained for %3 In-doped ZnO TFT (IZO3). Also IZO3 has a 6.96 V threshold voltage (Vth), 106Ion/Ioff ratio, 1.98 V/dec subthreshold slope (SS), and a high on-current of 4.6 mA. We ascribed the performance enhancement of devices with In doping due to increasing carrier concentration of channel. These results show that the low concentration of indium incorporation is very crucial to change the morphological properties of ZnO active layers and to obtain high-performance solution-processed TFTs.

Impact of drain doping engineering on ambipolar and high-frequency performance of ZHP line-TFET

In this paper, we present a new Z-shaped line tunnel field effect transistor (TFET) employing drain doping engineering with a split drain structure (SD-ZHP-TFET). The split drain (SD) approach in the proposed ZHP-TFET helps increasing tunneling width at the channel-drain interface, reducing ambipolarity. Moreover, a horizontal pocket (HP) is implanted in the source region to boost the ON-current of the proposed SD-ZHP-TFET structure. The effect of both these approaches in the line-TFET provides higher ON-current and reduces ambipolarity significantly. Split drain structure in the ZHP-TFET exhibits a three-decade improvement in the ambipolar current without affecting the subthreshold (SS) and leakage current significantly. A calibrated simulation study of split drain thickness (tu) and drain region doping variation on the analog performance are investigated using the technology computer-aided design device simulator. Moreover, the high-frequency figure of merit regarding total gate capacitance (Cgg), unit-gain cut-off frequency (fT) is analysed. It is found that the drain doping improves the cut-off frequency from 1.8 GHz in ZHP-TFET to 2.2 GHz in the proposed SD-ZHP-TFET structure. Thus the proposed device is capable of providing higher ION/IOFF (≈1013) and ION/IAMB (≈1013) ratio with an average SS of 44 mV/decade.

The impact of donor/acceptor types of interface traps on selective buried oxide TFET characteristics

This paper investigates the reliability of the selective buried oxide TFET δp+ silicon-germanium layer at the tunneling junction. The impact of various uniform and Gaussian trap distributions and energies on the band-to-band tunneling current has been examined. The device has been optimized for different gap positions in the buried oxide. The OFF current of the proposed device is 1.7 × 10−18 A/µm. It has been observed that the effect of Gaussian trap is more compared to that of uniform trap. The study quantifies the DC parameters such as ION/IOFF ratio, subthreshold swing against different types of interface traps (donor or acceptor), density (Dit), position (near the tunneling junction or oxide/channel interface) and trap energy level (Etrap). Drain current reduces in the presence of acceptor-type trap and the variation is more for large trap density (1 × 1014 cm−3). An opposite behavior is perceived in the presence of donor-type traps. The device with highest acceptor trap concentration (1 × 1014 cm−3) provides minimum ON current of 2.21 × 10−6 A/µm whereas in case of donor trap concentration (1 × 1014 cm−3), highest ON current of 2.93 × 10−5 A/µm is obtained. The device with no traps proves to be better by providing maximum ION/IOFF ratio of 3.89 × 1012 with SS of 45 mV/dec. Further, the affectability of quantum correction on various electrical parameters has been studied for different types of traps.