High Effective Mobility Research Articles

High-Performance In0.23Ga0.77 As Channel MOSFETs with High Current Ratio Ion/Ioff Grown on Semi-insulating GaAs Substrates by MOCVD

We demonstrate high-performance In0.23 Ga0.77 As channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with high on-current to off-current (Ion/Ioff) ratio grown on semi-insulating GaAs wafers by metal-organic chemical vapor deposition (MOCVD). The 2 μm channel-length devices exhibit a peak extrinsic transconductance of 150 mS/mm and a drain current up to 500 mA/mm. The maximum effective mobility is 1680 cm2/Vs extracted by the split C-V method. Furthermore, the Ion/Ioff ratio is significantly improved from approximately 4.5 × 103 up to approximately 4.32 × 104 by controlling the etch thickness of In0.49 Ga0.51 P. The high drain current and high Ion/Ioff ratio of the In0.23 Ga0.77 As channel MOSFETs are achieved due to the high effective mobility and the low gate leakage current density.

Highly effective field-effect mobility amorphous InGaZnO TFT mediated by directional silver nanowire arrays.

In this work, we demonstrate sputtered amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) with a record high effective field-effect mobility of 174 cm(2)/V s by incorporating silver nanowire (AgNW) arrays to channel electron transport. Compared to the reference counterpart without nanowires, the over 5-fold enhancement in the effective field-effect mobility exhibits clear dependence on the orientation as well as the surface coverage ratio of silver nanowires. Detailed material and device analyses reveal that during the room-temperature IGZO sputtering indium and oxygen diffuse into the nanowire matrix while the nanowire morphology and good contact between IGZO and nanowires are maintained. The unchanged morphology and good interfacial contact lead to high mobility and air-ambient-stable characteristics up to 3 months. Neither hysteresis nor degraded bias stress reliability is observed. The proposed AgNW-mediated a-IGZO TFTs are promising for development of large-scale, flexible, transparent electronics.

Multi-channel ferroelectric-gate field effect transistors with excellent performance based on ZnO nanofibers

Bottom-gate multi-channel ferroelectric-gate field effect transistors (FETs) based on ZnO nanofibers were fabricated, using Bi3.15Nd0.85Ti3O12 (BNT) thin film as the gate insulator and ZnO nanofibers as the semiconductor multi-channel. The electrical characteristics of the multi-channel ZnO nanofiber ferroelectric-gate FETs showed typical p-channel transistor properties with a low threshold voltage of −0.5 V, a high effective field effect mobility, and a large on/off current ratio of 104. These excellent performances are attributed to the multi-channel ZnO nanofiber and BNT ferroelectric-gate insulator.

High-mobility solution-processed zinc oxide thin films on silicon nitride

A high effective electron mobility of 33 cm2 V–1 s–1 was achieved in solution-processed undoped zinc oxide (ZnO) thin films. The introduction of silicon nitride (Si3N4) as growth substrate resulted in a mobility improvement by a factor of 2.5 with respect to the commonly used silicon oxide (SiO2). The solution-processed ZnO thin films grown on Si3N4, prepared by low-pressure chemical vapor deposition, revealed bigger grain sizes, lower strain and better crystalline quality in comparison to the films grown on thermal SiO2. These results show that the nucleation and growth mechanisms of solution-processed films are substrate dependent and affect the final film structure accordingly. The substantial difference in electron mobilities suggests that, in addition to the grain morphology and crystalline structure effects, defect chemistry is a contributing factor that also depends on the particular substrate. In this respect, interface trap densities measured in high-κ HfO2/ZnO MOSCAPs were about ten times lower in those fabricated on Si3N4 substrates. (© 2014 WILEY-VCH Verlag GmbH &Co. KGaA, Weinheim)

Silicon Surface Passivation Technology for Germanium-Tin P-Channel MOSFETs: Suppression of Germanium and Tin Segregation for Mobility Enhancement

We report a two-step silicon (Si) surface passivation technology for germanium-tin (Ge1-xSnx) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs), featuring an initial low temperature atomic-layer-epitaxy or passivation step to suppress the segregation of subsurface germanium (Ge) and tin (Sn) atoms into the first monolayer of the ultrathin Si passivation layer. Evidence of reduced Ge and Sn segregation into the ultrathin Si passivation layer is provided by angle-resolved X-ray photoelectron spectroscopy (ARXPS) measurement. As compared to a Si passivation process performed at a higher temperature (370°C), the two-step Si passivation process gives ∼13% higher drive current in Ge0.94Sn0.06 pMOSFETs. It also achieved a high effective hole mobility μeff of 472 cm2/V·s at inversion carrier density Ninv of 1 × 1013 cm−2. The two-step Si surface passivation technology enables the formation of high-quality gate stack on Ge1-xSnx surface channel for high performance logic applications.

Determination of effective mobilities of EOF markers in BGE containing sulfated β‐cyclodextrin by a two‐detector method

A neutral marker of the EOF can gain a nonzero effective mobility because of its possible interaction with a charged complexing agent, such as a chiral selector in CE. We determined effective mobilities of four compounds often used as EOF markers (dimethyl sulfoxide, mesityl oxide, nitromethane, and thiourea) in the BGE-containing sulfated β-CD (60 g/L). All the compounds studied were measurably mobilized by their interaction with the selector. The highest effective mobility (-3.0·10(-9) m(2) s(-1) V(-1)) was observed for thiourea and the lowest (-1.5·10(-9) m(2) s(-1) V(-1)) for dimethyl sulfoxide and nitromethane. The mobilities were determined by a new two-detector pressure mobilization method (2d method), which we propose, and the results were confirmed by standard CE measurements. In the 2d method, one marker zone is situated in the BGE containing the charged selector, while the second marker zone is surrounded with a selector-free BGE, which prevents its complexation. The initial distance between the two marker zones equals the capillary length from the inlet to the first detector. After a brief voltage application, the final distance between the marker zones is determined based on known capillary length from the first to the second detector. The difference between these two distances determines the effective mobility.

Single‐Crystalline p‐Type Zn3As2 Nanowires for Field‐Effect Transistors and Visible‐Light Photodetectors on Rigid and Flexible Substrates

AbstractZn3As2 is an important p‐type semiconductor with the merit of high effective mobility. The synthesis of single‐crystalline Zn3As2 nanowires (NWs) via a simple chemical vapor deposition method is reported. High‐performance single Zn3As2 NW field‐effect transistors (FETs) on rigid SiO2/Si substrates and visible‐light photodetectors on rigid and flexible substrates are fabricated and studied. As‐fabricated single‐NW FETs exhibit typical p‐type transistor characteristics with the features of high mobility (305.5 cm2 V−1 s−1) and a high Ion/Ioff ratio (105). Single‐NW photodetectors on SiO2/Si substrate show good sensitivity to visible light. Using the contact printing process, large‐scale ordered Zn3As2 NW arrays are successfully assembled on SiO2/Si substrate to prepare NW thin‐film transistors and photodetectors. The NW‐array photodetectors on rigid SiO2/Si substrate and flexible PET substrate exhibit enhanced optoelectronic performance compared with the single‐NW devices. The results reveal that the p‐type Zn3As2 NWs have important applications in future electronic and optoelectronic devices.

High Performance Multilayer MoS2 Transistors with Scandium Contacts

While there has been growing interest in two-dimensional (2-D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancy due to the lack of a complete picture of their performance potential. The focus of this article is on contacts. We demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS(2) layers the excellent intrinsic properties of this 2-D material can be harvested. Using scandium contacts on 10-nm-thick exfoliated MoS(2) flakes that are covered by a 15 nm Al(2)O(3) film, high effective mobilities of 700 cm(2)/(V s) are achieved at room temperature. This breakthrough is largely attributed to the fact that we succeeded in eliminating contact resistance effects that limited the device performance in the past unrecognized. In fact, the apparent linear dependence of current on drain voltage had mislead researchers to believe that a truly Ohmic contact had already been achieved, a misconception that we also elucidate in the present article.

ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.

High-Performance Single Layered WSe2 p-FETs with Chemically Doped Contacts

We report high performance p-type field-effect transistors based on single layered (thickness, ~0.7 nm) WSe2 as the active channel with chemically doped source/drain contacts and high-{\kappa} gate dielectrics. The top-gated monolayer transistors exhibit a high effective hole mobility of ~250 cm2/Vs, perfect subthreshold swing of ~60 mV/dec, and ION/IOFF of >10^6 at room temperature. Special attention is given to lowering the contact resistance for hole injection by using high work function Pd contacts along with degenerate surface doping of the contacts by patterned NO2 chemisorption on WSe2. The results here present a promising material system and device architecture for p-type monolayer transistors with excellent characteristics.

Charge-Carrier Velocity Distributions in High-Mobility Polymer Dual-Gate Thin-Film Transistors

We report charge-carrier velocity distributions in high-mobility polymer thin-film transistors (PTFTs) employing a dual-gate configuration. Our time-domain measurements of dual-gate PTFTs indicate higher effective mobility as well as fewer low-velocity carriers than in single-gate operation. Such nonquasi-static (NQS) measurements support and clarify the previously reported results of improved device performance in dual-gate devices by various groups. We believe that this letter demonstrates the utility of NQS measurements in studying charge-carrier transport in dual-gate thin-film transistors.

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-κ Eu2O3 LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm2/V-s, a small subthreshold swing of 142 mV/decade, and a high Ion/Ioff current ratio of 1.34 × 107. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device.

Reserve accumulation and monetary sterilization in Singapore and Taiwan

Asian economies have embraced the globalization of production, trade and capital flows. One dimension of contemporary globalization has been the heavy exchange rate management by, and rapid and massive stockpiling of, foreign exchange reserves in Asia. This article undertakes an empirical investigation to assess the extent of de facto sterilization and capital mobility in Singapore and Taiwan using quarterly data between 1990 and 2008. Our empirical results suggest that, since, 2001 both Singapore and Taiwan have a high degree of – but not perfect – de facto capital mobility. To date, this high-effective capital mobility has not undermined the ability of the central bank in either economies to sterilize their respective foreign exchange intervention but may make the process increasingly difficult over time.

High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm2 V−1 s−1, small subthreshold slope of 269 mV dec−1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

InAs inserted InGaAs buried channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited gate dielectric

Performance improvement of InGaAs buried channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been achieved by inserting InAs layer and properly designing the inserted layer position. In0.7Ga0.3As and InAs channel buried channel MOSFETs were fabricated and analyzed including drive current, transconductance, effective mobility, and subthreshold swing. All InAs buried channel devices show good off-state and saturation property. By inserting InAs in the middle of InGaAs channel (InGaAs/InAs/InGaAs channel), 37% enhancement of high field effective channel mobility was achieved over devices with pure InGaAs channel. Devices with InAs inserted in the middle exhibits peak effective channel mobility around 6140 cm2/V s and subthreshold swing of 107 mV/dec.

High-Mobility TaN/$\hbox{Al}_{2}\hbox{O}_{3}$/Ge(111) n-MOSFETs With RTO-Grown Passivation Layer

We report the fabrication of high-electron-mobility Ge(III) n-MOSFETs using a novel and simple approach to passivate a Ge surface by rapid thermal oxidation (RTO). A thin interfacial GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer is formed by RTO, which passivates the high-k/Ge interface. The GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -passivated n-MOSFETs fabricated using a gate-first self-aligned process with high-k/metal gate demonstrate a high peak effective mobility (μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ~ 713 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> · V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> · s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) with ~2x enhancement over control Si(100) devices. Moreover, at a drain bias of 1 V and at a gate overdrive of 1.2 V, Ge MOSFETs (L ~ 75 μm) show a drive current of ~1.1 mA/ mm, which is ~1.6 X higher than that of the control Si devices. In addition, a good subthreshold slope of ~130 mV/decade and an Jon/-Toff ratio ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> were achieved using the GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer formed by RTO.

Highly Efficient Restoration of Graphitic Structure in Graphene Oxide Using Alcohol Vapors

Solution-based processes involving the chemical oxidation of graphite and reduction of the obtained graphene oxide (GO) sheets have attracted much attention for preparing graphene films for printed electronics and biosensors. However, the low electrical conductivity of reduced GO is still hindering the development of electronic applications. This article presents that GO sheets reduced by high-temperature alcohol vapors exhibit highly graphitic structures and excellent electrical conductivity. The sheet resistance of thin transparent films is lowered to ∼15 kΩ/◻ (>96% transparency). Field-effect transistors produced from these reduced GO sheets exhibit high effective field-effect hole mobility up to 210 cm(2)/V x s. Raman spectroscopic studies reveal that the conductivity enhancement in the low mobility regime is attributed to the removal of chemical functional groups and the formation of six-fold rings. In the high mobility regime, the growth of the graphitic domain size becomes dominant for enhancing its electrical conductivity. The excellent electrical conductivity of the reduced GO sheets promises potential electronic applications.

High-Performance Three-Terminal Fin Field-Effect Transistors Fabricated by a Combination of Damage-Free Neutral-Beam Etching and Neutral-Beam Oxidation

Three-terminal fin field-effect transistors (3T-FinFETs) were fabricated by neutral-beam oxidation (NBO) to form gate silicon dioxide (SiO2). The 3T-FinFET fabricated by NBO showed higher device performance – namely, a higher subthreshold slope and a higher effective mobility – than that fabricated by conventional thermal oxidation. It is considered that those improved subthreshold slope and mobility are due to the fact that the three-dimensional structure of a SiO2 film fabricated by NBO has a lower interfacial state density and a lower roughness than a similar structure fabricated by the conventional thermal oxidation of a SiO2 film. The reasons for the lower interfacial state density and lower roughness are the low temperature and lattice plane independence of NBO in comparison with conventional thermal oxidation processes.

High-performance CF4 plasma treated polycrystalline silicon thin-film transistors using a high-k Tb2O3 gate dielectric

In this letter, we have developed a high-k Tb2O3 gate dielectric polycrystalline silicon (poly-Si) thin-film transistors (TFTs) prepared under a CF4 plasma treatment. A high-performance TFT device that has a low threshold voltage of 0.89 V, a high effective carrier mobility of 59.6 cm2/V s, a small subthreshold swing of 212 mV/dec, and a high ION/IOFF current ratio of 8.15×106 can be achieved. This phenomenon is attributed to fluorine atoms into poly-Si films can effectively passivate the trap states near the Tb2O3/poly-Si interface. The fluorine incorporation also enhanced electrical reliability of the Tb2O3 poly-Si TFT. All of these results suggest that the CF4 plasma-treated poly-Si Tb2O3 TFT is a good candidate for high-performance TFTs.

An investigation of the electrical and optical properties of thin iron layers grown on the epitaxial Si(111)-(2 × 2)–Fe phaseand on an Si(111)7 × 7 surface

Electrical and optical properties of thin iron layers grown at room temperature on the epitaxial silicide Si(111)-(2 × 2)–Fe phaseand on an Si(111)7 × 7 surface were investigated using in situ Hall effect registration, atomic forcemicroscopy, and optical spectroscopy. It was established that Si(111)-(2 × 2)–Fe phase has semiconducting properties with a 0.99 eV effective band gapand acts as a diffusion barrier for the deposited iron atoms, preventingintermixing with the substrate at room temperature. Peculiarities in theoptical spectra of a sample with a 2 nm iron film grown on the Si(111)-(2 × 2)–Fe phase typical for both metal and semiconducting natures prove a conservationof the phase under the iron layer. The process of iron growth on the Si(111)-(2 × 2)–Fe phase is accompanied by the development of high stress in the subsurface arearesulting in band dispersion changes. Apparently the tension reaches a maximum at aniron layer thickness of 1.35 nm, and a high effective hole mobility equal to 820 cm2 V−1 s−1 was registered.