High Temperature Reverse Bias Research Articles

Design and experimental verification of a novel high-reliability variation of lateral doping (VLD) termination

Abstract A novel two-dimensional mesh-like variation of lateral doping (VLD) termination (M-VLD) is proposed, which modifies the conventional ring-shaped track VLD termination (R-VLD) mask into an interconnected mesh-like structure. The comparative simulations and experiments show that M-VLD can achieve better blocking capability and reliability than R-VLD. Vertical double diffusion MOSFET (VDMOS) with M-VLD achieves a maximum breakdown voltage ( B V max ) of 1588 V, which is 62 V higher than that of VDMOS with R-VLD. Furthermore, the devices with M-VLD exhibit lower leakage currents in 150 °C reverse-biased I − V test and successfully pass 1000 h-125 °C-1200 V high-temperature reverse bias (HTRB) test, while the devices with R-VLD fail to pass both tests.

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

Superjunction Reliability Analysis Under Extreme High Positive and Negative Gate Voltage Stress

High gate stress test is an extremely important part of power device reliability test. On this basis, a 650 V super junction device is designed and fabricated, conventional stress test including high temperature gate bias (HTGB), high temperature reverse bias (HTRB) test results show that the device possess good reliability. The degradation of performance parameters under extreme high gate stress (including positive and negative) and the corresponding mechanism is further studied. It is found that the main performance parameters of superjunction MOSFET (SJ-MOSFET) will change significantly when the gate voltage stress is greater than 70 V. Under the positive high gate voltage stress, the threshold voltage decreases significantly. Under the negative high gate voltage stress, the threshold voltage also shifted to the left. Comparing the device under the same value of positive and negative high gate stress, it is found that the degradation degree of the device under positive stress is far greater than that under negative stress. Theoretical analysis combined with experimental data believes that the two degradation mechanisms are different. For positive stress, tunneling electrons collide on their way to the gate electrode creating electron–hole pairs, and the holes are captured by traps. But for negative gate voltage, holes tunnel and serve as extra gate positive charge directly. The electron injection efficiency is much higher than hole injection efficiency. Besides, the n-type region is larger at the bottom of the gate. Simultaneously, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{C}$</tex-math> </inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}$</tex-math> </inline-formula> measurement is also taken to prove the hypothesis.

Advanced Power Cycling Test Integrated With Voltage, Current, Temperature, and Humidity Stress

In this article, an advanced power cycling test with high voltage, large current, high temperature, and high humidity stress is proposed to get closer to the actual working conditions of power electronics in the accelerated aging test. The proposed test, integrated with High-Voltage High Humidity High Temperature Reverse Bias Test (HV-H3TRB) and standard DC Power Cycling Test (PCT), achieves precise measurement at the microsecond, millivolt, and microampere accuracy. A 6-kV/750-A prototype is built to verify the feasibility and effectiveness, and the noise mitigation method for measurement under high voltage is analyzed. The proposed test was carried out on the full-bridge power modules for electric vehicles, and the lifetime exhibits lower than the standard PCT. The root cause is the increment of thermal resistance at an early stage due to moisture invasion, which results in a failure mode change. Finally, the electrochemical corrosion signs induced by sulfur/carbon under voltage, temperature, and humidity stress are also revealed by optical inspection and Scanning Electron Microscope (SEM).

Investigation on the threshold voltage instability mechanism of p-GaN gate AlGaN/GaN HEMTs under high-temperature reverse bias stress

In this Letter, threshold voltage instability of p-GaN gate AlGaN/GaN HEMTs under high-temperature reverse bias (HTRB) stress has been investigated in detail. The experimental results show that the threshold voltage increases by 0.62 V after 100 ks stress at 200 °C. Especially, the degradation phenomenon is unrecoverable. A deep-level transient spectroscopy (DLTS) technique is used to characterize the defect evolution process during the stress. Two kinds of electron traps within the p-GaN layer were proposed to explain the degradation, which were generated by the injected high-energy electrons from the gate electrode. One is referred to as fixed charge trap, and another is trap E3 (EC-0.7 eV). With the aid of high temperature, more electrons are injected and trapped in the fixed charge trap, which causes the permanent threshold voltage increase. In addition, the concentration and capture cross section of trap E3 were extracted as well, which are considered to dominate the recoverable degradation of the device due to the relatively shallower energy level.

Optimal impurity distribution model and experimental verification of variation of lateral doping termination

Based on the charge balance principle, an optimal impurity distribution variation of lateral doping termination (OID-VLD) and its ion-injection mask design method are proposed and verified. The comparative simulations and experiments show that OID-VLD can achieve better blocking ability and reliability than the traditional VLD (T-VLD). Vertical double diffusion MOSFET (VDMOS) with OID-VLD achieved breakdown voltage (BV) of 1684 V and passed the 168 hours 100 °C–110 °C–120 °C–125 °C high-temperature reverse bias (HTRB) test, while VDMOS with T-VLD obtained BV of 1636 V and failed in the 20 hours 120 °C HTRB test.

High temperature reliability and performance evaluation of 1200 V SiC MOSFETs

Reliability characteristics play a critical role in studied of SiC MOSFETs, including gate oxygen, long-term and short circuit reliability. This article presents a long-term reliability and device high temperature performance. Firstly, the static performance evaluation of the device at high temperature is introduced. Next, the gate bias test induces the threshold voltage shift, arguing that the instability is due to the capture of electrons by the SiC/SiO2 interface traps and the gate dielectric near-interface traps. Finally, the reliability characterization is verified using the common methods of high temperature reverse bias and high temperature gate bias tests. The results exhibit the superior reliability and performance of 1200 V SiC MOSFETs.

Influence of Humidity on the Power Cycling Lifetime of SiC MOSFETs

Power cycling test (PCT) is widely used to accelerate power semiconductor device aging and assess its packaging reliability. Standard PCT only considers thermomechanical stress and neglects the effect of humidity from the environment. In this article, the power cycling lifetime of three groups [Group 1: devices under test (DUTs) preaged with 3600-h high-voltage high-humidity high-temperature reverse bias test (HV-H3TRB), Group 2: DUTs preaged with 3600-h high-temperature high-humidity storage, and Group 3: DUTs without preaging] is compared to explore the contribution of high humidity and high voltage. The results show that Groups 1 and 2 have a shorter lifetime, and the shape factor of Group 2 in Weibull analysis drops below 1, indicating that a sign of infant mortality and moisture is the root cause. After decapsulation, optical inspection, and scanning electron microscope (SEM), it is found that the bubbles form at edge termination, and the corrosion signs of moisture appear on the chip surface and bond wire in DUTs of Groups 1 and 2. This phenomenon is caused by the elements of C, O, and Si migration and deposition on the bond wire, which radically come from epoxy molding compound (EMC) and finally result in a shorter power cycling lifetime of discrete silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs).

Experimental investigation of PCB embedded 1200 V IGBT/diode power pre-package under high-humidity high-temperature reverse voltage bias

PCB embedding is an attractive packaging technology for highly integrated future power systems. Electrical and thermal benefits and limitations are well understood, but only few publications focus on reliability. Here we are addressing high-humidity high temperature reverse bias (H3TRB) tests, which are performed to gain deeper understanding of the limitations of this technology. Cu filament growth is observed on both, PCB embedded samples and silicone potted reference samples. These filaments may form a conductive path and lead to an increased leakage current in blocking mode. Electrochemical corrosion of the Cu-plated guard ring is identified as root cause.

Study of the influence of gate etching and passivation on current dispersion, trapping and reliability in RF 0.15 μm AlGaN/GaN HEMTs

In this paper we examine the effect of passivation and gate etching processes on the current dispersion and reliability of AlGaN/GaN HEMTs for RF applications. We compared the performance of HEMTs with a standard gate etching and passivation processes (reference wafer) with the performances of HEMTs with improved etching process (etching variant wafer) and improved passivation process (passivation variant wafer). In order to study the trapping behavior, we performed dispersion measurements in off-state conditions and drain current transients (DCT) and we found that:1)The use of improved passivation process determines a decrease of current dispersion, in particular at the knee voltage, where current collapse depends on both threshold voltage and on-resistance variation,2)The trapping process linked to surface states is influenced by the gate etching and passivation processes; the use of improved passivation slows down the trapping/de-trapping kinetics, resulting in a lower impact on dynamic performance.The study of reliability is based on high-temperature reverse bias (HTRB) stresses. The gate-drain diodes are biased in the same voltage stress conditions (VGS,Stress = -7 V, VDS,Stress = 50 V) at high temperatures (175 °C) for 24 h. We demonstrated that the improved passivation limits the increase of gate leakage current during HTRB stress and prevents the belly shape effect linked to the presence of donor traps in the surface between SiN and GaN cap.We performed gate step stress increasing the negative voltage applied to the Schottky contact. The electroluminescence images performed during the stress show spots along the gate finger that are the responsible of the failure of the devices. The results presented in the paper provide information on the optimization of GaN HEMTs for RF applications.

Embedded systems and printed circuit boards as weak spots in HV-H3TRB tests

Wide-band-gap (WBG) devices and embedding technology offer a huge advantage when increasing the power density of power electronics. However, the miniaturisation leads to new reliability challenges. The critical spot prone to humidity degradation moves outside the actual device under test (DUT) to the periphery, i.e. printed circuit board assemblies (PCBA). In the case of High Voltage Embedding Technology (HVET) devices, the housing of the power element is completely omitted. The materials used in HVET must entirely ensure the moisture protection of the power unit and the passive components of the embedded systems.In this work, results on various batches of PCBA and HVET after several thousand hours of testing in High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) are presented. Failure analyses have identified degradation mechanisms such as conductive anodic filament (CAF) formed inside the FR-4 printed circuit boards (PCB) and anodic migration phenomenon (AMP) in HVET devices as the root cause of failures. Therefore, special preventive procedures are required in harsh climatic conditions.

Optimization of the Field Plate Design of a 1200 V p-GaN Power High-Electron-Mobility Transistor.

This study optimized the field plate (FP) design (i.e., the number and positions of FP layers) of p-GaN power high-electron-mobility transistors (HEMTs) on the basic of simulations conducted using the technology computer-aided design software of Silvaco. Devices with zero, two, and three FP layers were designed. The FP layers of the HEMTs dispersed the electric field between the gate and drain regions. The device with two FP layers exhibited a high off-state breakdown voltage of 1549 V because of the long distance between its first FP layer and the channel. The devices were subjected to high-temperature reverse bias and high-temperature gate bias measurements to examine their characteristics, which satisfied the reliability specifications of JEDEC.

N2O plasma treatment effect on reliability of p-GaN gate AlGaN/GaN HEMTs

This work investigates the effect of N2O plasma treatment on the reliability of p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs), specifically in the AlGaN drift region. The formation of a GaON/AlON compound layer on the AlGaN surface after N2O plasma treatment was confirmed by energy-dispersive x-ray spectroscopy mapping and x-ray photoelectron spectroscopy analysis. When a device is under highly stressed conditions, the compound layer reduces the number of negatively charged interface traps and protects the AlGaN surface by hindering the Ga-out diffusion. The high temperature reverse bias reliability test demonstrated that the N2O plasma treatment enhanced the reliability of p-GaN gate HEMTs by suppressing the degradation of the on-resistance from 18.7% to 9.0%, after being subjected to a high drain bias (VDS = 700 V) at 200 °C for 1000 s.

Time-Resolved Threshold Voltage Instability of 650-V Schottky Type p-GaN Gate HEMT Under Temperature-Dependent Forward and Reverse Gate Bias Conditions

A research on time-resolved threshold voltage instability of 650-V Schottky type p-GaN gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> N/GaN high electron mobility transistor (HEMT) under high-temperature gate bias (HTGB) conditions has been carried out. Both forward and reverse bias conditions are applied. We found that the threshold voltage of p-GaN AlGaN/GaN HEMT shifts negatively under high-temperature forward gate bias (HTFB), while shifts positively under high-temperature reverse gate bias (HTRB). Negative threshold voltage shifts under forward gate bias are largely due to the trapped positive charges (holes) caused by existing defects in the AlGaN layer. The holes are from the accumulated 2-D hole gas (2DHG) in the p-GaN layer near the p-GaN/AlGaN interface, which may be partially filled into the AlGaN layer by tunneling effect. Therefore, negative threshold voltage shifts under HTFB are temperature-independent. Positive threshold voltage shifts under reverse gate bias are from the hole emission in the p-GaN layer and the trapped negative charges (electrons) in the AlGaN layer. The electrons are trapped by defects resulted from the created hot holes in high temperature. The positive threshold voltage shift under HTRB is temperature-dependent, where higher temperature leads to a larger positive threshold voltage shift.

JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs

650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (Ron,sp) of 2.06 mΩ · cm2 (further reducible through tighter layout design) while having a narrow JFET region for device reliability.

(Invited) Vertical Gallium Nitride PN Diodes for Grid Resiliency and Medium-Voltage Power Electronics

Due to their fast avalanche breakdown response, gallium nitride (GaN) diodes with vertical device geometry hold promise for protection of the electric grid against fast (<1 us) voltage transients induced by electromagnetic pulses (EMPs). Additionally, comparable critical electric field and superior mobility relative to silicon carbide (SiC) suggest that vertical GaN devices compare favorably to SiC for medium-voltage (defined here as 1.2 to 20 kV) power electronics, with the advantage becoming more pronounced as the voltage rating exceeds 10 kV. However, vertical GaN power devices are significantly less mature than their SiC counterparts, and further work on epitaxial growth, characterization of fundamental material properties, device processing, manufacturability, and reliability / failure analysis is needed. This talk will describe our team’s efforts to advance the state-of-the-art for vertical GaN PN diodes. One key challenge is the growth of thick (tens of um), controllably low-doped (<1016 cm-3) drift layers on native GaN substrates by metal-organic chemical vapor deposition (MOCVD), and our team has achieved >50 um thick layers with net doping in the low-1015 cm-3 range suitable for medium-voltage devices. Additionally, significant challenges exist in the processing of such devices, notably in the edge termination used to prevent premature breakdown. Using the aforementioned drift layers coupled with a multi-step-etched junction termination extension (JTE), our team has demonstrated PN diodes with breakdown voltage >4 kV and specific on-resistance <4 mOhm cm2. Future work aims to extend the growth and fabrication such that devices up to 20 kV breakdown are achieved. Additionally, a parallel foundry effort aiming to establish the manufacturability of vertical GaN technology, focused thus far on 1.2-kV-class devices, has performed extensive metrology on incoming epitaxial GaN wafers prior to fabrication of PN diodes with areas ranging from ~0.1 up to 1 mm2. Using various combinations of implanted guard rings and JTEs as the edge termination, devices with breakdown voltages >1.2 kV have been achieved, and the yield has been evaluated based on a combination of both breakdown voltage and the forward current characteristic. The foundry effort will be extended to 3.3 and later 6.5 kV devices, possibly using alternative edge termination approaches such as bevels that are currently under development. Further, in order to understand the fundamental degradation mechanisms in vertical GaN devices and ultimately to mitigate them, extensive reliability testing of 1.2-kV-class vertical GaN PN diodes has been underway, including tests such as high-temperature reverse bias and high-temperature operating life. Such testing has revealed several distinct degradation behaviors, and failure analysis has been performed on select devices to determine the root cause(s) of degradation and/or failure. Finally, a transmission-line-based setup has been used to quantify the time response of the avalanche breakdown of 1.2-kV-class GaN PN diodes to determine whether it is fast enough for the diodes to be used for protection of the grid against EMPs, and the measured breakdown time of ~1 ns is indeed sufficient for such an application. This work was supported by the ARPA-E OPEN+ Kilovolt Devices Cohort directed by Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Improved HV-H3TRB robustness of a 1700 V IGBT chip set in standard power modules

High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) is the standard to test power modules for humidity driven degradation. This test has contributed significantly to detect and fix weak points in device designs, especially of the junction termination. Thus, the latest junction termination designs offer unprecedented humidity robustness. This work reports on a comparative HV-H3TRB test on 1.7 kV IGBT modules with chips sets of two consecutive generations tested at two different test voltages each. The progress in the chip design and material composition provides more than an order of magnitude better performance in HV-H3TRB. Failure analyses have indicated vastly reduced degrees of aluminium corrosion in the junction termination area, leading to a slowed down failure mechanism.

Assembly Reliability and Molding Material Comparison of Miniature Integrated High Power Module With Insulated Metal Substrate

Abstract Given the increasing demand for power density and lightweight specifications, the discrete transistor outline-type package is no longer sufficient for personal vehicle. The new generation of high-power drive needs excellent heat dissipation and miniaturized system simultaneously. However, a traditional architecture of power module, direct bonding copper substrate, has serious warpage deformation and limitation of the heat dissipation. Therefore, a power module with an insulated metal substrate (IMS) is proposed. The proposed power module has a smaller volume, better electrical and thermal performance, and high reliability to be utilized in personal vehicles. A fine-quality assembly process is also presented and verified. Furthermore, two different kinds of molding materials that are widely used in power modules, silicone gel, and epoxy, are utilized. The IMS-type module with silicone gel molding fails the temperature cycling test (TCT) with the delamination of the solder layer. The module with epoxy successfully passes the automotive-grade reliability tests, including TCT, highly accelerated stress test, high-temperature reverse bias, and intermittent operational life test according to the standard of AEC-Q101. The finite element analysis for the IMS power module is presented and analyzed under the condition of TCT to estimate the mechanical behavior of the solder layer. The equivalent plastic strain of solder layer with silicone gel and epoxy is 0.76 and 0.08, respectively, after TCT, separately. The main reason can be attributed to the coefficient of thermal expansion between the IMS and molding material. According to the analyzed results, the effect of molding material should not be ignored in the power modulus.

Influence of high temperature reliability test of 1200V SiC MOSFET on static parameters

The gate oxide interface state of SiC MOSFET is the main factor that affects the high temperature reliability of the device. Therefore, the high temperature reliability test of planar gate depleted 1200V20A SiC MOSFET is carried out in this paper. The relationship between leakage current and temperature is studied by comparing the change process of leakage current and temperature in the initial stage of high temperature gate bias and high temperature reverse bias. After the HTGB and HTRB test, the threshold voltage and on resistance are measured at room temperature. The influence of the HTGB test and HTRB test on device parameters is further analyzed, and the relationship between them is revealed.