Higher Static Noise Margin Research Articles

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18 nm technology.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

SummaryAs the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Many researchers are trying to create a low power, high stability, and high-speed static random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 transistors (12 T) developed by carbon nanotube field-effect transistor (CNTFET) to support such an endeavor and be a milestone in creating a better SRAM cell. The proposed 12 T CNTFET SRAM cell is a modified Schmitt-trigger (ST)-based SRAM cell design. The ST-based SRAM cell feedback-cutting and single-ended read decupled techniques are introduced to improve the SRAM cell’s static noise margin (SNM) and access time. The presence of stacked N-CNTFETs reduces the proposed cell’s power consumption. In addition to conventional 6 T [9] and 8 T [10] SRAM cells, it has been compared with some of the existing SRAM cells such as 12 T SRAM [11], 12 T SRAM [12], 12 T SRAM [13] and 12 T SRAM [14], for calculating the relative performance of the proposed 12 T CNTFET SRAM cell design in terms of fundamental design metrics. The simulation results at 0.9 V show that compared to the afromentioned bit cells, the proposed design accomplishes low power consumption while writing, reading, and holding modes of operation. It has a high SNM during all the operations. The proposed cell has the least read access time. The power, SNM, and access time performance of the bit cells are evaluated for the variation of CNTFET parameters and reported in this article. The proposed cell is also implemented using MOSFET, and the performance of MOSFET and CNTFET is compared. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model.

Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology

A novel 7T carbon nanotube field effect transistor (CNTFET)-based static random-access memory (SRAM) cell is proposed in this paper. Power and noise margin performances of the proposed SRAM cell is observed for write, hold and read operations. The power consumption and noise margin of the proposed SRAM cell is compared with the conventional 6T and 8T CNTFET-based SRAM cells. From the simulation, it is noted that the proposed 7T SRAM cell consumes lesser power and offers high static noise margin (SNM) compared to that of conventional 6T and 8T SRAM cells. The introduction of diode-based transistor structure improves the power and noise performance of the proposed SRAM cell. The effect of variation of parameters such as gate oxide thickness, dielectric constant, pitch, temperature, number of carbon nanotubes (CNT) and supply voltage on power and noise performance of proposed 7T SRAM cell is studied. Simulations were carried out with HSPICE simulation tool using Stanford University 32-nm CNTFET model.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High-Performance, Low-Power Flexible Ternary Logic Circuits.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.

Performance Evaluation of Negative-Capacitance Fin-Type Field Effect Transistor-Based Static Random-Access Memory with Mixed-Mode Simulation

Electrical characteristics of fin-type field-effect transistor with negative capacitance effect (NCFinFET) are investigated coupled with the Landau-Khalatnikov equation for ferroelectric materials in this study. Moreover, Technology Computer Aided Design (TCAD) mixed-mode simulation is carried out to evaluate and compare the performance of NCFinFET-based static random access memory cell (NC-SRAM) with a traditional FinFETbased SRAM one. It is shown NC-SRAM has higher static noise margin (SNM) and better anti-interference capability than conventional SRAM with the same supply voltage. The static read, hold, and write noise margins (RSNM, HSNM, and WSNM, respectively) for NC-SRAM increased by 10%, 30%, and 15%, respectively, and the access disturb stability improved by 80%. Simulation results also reveal that the read stability increases with increasing ferroelectric layer thickness, while the write stability exhibits a non-monotonic trend with ferroelectric layer thickness for NC-SRAM.

(Invited) 3D Monolithic Integration in Flexible Organic Printed Transistors

Despite the significant enhancements in material properties such as carrier mobility, few attempts have been made to print organic integrated circuits (ICs). The relatively large size of printed features (typically 10 μm – 100 μm) have limited the implementation of organic ICs with reasonable transistor densities. To overcome the limitation, we introduce three-dimensional (3D) integration of inkjet-printed organic transistors and circuits. We fabricated a p-type organic field-effect transistor that is inkjet-printed on top of an n-type organic field-effect transistor with a shared gate joining the two transistors. Based on the common-gate transistor-on-transistor structure, a complementary inverter array is fabricated with a high static noise margin and reliable characteristics. We have further developed 3D integration of a dual-gate NAND technology fabricated by printing technique with a demonstration of flexible logic circuits. The vertical stacking of independent-gate controlled dual gate transistors offers enhanced on-current, lowered sub-threshold swing, increased device stability and density. The present study fulfills the essential requirements for the fabrication of organic printed complex ICs, and the findings can be applied to realize more complex digital/analogue ICs and intelligent devices

A Novel concept on 8-Transistor Dynamic Feedback Control on Static RAM Cell Array

A novel idea of 8-Transistor (8T) static random access memory cell with enhanced information stability, sub threshold operation may be outlined. Those prescribed novel built single-ended for dynamic control 8 transistors static RAM (SRAM) cell enhances the static noise margin (SNM) to grater low energy supply. The suggested 8T takes less read and write power supply compared to 6T. Those suggested 8T need higher static noise margin than that from 6T. The portable microprocessor chips need ultralow energy consuming circuits on use battery to more drawn out span. The power utilization might be minimized utilizing non-conventional gadget structures, new circuit topologies, and upgrading the architecture. Although, voltage scaling require of the operation completed over sub threshold for low power consumption, and there will be an inconvenience from exponential decrease in execution. However, to sub threshold regime, that data stability of SRAM cell might a chance to be a amazing issue and worsens for those scaling from claming MOSFET ought to sub-nanometer engineering technology.

Vertically Stacked Complementary Organic Field‐Effect Transistors and Logic Circuits Fabricated by Inkjet Printing

Vertically stacked complementary organic field-effect transistors and logic circuits are fabricated by inkjet printing. Based on a common-gate transistor-on-transistor structure, a complementary inverter array is demonstrated with a high static noise margin and reliable characteristics. This study reports a general strategy to continuously increase the transistor density of printed devices.

Solution-Processed Vertically Stacked Complementary Organic Circuits with Inkjet-Printed Routing.

The fabrication and measurements of solution‐processed vertically stacked complementary organic field‐effect transistors (FETs) with a high static noise margin (SNM) are reported. In the device structure, a bottom‐gate p‐type organic FET (PFET) is vertically integrated on a top‐gate n‐type organic FET (NFET) with the gate shared in‐between. A new strategy has been proposed to maximize the SNM by matching the driving strengths of the PFET and the NFET by independently adjusting the dielectric capacitance of each type of transistor. Using ideally balanced inverters with the transistor‐on‐transistor structure, the first examples of universal logic gates by inkjet‐printed routing are demonstrated. It is believed that this work can be extended to large‐scale complementary integrated circuits with a high transistor density, simpler routing path, and high yield.

Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio

Low Power High Static Noise Margin with Material Parameter of SRAM Cell Design Considering Nano-Scaled Technology and Transistor Ratio

A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments

CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35μm standard CMOS process. The prototype chips are adapted to work with frequencies up to 80MHz, power supply voltages from 2.9V to 3.3V and temperatures from 0°C to 60°C. The single event latchup (SEL) tolerance is improved from 5.2MeVcm2/mg to above 56MeVcm2/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

Junctionless 6T SRAM cell

The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 µA along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

Low-Power Logic Circuit and SRAM Cell Applications With Silicon on Depletion Layer CMOS (SODEL CMOS) Technology

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (/spl tau//sub pd/) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V/sub dd/. It is also confirmed that about 30% better power-delay product can be realized at the same /spl tau//sub pd/ with reduced V/sub dd/ in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of /spl sim/95 mV at V/sub dd/=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for /spl alpha/-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).

SMT: today and tomorrow : Susumu Suzuki. J. Electron. Engng Japan, 40 (February 1988)

CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35 μm standard CMOS process. The prototype chips are adapted to work with frequencies up to 80 MHz, power supply voltages from 2.9 V to 3.3 V and temperatures from 0 °C to 60 °C. The single event latchup (SEL) tolerance is improved from 5.2 MeV cm2/mg to above 56 MeV cm2/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.