High-speed Serial Transmission Research Articles

Low-Latency Ultra-Wideband High-Speed Transmission Protocol Based on FPGA

Aiming at the shortcomings of current high-speed serial transmission protocol including high latency and low effective transmission bandwidth, this paper designs a low-latency, ultra-wideband high-speed serial transmission protocol based on FPGA. Based on homologous system clock, data scrambling and synchronous frame synthesis are used to complete the data integration, so as to increase the effective bandwidth of data transmission. The receiving end reduces the data transmission latency by using the internal logic of FPGA and the buffer pool built by the register group together with status machine. The protocol is simple and universal, which can be applied to the FPGA platform of any OEM. Experiments show that the protocol can effectively reduce data transmission latency, improve the effective bandwidth of data transmission, and monitor the health and error code status of each data transmission channel in real time.

Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction

Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction

Application of High Speed Serial Data Transmission System in Remote Sensing Camera

In order to meet the system needs of miniaturization, real-time, high-speed data and high reliability transmission in remote sensing camera, a high-speed serial protocol based on high-speed serial/parallel converter SerDes is proposed. For the SerDes high-speed serial data transmission chip for the physical layer, FPGA for the link layer of the communication system, design high-speed serial transmission communication protocol. Through the development of a simplified protocol for the upper user to provide a simple data interface. The system completed the data rate of 12.5Gbps point to point high-speed transmission. Verification is done by sending a pseudo-random code between boards. System work 3 hours, the measured bit error rate is less than 10 -12 .

Line coding methods for high speed serial links

A line coding for high speed serial transmission is defined by two major characteristics: the maximum guaranteed run length (RL) which is the number of consecutive identical bits, and the running disparity (RD or DC-Balance) which is the difference between the number of 'zeroes' and 'ones' in a frame. Both should be bounded to a certain limit, RL to ensure reliable clock recovery and RD to limit baseline wander. Another important parameter is the overhead predictability. This parameter may be critical for applications that need a regular synchronization but for other applications, especially if the variable transfer rate is handled by the upper layer protocol, a statistical value of this parameter is good enough. In this paper, we propose two programmable line codings which bound RL and RD with fixed or variable overhead. The resulting overhead for the line coding we propose is shown to be the lowest among the existing methods, as much as to 10 times lower than well-known encoding methods. The fixed overhead line coding is based on a generalization of the polarity bit approach and can be dynamically adapted to link quality and the environment. First we propose a line coding which bounds the RL, and then we propose another one which bounds the RD. We end up by combining both methods to build a DC-balanced and Run Length limited line coding.

A <formula formulatype="inline"><tex Notation="TeX">${0.35}~\mu{\rm m}$</tex></formula> Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links

This paper presents a low power switchable current mode driver/receiver I/O pair for high speed serial transmission of asynchronous address event representation (AER) information. The sparse nature of AER packets (also called events) allows driver/receiver bias currents to be switched off to save power. The on/off times must be lower than the bit time to minimize the latency introduced by the switching mechanism. Using this technique, the link power consumption can be scaled down with the event rate without compromising the maximum system throughput. The proposed technique has been implemented on a typical push/pull low voltage differential signaling (LVDS) circuit, but it can easily be extended to other widely used current mode standards, such as current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL). A proof of concept prototype has been fabricated in 0.35 μm CMOS incorporating the proposed driver/receiver pair along with a previously reported switchable serializer/deserializer scheme. At a 500 Mbps bit rate, the maximum event rate is 11 Mevent/s for 32-bit events. In this situation, current consumption is 7.5 mA and 9.6 mA for the driver and receiver, respectively, while differential voltage amplitude is ±300 mV. However, if event rate is lower than 20-30 Kevent/s, current consumption has a floor of 270 μA for the driver and 570 μA for the receiver. The measured ON/OFF switching times are in the order of 1 ns. The serial link could be operated at up to 710 Mbps bit rate, resulting in a maximum 32-bit event rate of 15 Mevent/s . This is the same peak event rate as that obtained with the same SerDes circuits and a non-switched driver/receiver pair.

高速デジタル回路におけるチップ部品パッド直下のグラウンドクリアランスサイズの簡易計算式の提案

In recent years, PCI Express and USB have become established as high-speed serial transmission methods, reaching speeds of 5–10 Gbps and showing remarkable progress. As a result, several new design techniques for high-speed digital circuits have been recommended for printed circuit boards (PCB) by device makers. However, in order to adopt the actual designs, it is necessary to grasp their e ects and detailed mechanisms. We focused on a technology which removes the copper on the ground plane beneath the chip component pad, and veri ed the e ect. Design methods corresponding to the layer constitution and the material of the printed circuit board are proposed. e S-parameter, current distribution, and emission characteristics are analyzed by means of an electromagnetic eld analysis simulator (Sonnet EM) of the method-of-moment. In addition, the S-parameter of the test board was measured and the e ect was veri ed.

An Implementation of High-speed Serial Transmission by RocketIO Used on SAR System

Synthetic Aperture Radar is an efficient method of remote sensing.In the real-time processing system of Synthetic Aperture Radar,the high-speed data transmission is the emphases and the difficulty all the while.Aiming at the RocketIO Tranceiver module of Xilinx Virtex-Ⅱ PRO FPGA,This paper designs a high-speed serial I/O PCB board used on SAR data transmission system.This board uses RocketIO module in the chip fully,BREFCLK differential input reference clock,8B/10B decoder and pre-emphasis technology etc;implements one RocketIO transmission at 3.125 Gb/s and multi-channel high-speed serial interconnection.It is reliable through validated by actual system.The results of simulation and experimentation on the hardware circuit prove this method is efficient.and can reduce the design's complexity and board size very well.

A high speed low jitter LVDS output driver for serial links

A high speed, low jitter low voltage differential signaling (LVDS) output driver for high speed serial transmission is presented. Based on the comparison among four typical output driver architectu...

Experiences with ATM in a multivendor pilot system at Forschungszentrum Julich

The ATM technology for high speed serial transmission provides a new quality of communication by introducing novel features in a LAN environment, especially support of real time communication, of both LAN and WAN communication and of multimedia streams. In order to evaluate ATM for future DAQ systems and remote control systems as well as for a high speed picture archiving and communications system for medical images, Forschungszentrum Julich has build up a pilot system for the evaluation of ATM and standard low cost multimedia systems. It is a heterogeneous multivendor system containing a variety of switches and desktop solutions, employing different protocol options of ATM. The tests conducted in the pilot system revealed major difficulties regarding stability, interoperability and performance. The paper presents motivations, layout and results of the pilot system. Discussion of results concentrates on performance issues relevant for realistic applications, e.g., connection to a RAID system via NFS over ATM.